CN109427544B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN109427544B
CN109427544B CN201710778300.6A CN201710778300A CN109427544B CN 109427544 B CN109427544 B CN 109427544B CN 201710778300 A CN201710778300 A CN 201710778300A CN 109427544 B CN109427544 B CN 109427544B
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CN109427544A (zh
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朱占魁
张芳余
史运泽
赵鹏
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

本申请公开了一种半导体器件的制造方法，涉及半导体技术领域。所述方法包括：提供衬底结构，所述衬底结构包括：衬底，包括第一区和第二区；以及在所述第一区上用于第一器件的第一栅极结构；在所述衬底结构的表面上形成刻蚀保护层；在所述第二区上方的刻蚀保护层上形成掩模层，所述掩模层包含聚合物；执行干法刻蚀，以使得所述第一栅极结构两侧的第一区被刻蚀以形成第一凹陷，并使得所述第一栅极结构的表面上的刻蚀保护层被去除；去除所述掩模层，以形成半导体结构；利用光对所述半导体结构进行照射；执行湿法刻蚀，以将所述第一凹陷形成为第二凹陷。本申请可以减小聚合物的残留对器件性能的影响。

Description

半导体器件的制造方法
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件的制造方法。
背景技术
在集成电路的制造过程中，各种原因都可能造成聚合物的残留，而聚合物的残留会影响器件的性能。随集成电路制造工艺的发展，器件的关键尺寸越来越小，聚合物的残留对器件的性能影响也越发明显。
因此，有必要提出一种技术方案，能够减小聚合物的残留对器件性能的影响。
发明内容
本申请的一个目的在于减小聚合物的残留对器件性能的影响。
根据本申请的一方面，提供了一种半导体器件的制造方法，包括：提供衬底结构，所述衬底结构包括：衬底，包括第一区和第二区；以及在所述第一区上用于第一器件的第一栅极结构；在所述衬底结构的表面上形成刻蚀保护层；在所述第二区上方的刻蚀保护层上形成掩模层，所述掩模层包含聚合物；执行干法刻蚀，以使得所述第一栅极结构两侧的第一区被刻蚀以形成第一凹陷，并使得所述第一栅极结构的表面上的刻蚀保护层被去除；去除所述掩模层，以形成半导体结构；利用光对所述半导体结构进行照射；执行湿法刻蚀，以将所述第一凹陷形成为第二凹陷。
在一个实施例中，所述第一器件包括MOS器件。
在一个实施例中，所述MOS器件包括PMOS器件。
在一个实施例中，所述方法还包括：在所述第二凹陷中外延生长SiGe。
在一个实施例中，在所述第二凹陷中外延生长SiGe之前，还包括：利用光对所述第二凹陷进行照射。
在一个实施例中，所述衬底结构还包括在所述第二区上用于第二器件的第二栅极结构。
在一个实施例中，所述第二器件包括NMOS器件。
在一个实施例中，所述光包括激光。
在一个实施例中，所述激光的波长大于380nm。
在一个实施例中，所述激光的波长范围为10nm至380nm。
在一个实施例中，所述激光的波长小于10nm。
在一个实施例中，所述激光包括第一激光、第二激光和第三激光中的多个；所述第一激光的波长大于380nm；所述第二激光的波长范围为10nm至380nm；所述第三激光的波长小于10nm。
在一个实施例中，所述方法还包括：在去除所述掩模层后，执行灰化工艺。
在一个实施例中，在利用光对所述第一半导体结构进行照射之前执行所述灰化工艺。
在一个实施例中，所述掩模层包括光致抗蚀剂。
在一个实施例中，所述刻蚀保护层包括硅的氮化物或碳化硅。
在一个实施例中，所述湿法刻蚀采用的刻蚀剂包括四甲基氢氧化铵。
在一个实施例中，所述第一栅极结构包括：在所述第一区上的第一栅极电介质层；在所述第一栅极电介质层上的第一栅极；在所述第一栅极的表面和侧壁上的第一硬掩模层。
在一个实施例中，所述方法还包括：在所述衬底结构的表面上形成刻蚀保护层之前，在所述衬底结构的表面上形成缓冲层。
在一个实施例中，所述第二栅极结构包括：在所述第二区上的第二栅极电介质层；在所述第二栅极电介质层上的第二栅极；在所述第二栅极的表面和侧壁上的第二硬掩模层。
本申请提出的制造方法中，在去除掩模层后通过光照的方式可以有效地去除第一凹陷中残余的聚合物，从而减小了残余的聚合物对湿法刻蚀的影响，使得第二凹陷的形状为期望的形状，减小了对器件性能(例如载流子迁移率)的影响。另外，由于去除了第一凹陷中残余的聚合物，不必立刻进行下一步的工艺，增加了等待时间。此外，光照不会对器件的其他性能造成不利影响，易于执行。
通过以下参照附图对本申请的示例性实施例的详细描述，本申请的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本申请的示例性实施例，并且连同说明书一起用于解释本申请的原理，在附图中：
图1是根据本申请一个实施例的半导体器件的制造方法的流程图；
图2-图8示出了根据本申请一些实施例的半导体器件的制造方法的各个阶段的示意图。
具体实施方式
现在将参照附图来详细描述本申请的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本申请范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本申请及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和器件可能不作详细讨论，但在适用这些技术、方法和器件情况下，这些技术、方法和器件应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
本申请的发明人发现，聚合物的残留对PMOS(P沟道金属氧化物半导体)器件的影响尤为明显。在应变工程中，为了向沟道引入压应力，通常需要在栅极两侧形成用于外延源区和漏区的凹陷，之后，在凹陷中外延生成例如SiGe，以向沟道引入压应力，提高载流子的迁移率。然而，发明人发现，用于外延源区和漏区的凹陷的形状并非全为期望的形状，例如，某些凹陷的底部相比于正常的凹陷的底部更宽。凹陷的形状会影响外延形成的源区和漏区向沟道引入的压应力，从而影响器件的载流子迁移率。
发明人尝试找到导致上述问题发生的原因。发明人发现，PMOS器件可能会与其他器件，例如NMOS(N沟道金属氧化物半导体)器件一起制造，在刻蚀形成用于外延源区和漏区的凹陷之前，可能会在其他器件所在的区域上形成包含聚合物的掩模层，例如光致抗蚀剂等。在去除掩模层后，凹陷中可能会有残余的聚合物。例如，在之后的湿法刻蚀工艺中残余的掩模层可能会被带入凹陷中，从而使得凹陷中会存在聚合物；又例如，在去除掩模层时废气的沉淀导致凹陷中会存在聚合物；再例如，晶片所在的密闭容器的空气中存在聚合物等等。聚合物的存在会影响凹陷的刻蚀，从而使得形成的凹陷的形状并非全为期望的形状。
另外，由于凹陷中聚合物的残余，在去除掩模层后需要立刻进行下一步工艺，等待时间(Q time)较短。否则凹陷中的聚合物可能会进一步增多，例如残余的掩模层中的聚合物迁移至凹陷中等。
除了MOS器件外，其他器件在制造过程中如果需要在某个区域刻蚀形成凹陷，也会存在上述问题。
基于上述考虑，发明人提出了如下解决方案。
图1是根据本申请一个实施例的半导体器件的制造方法的流程图。图2-图8示出了根据本申请一些实施例的半导体器件的制造方法的各个阶段的示意图。
下面结合图1、图2-图8对根据本申请一些实施例的半导体器件的制造方法进行详细说明。
如图1所示，首先，在步骤102，提供衬底结构。
如图2所示，衬底结构可以包括衬底201。衬底201例如可以是硅衬底、锗衬底等元素半导体衬底，或者可以是砷化镓等化合物半导体衬底等。衬底201包括第一区211和第二区221。第一区211和第二区221可以通过隔离结构202(例如浅沟槽隔离结构)隔离开。
衬底结构还可以包括在第一区211上用于第一器件的第一栅极结构203。在一个实施例中，第一器件可以是MOS器件。例如，MOS器件可以是PMOS器件。然而，本申请并不限于此，例如，MOS器件也可以是NMOS器件。
在一个实施例中，第一栅极结构203可以包括在第一区211上的第一栅极电介质层213(例如硅的氧化物等)、在第一栅极电介质层213上的第一栅极223(例如多晶硅等)以及在第一栅极223的表面和侧壁上的第一硬掩模层243(例如硅的氮化物等)。优选地，第一栅极结构203还可以包括在第一栅极223的表面与第一硬掩模层243之间的缓冲层233，例如硅的氧化物等。然而，应理解，第一栅极结构203并不限于上面给出的结构，例如，在其他的实施例中，第一栅极结构203可以包括其他层，又例如，第一硬掩模层243可以仅形成在第一栅极223上方，而不形成在第一栅极223的侧壁上。
在一个实施例中，衬底结构还可以包括在第二区221上用于第二器件(例如NMOS器件)的第二栅极结构204。在一个实施例中，第二栅极结构204可以包括在第二区221上的第二栅极电介质层214(例如硅的氧化物等)、在第二栅极电介质层214上的第二栅极224(例如多晶硅等)以及在第二栅极224的表面和侧壁上的第二硬掩模层244(例如硅的氮化物等)。优选地，第二栅极结构204还可以包括在第二栅极224的表面与第二硬掩模层234之间的缓冲层244，例如硅的氧化物等。类似地，第二栅极结构204也不限于上面给出的结构。
接下来，在步骤104，在衬底结构的表面上形成刻蚀保护层206，如图3所示。优选地，刻蚀保护层206可以包括硅的氮化物(例如SiN)或碳化硅等。
优选地，在衬底结构的表面上形成刻蚀保护层206之前，可以先在衬底结构的表面上形成缓冲层205，例如硅的氧化物等。缓冲层205一方面可以增加刻蚀保护层206与第一硬掩模层233以及第二硬掩模层234之间的结合力，另一方面可以保护第一硬掩模层233和第二硬掩模层234在后续的工艺中不被刻蚀。
然后，在步骤106，在第二区221上方的刻蚀保护层206上形成掩模层207，如图4所示。这里，掩模层207包含聚合物。在一个实施例中，掩模层207可以包括但不限于光致抗蚀剂。例如，掩模层207还可以包括底部抗反射涂层等其他层。
之后，在步骤108，执行干法刻蚀，如图5所示。干法刻蚀使得第一栅极结构203两侧的第一区211被刻蚀以形成第一凹陷208，第一凹陷208的形状例如可以为类似椭圆形的形状。干法刻蚀还使得第一栅极结构203的表面上的刻蚀保护层206被去除，第一栅极结构203的侧壁上剩余的刻蚀保护层206作为间隔物层206A。
需要说明的是，在具有缓冲层205的情况下，干法刻蚀还使得第一栅极结构203的表面上的缓冲层205被去除，第一栅极结构203的侧壁上剩余的缓冲层205作为间隔物层205A。另外，可以理解的是，第一栅极结构203两侧的第一区211上的刻蚀保护层206和缓冲层205(如果有的话)也被相应地去除。
接下来，在步骤110，去除掩模层207，以形成如图6所示的半导体结构。
之后，在步骤112，利用光对半导体结构进行照射，如图7所示。
在去除掩模层207时，掩模层207可能会有残余，如果不采用其他措施，残余的掩模层207在后续的湿法刻蚀工艺中有可能会移至凹陷208中。而通过引进光对半导体结构进行照射的步骤，可以使得残余的掩模层中的聚合物分解。应理解，光照可以使得第一凹陷208中各种原因导致的聚合物分解。光照后的第一凹陷208的表面特征更适合后续工艺的进行。
优选地，可以利用激光对半导体结构进行照射。激光的定向性更好，并且能量密度更高，从而可以使得残余的掩模层中的聚合物更快被分解。在一个实施例中，激光的波长可以大于380nm，例如400nm、450nm、600nm等。在另一个实施例中，激光的波长范围可以为10nm至380nm，例如50nm、100nm、200nm等。在又一个实施例中，激光的波长可以小于10nm，例如5nm、8nm等。
优选地，可以利用不同波长的激光同时对半导体结构进行照射。在一个实施例中，激光可以包括第一激光、第二激光和第三激光中的多个。这里，第一激光的波长大于380nm，第二激光的波长范围为10nm至380nm，第三激光的波长小于10nm。例如，激光可以包括第一激光和第二激光；又例如，激光可以包括第二激光和第三激光；再例如，激光可以包括第一激光和第三激光；还例如，激光可以包括第一激光、第二激光和第三激光。利用上述三个不同波长范围内的激光同时对半导体结构进行照射可以更快、更充分地分解残余的掩模层207中的聚合物。
优选地，为了更好地去除残余的聚合物，在去除掩模层207后，还可以执行灰化工艺(Asher)。灰化工艺和光照的结合更有利于充分去除残余的聚合物。这里，可以在步骤112之前执行灰化工艺，也可以在步骤112之后执行灰化工艺。优选地，灰化工艺在步骤112之前执行，在灰化工艺后再利用光照的方式可以更充分地去除残余的聚合物。
之后，在步骤114，执行湿法刻蚀，以将第一凹陷208形成为第二凹陷209，如图8所示。第二凹陷209的形状例如可以为六边形或∑形状。在一个实施例中，湿法刻蚀采用的刻蚀剂可以包括四甲基氢氧化铵(TMAH)等。
在形成第二凹陷209后，还可以在第二凹陷209中外延生长SiGe，从而形成源区和漏区。
优选地，在外延SiGe之前，可以再次利用光对第二凹陷进行照射，从而进一步去除第二凹陷209中残余的聚合物，避免聚合物的残余对外延工艺的影响。光照的方式可以参照前面的描述，在此不再赘述。
之后，可以进行后续的工艺，例如，可以利用本申请提供的上述方法形成用于NMOS器件的源区和漏区的凹陷，进而在形成的凹陷中外延例如SiC，从而形成用于NMOS器件的源区和漏区。
本申请提出的制造方法中，在去除掩模层后通过光照的方式可以有效地去除第一凹陷中残余的聚合物，从而减小了残余的聚合物对湿法刻蚀的影响，使得第二凹陷的形状为期望的形状，减小了对器件性能(例如载流子迁移率)的影响。另外，由于去除了第一凹陷中残余的聚合物，不必立刻进行下一步的工艺，增加了等待时间。此外，光照不会对器件的其他性能造成不利影响，易于执行。
至此，已经详细描述了根据本申请实施例的半导体器件的制造方法。为了避免遮蔽本申请的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本申请的精神和范围。

Claims (18)

1.一种半导体器件的制造方法，其特征在于，包括：
提供衬底结构，所述衬底结构包括：
衬底，包括第一区和第二区；以及
在所述第一区上用于第一器件的第一栅极结构；
在所述衬底结构的表面上形成刻蚀保护层；
在所述第二区上方的刻蚀保护层上形成掩模层，所述掩模层包含聚合物；
执行干法刻蚀，以使得所述第一栅极结构两侧的第一区被刻蚀以形成第一凹陷，并使得所述第一栅极结构的表面上的刻蚀保护层被去除；
去除所述掩模层，以形成半导体结构；
在去除所述掩模层后，执行灰化工艺；
在所述灰化工艺之后，利用光对所述半导体结构进行照射，所述照射包括对所述第一凹陷进行照射、以及对在所述第二区上方的刻蚀保护层进行照射；
在所述照射后，执行湿法刻蚀，以将所述第一凹陷形成为第二凹陷。
2.根据权利要求1所述的方法，其特征在于，所述第一器件包括MOS器件。
3.根据权利要求2所述的方法，其特征在于，所述MOS器件包括PMOS器件。
4.根据权利要求3所述的方法，其特征在于，还包括：
在所述第二凹陷中外延生长SiGe。
5.根据权利要求4所述的方法，其特征在于，在所述第二凹陷中外延生长SiGe之前，还包括：
利用光对所述第二凹陷进行照射。
6.根据权利要求3所述的方法，其特征在于，所述衬底结构还包括在所述第二区上用于第二器件的第二栅极结构。
7.根据权利要求6所述的方法，其特征在于，所述第二器件包括NMOS器件。
8.根据权利要求1或5所述的方法，其特征在于，所述光包括激光。
9.根据权利要求8所述的方法，其特征在于，所述激光的波长大于380nm。
10.根据权利要求8所述的方法，其特征在于，所述激光的波长范围为10nm至380nm。
11.根据权利要求8所述的方法，其特征在于，所述激光的波长小于10nm。
12.根据权利要求8所述的方法，其特征在于，所述激光包括第一激光、第二激光和第三激光中的多个；
所述第一激光的波长大于380nm；
所述第二激光的波长范围为10nm至380nm；
所述第三激光的波长小于10nm。
13.根据权利要求1所述的方法，其特征在于，所述掩模层包括光致抗蚀剂。
14.根据权利要求1所述的方法，其特征在于，所述刻蚀保护层包括硅的氮化物或碳化硅。
15.根据权利要求1所述的方法，其特征在于，所述湿法刻蚀采用的刻蚀剂包括四甲基氢氧化铵。
16.根据权利要求1所述的方法，其特征在于，所述第一栅极结构包括：
在所述第一区上的第一栅极电介质层；
在所述第一栅极电介质层上的第一栅极；
在所述第一栅极的表面和侧壁上的第一硬掩模层。
17.根据权利要求16所述的方法，其特征在于，还包括：
在所述衬底结构的表面上形成刻蚀保护层之前，在所述衬底结构的表面上形成缓冲层。
18.根据权利要求6所述的方法，其特征在于，所述第二栅极结构包括：
在所述第二区上的第二栅极电介质层；
在所述第二栅极电介质层上的第二栅极；
在所述第二栅极的表面和侧壁上的第二硬掩模层。
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