CN109427276B - Display device, time sequence control circuit and signal reconstruction method thereof - Google Patents
Display device, time sequence control circuit and signal reconstruction method thereof Download PDFInfo
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Abstract
The invention provides a display device, which comprises a time sequence control circuit and an image processing system. The time sequence control circuit receives image data, a clock signal and a plurality of synchronous control signals output by the image processing system. The plurality of synchronization control signals includes at least one of a periodic synchronization control signal and a non-periodic synchronization control signal. The sequential control circuit comprises a signal reconstruction module and a signal processing module. The signal reconstruction module detects the periodic synchronous control signal at the initial stage to obtain a first parameter, and automatically generates a reconstruction synchronous control signal in a counting mode according to the first parameter. The signal processing module generates a gate control signal and a source control signal according to the image data, the reconstruction synchronization control signal and the aperiodic synchronization control signal. The invention also provides a time sequence control circuit and a signal reconstruction method thereof.
Description
Technical Field
The invention relates to a display device, a time sequence control circuit and a signal reconstruction method thereof.
Background
With the continuous development of electronic technology, most consumer electronic products such as mobile phones, portable computers, Personal Digital Assistants (PDAs), tablet computers, media players, etc. use displays as input and output devices, so that the products have a more friendly man-machine interaction mode. A display generally includes a display panel and a display driving circuit for driving the display panel to display an image. The driving circuit includes a timing controller, a scan driving circuit, and a data driving circuit. The time sequence controller receives an image data signal and a synchronous control signal sent by the image processing system, outputs a scanning control signal to the scanning driving circuit and outputs a data control signal to the data driving circuit. The display control signals include Vertical synchronization (Vsync), Horizontal synchronization (Hsync), Main Clock (MCLK), Data Enable (DE), and the like. Generally, the data enable signal is a periodic pulse signal and is active high. When the data enable signal is valid, the data information correspondingly output by the time sequence controller is valid display data and is displayed through the display panel. In the case where the image processing system and the timing control circuit are two chips, and data signals are transmitted between the two chips, an input pin of the timing controller is easily interfered by factors such as Static Electricity (ESD), so that a received input generates a jump or oscillation. When the data enable signal DE jumps or oscillates, a data driving circuit such as in a display device is caused to erroneously drive the data lines, resulting in an abnormality in the display screen of the display panel.
Disclosure of Invention
Accordingly, a display device with better noise interference resistance is needed.
It is also necessary to provide a timing control circuit with better noise interference resistance.
It is also necessary to provide a signal reconstruction method with better noise interference resistance.
A display device includes a display driving system and an image processing system. The display driving system comprises a time sequence control circuit, a scanning driving circuit and a data driving circuit. The time sequence control circuit receives image data, a clock signal and a plurality of synchronous control signals output by the image processing system and generates a grid control signal to control the scanning driving circuit and a source control signal to control the data driving circuit. The plurality of synchronization control signals includes at least one of a periodic synchronization control signal and a non-periodic synchronization control signal. The sequential control circuit comprises a signal reconstruction module and a signal processing module. The signal reconstruction module detects the periodic synchronous control signal in an initial stage to obtain a first parameter, and automatically generates a reconstruction synchronous control signal in a counting mode according to the first parameter so as to avoid noise from influencing the reconstruction synchronous control signal. The first parameter is used for characterizing the period length of the periodic synchronization signal. The at least one parameter is the number of the synchronous control signals in the same level state in any frame time of the initial stage. The re-establishing synchronization control signal is a signal having the same first parameter as the periodic signal. The signal processing module generates a gate control signal and a source control signal according to the image data, the reconstruction synchronization control signal and the aperiodic synchronization control signal.
A time sequence control circuit receives image data, a clock signal and a plurality of synchronous control signals output by an image processing system and generates a grid control signal to control a scanning driving circuit and a source control signal to control a data driving circuit. The plurality of synchronization control signals includes at least one of a periodic synchronization control signal and a non-periodic synchronization control signal. The sequential control circuit comprises a signal reconstruction module and a signal processing module. The signal reconstruction module detects the periodic synchronous control signal in an initial stage to obtain a first parameter, and automatically generates a reconstruction synchronous control signal in a counting mode according to the first parameter so as to avoid noise from influencing the reconstruction synchronous control signal. The first parameter is used for characterizing the period length of the periodic synchronization signal. The re-establishing synchronization control signal is a signal having the same first parameter as the periodic signal. The at least one parameter is the number of the synchronous control signals in the same level state in any frame time of the initial stage. The signal processing module generates a gate control signal and a source control signal according to the image data, the reconstruction synchronization control signal and the aperiodic synchronization control signal.
A signal reconstruction method is used in a time sequence control circuit of a display device; the time sequence control circuit receives image data, a clock signal and a plurality of synchronous control signals output by the image system. The plurality of synchronization control signals includes at least one of a periodic synchronization signal and a non-periodic synchronization signal. The signal reconstruction method comprises the following steps:
detecting a periodic synchronization control signal at an initial stage to obtain at least one parameter;
generating a start pulse according to the periodic synchronous control signal;
generating a reconstructed synchronization control signal in a counting manner according to the at least one parameter, wherein the at least one parameter can represent the period information of the synchronization control signal without a noise signal; the at least one parameter is the number of the synchronous control signals in the same level state in any frame time of an initial stage;
and generating a grid control signal and a source control signal according to the image data and the reconstruction synchronous control signal.
According to the time sequence control circuit of the display device, the periodic synchronous control signals input from the outside are simulated, the reestablished synchronous control signals are automatically generated in the time sequence control circuit, and therefore the phenomenon that the synchronous control signals output to the scanning driving circuit and the data driving circuit are suddenly changed due to the fact that system noise enters the pins of the time sequence control circuit is prevented, and the working stability of the time sequence control circuit is further guaranteed.
Drawings
FIG. 1 is a schematic diagram of an equivalent circuit of a display device according to a preferred embodiment.
FIG. 2 is a functional block diagram of a signal reconstruction module of the display device shown in FIG. 1.
FIG. 3 is a timing diagram of the synchronization control signal, the start pulse, the counter and the re-synchronization control signal of the re-establishment unit of the first embodiment shown in FIG. 2.
FIG. 4 is a timing diagram of a synchronization control signal with noise during a first level period, a counter and a reconstructed synchronization control signal received by the signal reconstruction module shown in FIG. 2.
FIG. 5 is a timing diagram illustrating a synchronization control signal with noise during a second level period, a counter and a reconstructed synchronization control signal received by the signal reconstruction module shown in FIG. 2.
Fig. 6 is a timing diagram of the synchronization control signal, the reconstructed synchronization control signal, the compensation signal and the compensated reconstructed synchronization control signal of the signal reconstruction module according to the second embodiment shown in fig. 2.
Fig. 7 is a flowchart of a signal reconstruction method for a timing control circuit according to a first embodiment.
Fig. 8 is a flowchart of a signal reconstruction method for a timing control circuit according to a second embodiment.
Description of the main elements
A reconstruction unit 215
Scan driving circuit 40
Signal reconstruction method S501-S506
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The invention provides a display device with a time sequence control circuit, wherein the time sequence control circuit detects a periodic synchronous control signal input by an image processing system at an initial stage to obtain at least one parameter and automatically generates a reestablished synchronous control signal in a counting mode according to the at least one parameter, so that the phenomenon that the synchronous control signal is suddenly changed due to the fact that system noise enters a pin of the time sequence control circuit is prevented, and the working stability of the time sequence control circuit is further guaranteed.
Referring to fig. 1, fig. 1 is an equivalent circuit diagram of a display device 1 according to an embodiment of the invention. The display device 1 includes a display panel 100, a display driving system 200, and an image processing system 500. The display panel 100 includes a plurality of scan lines 102 and a plurality of data lines 104. The scan lines 102 and the data lines 104 are insulated from each other to define a plurality of pixel units 106 arranged in a matrix. The display driving system 200 includes a timing control circuit 20, a scan driving circuit 40, and a data driving circuit 60. Each row of pixel units is electrically connected to the scan driving circuit 40 through a scan line 102, and each column of pixel units 106 is electrically connected to the data driving circuit 60 through a data line 104. In this embodiment, the image processing system 500 is configured to output a data signal and a synchronization control signal to the display driving system 200.
The timing control circuit 20 is electrically connected to the scan driving circuit 40 and the data driving circuit 60, respectively. The timing control circuit 20 receives the image data, the plurality of synchronization control signals, and the clock signal (MCLK) input from the image processing system 500, buffers the image data, and generates a gate control signal to the scan driving circuit 40 and a source control signal to the data driving circuit 60 according to the image data, the plurality of synchronization control signals, and the clock signal. The plurality of synchronization control signals may include a periodic synchronization control signal and a non-periodic synchronization control signal. The plurality of synchronization control signals include a Vertical synchronization (Vsync) signal, a Horizontal synchronization (Hsync) signal, and a Data Enable (DE) signal. Wherein, the data enable signal DE is a periodic synchronization control signal. The periodic synchronous control signal is a square wave-like signal and is a pulse signal formed by periodically alternating a first level and a second level, wherein the first level is a high level, and the second level is a low level. In the present embodiment, the timing control circuit 20 is a chip having a plurality of pins. However, when the synchronization control signal is transmitted between the image processing system 500 and the timing control circuit 20, the periodic synchronization control signal may generate sudden changes and noise due to static electricity or other factors entering the pins of the timing control circuit 20, which may generate the first level output period and/or the second level output period, and the noise usually appears as an oscillating wave with an oscillating frequency significantly higher than that of the periodic synchronization control signal. For example, as shown in the synchronization control signal of fig. 4, the periodic synchronization signal generates noise during the period that should be maintained at the first level. That is, the plurality of synchronization control signals includes a periodic synchronization signal having noise.
The timing control circuit 20 can eliminate noise in the periodic synchronization signal in addition to the basic functions of the timing control circuit 20, and the timing control circuit 20 includes a signal reconstruction module 21 and a signal processing module 23. The signal reconstructing module 21 is configured to detect the periodic synchronization control signal at an initial stage to obtain at least one parameter and to generate a reconstructed synchronization control signal according to the at least one parameter in a counting manner. This parameter can characterize the period of the ideal periodic synchronization signal. In the disclosure, the parameter includes a first parameter indicating the number of the first level state of the periodic synchronization signal in any frame time of the initial stage. Still further, the parameter further includes a second parameter characterizing a number of states of the periodic synchronization signal at a second level within any one frame time of the initial stage. The first parameter and the crystal oscillator pulse width of the time sequence control circuit can define the pulse width of a first level in a period, and the second parameter and the crystal oscillator pulse width of the time sequence control circuit can define the pulse width of a second level in the period.
Through research and observation of the waveform of the output synchronous control signal, the initial stage referred to in the present disclosure includes one or more of the following conditions:
first, in an initial stage, in a power-on stage of the display device 1, the periodic synchronization signal output to the timing control circuit 20 is less affected by the outside, the waveform of the periodic synchronization signal is more accurate, and the detected parameter is more accurate. In this embodiment, it is found through research that the periodic synchronization signal received by the timing control circuit 20 is less affected by the external environment in the next four frame times after the power-on, and is suitable for counting the period of the periodic synchronization signal in this period, and further calculating the first parameter.
Secondly, or in another initial stage, before a frame is displayed and a next frame is output to the timing control circuit 20, the electrostatic discharge process of the display device 1 is usually performed, and in the initial stage after the electrostatic discharge, for example, in the next four-frame time after the electrostatic discharge is completed, the periodic synchronization signal output to the timing control circuit 20 is less affected by the outside, the waveform of the periodic synchronization signal is more accurate, and the detected parameter is more accurate.
In the third or other cases or in other initial stages after the electrostatic discharge, such as the immediately following four frame times after the electrostatic discharge is completed, the periodic synchronization signal output to the timing control circuit 20 is less affected by the external environment, and is also suitable for performing waveform detection of the periodic synchronization signal to obtain more accurate parameters.
It is understood that in any case, the duration of the initial stage is a predetermined duration, and in this embodiment, the duration of the initial stage is four frames. For the acquisition of the first parameter, any one frame in the four-frame duration in the initial stage may be used as an object, and the average value of the sum of the first parameters corresponding to all frames in the four-frame duration in the initial stage may also be used.
The signal processing module 23 generates a gate control signal to the scan driving circuit 40 and a source control signal to the data driving circuit 60 according to the image data, the aperiodic sync signal, and the re-establishment sync control signal. The re-establishing synchronization control signal is a periodic synchronization signal which is generated by the timing control circuit 20 according to the parameters and has no noise. That is, the resync control signal is a periodically alternating pulse signal composed of a first level and a second level, and the pulse width of the first level is determined according to a first parameter.
Referring to fig. 2 and fig. 3 together, fig. 2 discloses a block diagram of an embodiment of the signal reconstruction module 21, and fig. 3 illustrates waveforms for explaining the working principle of the signal reconstruction module 21 according to the present disclosure. For the sake of illustration of the principle, fig. 3 discloses a waveform of the synchronization control signal as a period synchronization control signal without noise or as a period synchronization control signal at an initial stage.
The signal reconstruction module 21 comprises a calculation unit 213 and a reconstruction unit 215. The calculation unit 213 monitors and calculates the cycle synchronization control signal received at the initial stage to obtain the first parameter. Wherein the initial stage is one or more of the above listed initial stages. In this embodiment, the first parameter is the number of states that the periodic synchronization control signal is in the first level during the initial phase.
The reconstruction unit 215 has at least one counter 217 built therein. The counter 217 stores a first parameter and takes the first parameter as a count value. The reconstruction unit 215 generates a start pulse at a rising edge of the received periodic synchronization control signal, and generates a reconstructed synchronization control signal in a counting manner according to the first parameter. Specifically, the reconstructing unit 215 generates a start pulse SV from a rising edge of the received periodic synchronization control signal at the initial stage as a starting edge, outputs a first level with a falling edge of the start pulse SV as a starting point, and starts counting by the counter 217, wherein the start pulse SV has a predetermined pulse width or a predetermined duty ratio, the predetermined pulse width/duty ratio of the start pulse is smaller than that of the periodic synchronization control signal, where the pulse width is a duration of maintaining the first level in one period, and the duty ratio is a ratio of the first level to the period; when the accumulated count value of the counter 217 is equal to the first parameter, the output of the first level and the output of the second level are stopped, and the counter 217 is reset, that is, the reconstruction of the synchronous control signal for one cycle is completed. The start pulse is triggered by the rising edge of the synchronization control signal, that is, the synchronization control signal is switched from the second level to the first level. In the present embodiment, the pulse width of the start pulse is determined by the clock width generated by the crystal oscillator inherent to the timing control circuit 20 itself.
The working principle of the signal reconstruction module 21 is described below by taking the input data enable signal as an example. The data enable signal is used to control whether the data signal received by the timing control circuit 20 can be displayed through the display panel 100, and when the data enable signal is at a high level, the data enable signal controls the image data received by the timing control circuit 20 to be displayed through the display panel 100.
Referring to fig. 3, the calculating unit 213 monitors and calculates the first parameter N according to the data enable signal. The first parameter N is a number corresponding to a first level state of the data enable signal DE within a frame time. In this embodiment, the acquisition period of the first parameter N is any one frame time in the initial stage time period. Alternatively, the first parameter N is: in all four frame times of the initial stage period, an average of the sum of the numbers of the data enable signal DE in the first level state for each frame time is monitored.
The reconstruction unit 215 generates a start pulse according to the data enable signal DE, outputs a first level as a start point of the first level according to a falling edge of the start pulse, outputs a pulse width of one start pulse or a crystal oscillator pulse width inherent to the timing control circuit 20 as a unit width, and continuously outputs the first level of N unit widths from the start point according to the first parameter N to generate the reconstruction data enable signal. Specifically, the reconstruction unit 215 generates a start pulse from a rising edge of the data enable signal DE as a start edge, outputs a first level with a falling edge of the start pulse as a start edge, while the counter 217 starts counting, the reconstruction unit 215 maintains the output of the first level during the counter 217 continues counting, and the counter 217 counts up by one every time the duration of outputting the first level is equal to one unit width duration; when the accumulated count value of the counter 217 is equal to N, the output of the first level and the output of the second level are stopped until the falling edge of the next start pulse, and the counter 217 is reset, that is, the reconstruction of the data enable signal for one cycle is completed. Wherein the start pulse is triggered by the rising edge of the data enable signal DE, i.e. the data enable signal is switched from the second level to the first level.
Referring to fig. 4, after the initial stage, noise may enter the timing control circuit 20 through a pin, which may cause a synchronous control signal received by the timing control circuit 20 to have an oscillation waveform with an oscillation frequency higher than itself in an original first level period, because the reconstruction unit 215 may generate the start pulse SV according to a rising edge of the data enable signal DE and output the first level with a falling edge of the start pulse SV as a starting point, and the counter 217 starts counting at the same time, the reconstruction unit 215 keeps outputting the first level during a continuous counting period of the counter 217, and each time a duration of outputting the first level is equal to a unit width duration, the counter 217 counts up by one; when the accumulated count value of the counter 217 is equal to the first parameter, the output of the first level and the output of the second level are stopped until the falling edge of the next start pulse, and the counter 217 is reset to complete one cycle. The reconstruction unit 215 generates a mask by using the counting function of the counter 217, so as to prevent the synchronous control signal with noise from being directly output to the signal processing module 23, thereby ensuring the stability of the synchronous control signal received by the signal processing module 23.
Referring to fig. 5, after the initial stage, noise may enter the timing control circuit 20 through the pin, which may cause the synchronous control signal received by the timing control circuit 20 to have an oscillation waveform with an oscillation frequency higher than itself during the original second level period, because the reconstruction unit 215 generates the start pulse SV according to the rising edge of the data enable signal DE and outputs the first level with the falling edge of the start pulse SV as the starting point, and the counter 217 starts counting at the same time, the reconstruction unit 215 keeps outputting the first level during the continuous counting period of the counter 217, and the counter 217 counts up by one each time the duration of outputting the first level is equal to the duration of one unit width; when the accumulated count value of the counter 217 is equal to the first parameter N, the output of the first level and the output of the second level are stopped until the falling edge of the next start pulse, and the counter 217 is reset to complete one cycle. The reconstruction unit 215 generates a mask by using the counting function of the counter 217, so as to prevent the synchronous control signal with noise from being directly output to the signal processing module 23, thereby ensuring the stability of the synchronous control signal received by the signal processing module 23.
The timing control circuit of the display device of the embodiment can prevent the system noise from entering the pins of the timing control circuit to cause the sudden change of the synchronous control signal, thereby ensuring the working stability of the timing control circuit.
Please refer to fig. 6, which is a timing diagram of a signal reconstructing module of a timing control circuit according to a second embodiment of the disclosure. In the second embodiment, elements having the same functions as those in the first embodiment are named the same. In this embodiment, the parameters include a first parameter and a second parameter, and the first parameter is the same as the first parameter of the first embodiment.
The signal reconstructing module 21 further detects whether the reconstructed synchronization control signal is abnormal, generates a compensation signal according to the second parameter when the reconstructed synchronization control signal is abnormal, performs logic operation on the reconstructed synchronization control signal and the compensation signal to obtain a compensated reconstructed synchronization control signal, and outputs the compensated reconstructed synchronization control signal to the signal processing module 23. When noise is generated on the rising edge of the input synchronization control signal, the reconstruction synchronization control signal generated by the signal reconstruction module 21 will mask the start pulse of the synchronization control signal of the next period, so that the first parameter of the reconstruction synchronization control signal is smaller than the first parameter of the input synchronization control signal, and the reconstruction synchronization control signal is abnormal.
The calculation unit 213 monitors and calculates the synchronization control signal received at the initial stage to obtain the first parameter and the second parameter. The first parameter N is a number corresponding to a first level state of the data enable signal DE within a frame time. In this embodiment, the acquisition period of the first parameter N is any one frame time in the initial stage time period. Alternatively, the first parameter N is: in all four frame times of the initial stage period, an average of the sum of the numbers of the data enable signal DE in the first level state for each frame time is monitored. The second parameter is the number of the second level state of the periodical synchronous control signal in the corresponding frame time during the initial stage. In this embodiment, the acquisition period of the second parameter is any one frame time in the initial stage time period. Alternatively, the second parameter is: in all four frame times of the initial stage period, an average of the sum of the numbers of the data enable signal DE in the second level state for each frame time is monitored.
The reconstruction unit 215 has at least one counter 217 built therein. The reconstruction unit 215 generates a start pulse according to the data enable signal DE, uses a falling edge of the start pulse as a start point of outputting a first level of the reconstructed data enable signal, uses a pulse width of each output start pulse or a crystal oscillator pulse width inherent to the timing control circuit 20 as a unit width, continuously outputs first levels of N unit widths from the start point according to the first parameter N to generate the reconstructed data enable signal, and monitors whether the reconstructed synchronization control signal has the first level where the falling edge happens to correspond to the synchronization control signal. When the position of the falling edge of the reconstructed synchronization control signal corresponds to the first level of the synchronization control signal, the reconstruction unit 215 generates the compensation signal according to the second parameter. The compensation signal is a pulse signal. The compensation signal is at the second level when the position where the falling edge of the reconstructed synchronization control signal is corresponding to the first level of the synchronization control signal, the second level is switched to the first level when the counter 217 counts again and the count value is equal to the second parameter, and the first level is switched to the second level when the reconstructed synchronization control signal is corresponding to the falling edge of the synchronization control signal. The reconstruction unit 215 performs a logical operation on the compensation signal and the reconstruction synchronization control signal, and outputs the result to the signal processing module 23. When the falling edge of the reestablished synchronization control signal corresponds to the first level of the synchronization control signal, the reestablished synchronization control signal is abnormal, which may cause the start pulse corresponding to the synchronization control signal of the next period to be masked, and the corresponding reestablished synchronization control signal cannot be generated. I.e. the first parameter of the re-establishing synchronization control signal is smaller than the first parameter of the synchronization control signal. The compensation signal and the reestablishment synchronization control signal are output after being operated through a logic OR gate. In the present embodiment, the pulse width of the start pulse is determined by the clock width generated by the crystal oscillator inherent to the timing control circuit 20 itself.
Specifically, taking the data enable signal DE as an example, the reconstruction unit 215 generates a start pulse starting from a rising edge of the data enable signal DE, outputs a first level starting from a falling edge of the start pulse, while the counter 217 starts counting, the reconstruction unit 215 keeps outputting the first level during the counter 217 continues counting, and the counter 217 counts up by one every time the duration of outputting the first level is equal to one unit width duration; when the accumulated count value of the counter 217 is equal to the first parameter N, stopping outputting the first level and outputting the second level until the falling edge of the next start pulse SV comes, resetting the counter 217; and monitoring whether the position of a falling edge formed by switching the first level to the second level corresponds to the first level of the data enable signal. If the falling edge corresponds to the first level of the data enable signal, the counter 217 starts counting, the reconstruction unit 215 generates the compensation signal, the compensation signal is in the second level state, the compensation signal keeps outputting the second level during the continuous counting of the counter 217, and the counter 217 counts up by one every time the duration of outputting the second level is equal to the duration of one unit width; when the accumulated count value of the counter 217 is equal to the second parameter, the compensation signal is switched from the second level to the first level, and when the reconstructed data enable signal corresponds to the falling edge of the data enable signal, the compensation signal is switched from the first level to the second level; the reconstruction unit 215 outputs the compensation signal and the reconstruction synchronization control signal to the signal processing module 23 after performing an OR gate (OR gate) operation. The compensation signal is used for compensating the first parameter N of the reconstruction data enabling signal, so that the first parameter of the reconstruction data enabling signal is equal to the first parameter N of the data enabling signal. In this embodiment, the pulse width of the compensation signal is smaller than the pulse width of the data enable signal.
According to the time sequence control circuit of the display device, the received synchronous control signal is prevented from generating sudden change due to the fact that system noise enters the pins of the time sequence control circuit through simulating the periodic synchronous control signal input from the outside and automatically generating the reestablished synchronous control signal in the time sequence control circuit, and the working stability of the time sequence control circuit is further guaranteed.
Please refer to fig. 7, which is a flowchart of a signal reconstruction method corresponding to the timing control circuit 20, and is applied to the timing control circuit 20 of the display device 1. The timing control circuit 20 receives image data, a plurality of synchronization control signals, and a clock signal (MCLK) input from the image processing system 500. The signal reconstruction method comprises the following steps:
in step S701, the calculating unit 213 monitors and calculates the periodic synchronization control signal to obtain the first parameter at the initial stage. Wherein the initial stage is one or more of the initial stages listed above. The first parameter is a number of states that the periodic synchronization control signal is in the first level during the initial phase. In this embodiment, the acquisition period of the first parameter N is any one frame time in the initial stage time period. Alternatively, the first parameter N is: in all four frame times of the initial stage period, an average value of a sum of the numbers of the first level states of the synchronization control signal at each frame time is monitored.
In step S702, the reconstruction unit 215 generates a start pulse according to the synchronization control signal. Wherein the start pulse is triggered by the rising edge of the synchronization control signal. The start pulse has a predetermined pulse width or a predetermined duty ratio, and the predetermined pulse width/duty ratio of the start pulse is smaller than that of the periodic synchronization control signal, where the pulse width refers to a duration of maintaining the first level in one period and the duty ratio refers to a ratio of the first level to the period. In the present embodiment, the pulse width of the start pulse is determined by the clock width generated by the crystal oscillator inherent to the timing control circuit 20 itself.
In step S703, the reconstruction unit 215 regenerates the reconstruction synchronization control signal in a counting manner according to the start pulse and the first parameter. Specifically, the first level is output as a start point of the first level for reconstructing the synchronization control signal based on the falling edge of the start pulse, the unit width is a pulse width per one start pulse output or a crystal oscillator pulse width inherent to the timing control circuit 20, and the first levels of N unit widths are continuously output from the start point based on the first parameter N to generate the reconstructed synchronization control signal. Taking the data enable signal DE as an example, when generating the data enable signal, the reconstruction unit 215 outputs the first level with a falling edge of the start pulse as a start edge by generating the start pulse with a rising edge of the data enable signal DE as a start edge, while the counter 217 starts counting, the reconstruction unit 215 keeps outputting the first level during the counter 217 continues counting, and the counter 217 counts up by one every time the duration of outputting the first level is equal to the duration of one unit width; when the accumulated count value of the counter 217 is equal to N, the output of the first level and the output of the second level are stopped until the falling edge of the next start pulse, and the counter 217 is reset, that is, the reconstruction with the data enable signal DE is completed for one cycle. Wherein the start pulse is triggered by the rising edge of the data enable signal DE, i.e. the synchronization control signal is switched from the second level to the first level.
In step S704, the signal processing module 23 generates a gate control signal and a source control signal according to the image data, the compensated reconstruction synchronization control signal, and the aperiodic synchronization control signal.
Please refer to fig. 8, which is a flowchart of a signal reconstruction method corresponding to the timing control circuit 20, and is applied to the timing control circuit 20 of the display device 1. The timing control circuit 20 receives image data, a plurality of synchronization control signals, and a clock signal (MCLK) input from the image processing system 500. The signal reconstruction method comprises the following steps:
in step S801, the calculating unit 213 detects a periodic synchronization control signal at an initial stage to obtain a first parameter and a second parameter. Wherein the initial stage is one or more of the above listed initial stages. The first parameter is a number of states that the periodic synchronization control signal is in the first level during the initial phase. In this embodiment, the acquisition period of the first parameter N is any one frame time in the initial stage time period. Alternatively, the first parameter N is: monitoring an average value of a sum of the number of the first level states of the synchronization control signal at each frame time in all four frame times of the initial stage period; the acquisition period of the second parameter is any frame time in the initial stage time period. The second parameter is: in all four frame times of the initial stage period, an average value of a sum of the numbers of the second level states of the synchronization control signal at each frame time is monitored.
In step S802, the reconstruction unit 215 generates a start pulse according to the synchronization control signal. Wherein the start pulse is triggered by the rising edge of the synchronization control signal. The start pulse has a predetermined pulse width or a predetermined duty ratio, and the predetermined pulse width/duty ratio of the start pulse is smaller than that of the periodic synchronization control signal, where the pulse width refers to a duration of maintaining the first level in one period and the duty ratio refers to a ratio of the first level to the period. In the present embodiment, the pulse width of the start pulse is determined by the clock width generated by the crystal oscillator inherent to the timing control circuit 20 itself.
In step S803, the reconstruction unit 215 regenerates the reconstruction synchronization control signal in a counting manner according to the start pulse and the first parameter. Specifically, the first level is output as a start point of the first level of the rebuilt synchronization control signal according to a falling edge of the start pulse, the unit width is a pulse width of one start pulse or a crystal oscillator pulse width inherent to the timing control circuit 20 at a time, and the first levels of N unit widths are continuously output from the start point according to the first parameter N to generate the rebuilt synchronization control signal. Taking the data enable signal DE as an example, the reconstruction unit 215 generates a start pulse from a rising edge of the data enable signal DE as a start edge, outputs a first level from a falling edge of the start pulse, while the counter 217 starts counting, the reconstruction unit 215 keeps outputting the first level during the counter 217 continues counting, and the counter 217 counts up by one every time a duration of outputting the first level is equal to a unit width duration; when the accumulated count value of the counter 217 is equal to N, the output of the first level and the output of the second level are stopped until the falling edge of the next start pulse, and the counter 217 is reset, that is, the reconstruction of the data enable signal DE for one cycle is completed. Wherein the start pulse is triggered by the rising edge of the data enable signal DE, i.e. the synchronization control signal is switched from the second level to the first level.
In step S804, the reconstruction unit 215 detects whether there is an abnormality in the reconstructed synchronization control signal. If the reestablishment synchronization control signal is abnormal, the step S805 is performed; if the reestablishment synchronization control signal is abnormal, the process proceeds to step S806. When noise is generated on the rising edge of the input synchronization control signal, the reconstruction synchronization control signal generated by the signal reconstruction module 21 will mask the start pulse of the synchronization control signal of the next period, so that the first parameter of the reconstruction synchronization control signal is smaller than the first parameter of the input synchronization control signal, and the reconstruction synchronization control signal is abnormal. Specifically, the reconstruction unit 215 monitors whether the reconstruction of the synchronization control signal where the falling edge happens corresponds to the first level of the synchronization control signal.
In step S805, the reconstruction unit 215 generates a compensation signal according to the second parameter, and outputs the compensation signal and the reconstruction synchronization control signal after performing a logic operation. When the falling edge of the resynchronization control signal corresponds to the first level of the synchronization control signal, the reconstruction unit 215 starts counting by the counter 217, and the compensation signal is at the second level; the compensation signal maintains the output of the second level during the continuous counting of the counter 217, and the counter 217 counts up by one every time the duration of outputting the second level is equal to the duration of one unit width; when the accumulated count value of the counter 217 is equal to the second parameter, the compensation signal is switched from the second level to the first level; and when the reestablished synchronous control signal corresponds to the falling edge of the synchronous control signal, the compensation signal is switched from the first level to the second level. The compensation signal and the reconstruction synchronization control signal are output after being operated by a logic OR gate (OR gate). The compensation signal is used for compensating the first parameter of the reestablishment synchronization control signal, so that the first parameter of the reestablishment synchronization control signal is equal to the first parameter of the synchronization control signal. Wherein, the compensation signal is a pulse signal. In this embodiment, the pulse width of the compensation signal is smaller than the pulse width of the synchronization control signal.
In step S806, the signal processing module 23 generates a gate control signal and a source control signal according to the image data, the compensated reconstruction synchronization control signal, and the aperiodic synchronization control signal.
According to the time sequence control circuit of the display device, the received synchronous control signal is prevented from generating sudden change due to the fact that system noise enters the pins of the time sequence control circuit through simulating the periodic synchronous control signal input from the outside and automatically generating the reestablished synchronous control signal in the time sequence control circuit, and the working stability of the time sequence control circuit is further guaranteed.
It will be appreciated by those skilled in the art that the above embodiments are illustrative only and not intended to be limiting, and that suitable modifications and variations may be made to the above embodiments without departing from the true spirit and scope of the invention.
Claims (20)
1. A display device includes a display driving system and an image processing system; the display driving system comprises a time sequence control circuit, a scanning driving circuit and a data driving circuit; the time sequence control circuit receives image data, clock signals and synchronous control signals output by the image processing system and generates grid control signals to control the scanning driving circuit and the source control signals to control the data driving circuit; the method is characterized in that: the time sequence control circuit also comprises a signal reconstruction module and a signal processing module; the signal reconstruction module detects the synchronous control signal at the initial stage to obtain at least one parameter and regenerates a reconstructed synchronous control signal in a counting mode according to the at least one parameter, and the at least one parameter can represent the period information of the synchronous control signal without the noise signal; the at least one parameter is the number of the synchronous control signals in the same level state in any frame time of an initial stage; the signal processing module receives image data and the reconstruction synchronization control signal and generates the grid control signal and the source control signal.
2. The display device of claim 1, wherein: the synchronous control signal comprises a pulse signal formed by periodically alternating a first level and a second level, the at least one parameter comprises a first parameter representing the number of states of the synchronous control signal at the first level in any frame time of an initial stage, and the pulse width of the first level in one period can be defined by using the first parameter and the crystal oscillator pulse width of the timing control circuit.
3. The display device of claim 2, wherein: the signal reconstruction module comprises a calculation unit and a reconstruction unit; the calculation unit monitors and calculates the first parameter according to the received synchronous control signal; the reconstruction unit generates a start pulse by taking a rising edge of the synchronous control signal as a starting point, outputs a first level and starts counting by taking a falling edge of the start pulse as a starting point, and stops outputting the first level and generates a second level to form a falling edge when an accumulated count value is equal to the first parameter.
4. The display device of claim 2, wherein: the at least one parameter further includes a second parameter characterizing the number of states of the periodic synchronization signal at a second level in any frame time of the initial stage, and the pulse width of the second level in one period can be defined by using the second parameter and the crystal oscillator pulse width of the timing control circuit itself.
5. The display device of claim 2, wherein: the signal reconstruction module is also used for monitoring the synchronous control signal and calculating to obtain a second parameter; the signal reconstruction module detects whether the reconstruction synchronous control signal is abnormal or not, generates a compensation signal according to the second parameter when the reconstruction synchronous control signal is abnormal, and outputs the compensation signal and the reconstruction synchronous control signal to the signal processing module after logic operation.
6. The display device of claim 5, wherein: the signal reconstruction module compares whether the falling edge of the reconstructed synchronous control signal corresponds to the first level of the synchronous control signal; if the falling edge of the reestablished synchronous control signal corresponds to the first level of the synchronous control signal, the signal reestablishing module generates the compensation signal according to the second parameter; the compensation signal is at a second level when the position of the falling edge of the reestablished synchronous control signal corresponds to the first level of the synchronous control signal, the second level is switched to the first level when the recounting is carried out and the counting value is equal to the second parameter, and the first level is switched to the second level when the reestablished synchronous control signal corresponds to the falling edge of the synchronous control signal.
7. The display device of claim 6, wherein: and carrying out logical OR gate operation on the compensation signal and the reestablishment synchronization control signal.
8. The display device according to any one of claims 1 to 7, wherein: the initial stage is any one of a next predetermined period of time after the display device is powered on and an immediately subsequent predetermined period of time after the display device completes electrostatic discharge.
9. The display device of claim 8, wherein: the duration of the preset time period is four frames.
10. The display device of claim 1, wherein: the synchronization control signal is a data enable signal.
11. A time sequence control circuit receives image data, a clock signal and a plurality of synchronous control signals output by an image processing system and generates a grid control signal to control a scanning drive circuit and a source control signal to control a data drive circuit; the method is characterized in that: the time sequence control circuit comprises a signal reconstruction module and a signal processing module; the signal reconstruction module detects the synchronous control signal at the initial stage to obtain at least one parameter and regenerates a reconstructed synchronous control signal in a counting mode according to the at least one parameter, and the at least one parameter can represent the period information of the synchronous control signal without the noise signal; the at least one parameter is the number of the synchronous control signals in the same level state in any frame time of an initial stage; the signal processing module receives image data and the reconstruction synchronization control signal and generates the grid control signal and the source control signal.
12. The timing control circuit of claim 11, wherein: the synchronous control signal comprises a pulse signal formed by periodically alternating a first level and a second level, the at least one parameter comprises a first parameter representing the number of states of the synchronous control signal at the first level in any frame time of an initial stage, and the pulse width of the first level in one period can be defined by using the first parameter and the crystal oscillator pulse width of the timing control circuit.
13. The timing control circuit of claim 12, wherein: the signal reconstruction module comprises a calculation unit and a reconstruction unit; the calculation unit monitors and calculates the first parameter according to the received synchronous control signal; the signal reconstruction module generates a starting pulse by taking the rising edge of the synchronous control signal as a starting point, outputs a first level and starts counting by taking the falling edge of the starting pulse as a starting point, and stops outputting the first level and generates a second level to form a falling edge when the accumulated count value is equal to the first parameter.
14. The timing control circuit of claim 12, wherein: the at least one parameter further comprises a second parameter for representing the number of states of the periodic synchronous signal in a second level in any frame time of the initial stage, and the pulse width of the second level in one period can be defined by using the second parameter and the crystal oscillator pulse width of the time sequence control circuit; the signal reconstruction module monitors the synchronous control signal and calculates to obtain the second parameter; the signal reconstruction module detects whether the reconstruction synchronous control signal is abnormal or not, generates a compensation signal according to the second parameter when the reconstruction synchronous control signal is abnormal, and outputs the compensation signal and the reconstruction synchronous control signal to the signal processing module after logic operation.
15. The timing control circuit of claim 14, wherein: the signal reconstruction module compares whether the falling edge of the reconstructed synchronous control signal corresponds to the first level of the synchronous control signal; if the falling edge of the reestablished synchronous control signal corresponds to the first level of the synchronous control signal, the signal reestablishing module generates the compensation signal according to the second parameter; the compensation signal is at a second level when the position of the falling edge of the reestablished synchronous control signal corresponds to the first level of the synchronous control signal, the second level is switched to the first level when the recounting is carried out and the counting value is equal to the second parameter, and the first level is switched to the second level when the reestablished synchronous control signal corresponds to the falling edge of the synchronous control signal.
16. The timing control circuit of claim 15, wherein: and carrying out logical OR gate operation on the compensation signal and the reestablishment synchronization control signal.
17. A signal reconstruction method is used in a time sequence control circuit of a display device; the time sequence control circuit receives image data, a clock signal and a plurality of synchronous control signals output by an image system; wherein the plurality of synchronization control signals includes at least one of a periodic synchronization signal and a non-periodic synchronization signal; the signal reconstruction method comprises the following steps:
detecting a synchronization control signal at an initial stage to obtain at least one parameter;
generating a start pulse according to the periodic synchronous control signal;
generating a reconstructed synchronization control signal in a counting manner according to the at least one parameter, wherein the at least one parameter can represent the period information of the synchronization control signal without a noise signal; the at least one parameter is the number of the synchronous control signals in the same level state in any frame time of an initial stage;
and generating a grid control signal and a source control signal according to the image data and the reconstruction synchronous control signal.
18. The signal reconstruction method of claim 17, wherein: the at least one parameter comprises a first parameter which represents the number of the synchronous control signals in a first level state in any frame time of an initial stage; the step of generating a start pulse according to the periodic synchronization control signal further comprises:
generating a start pulse by taking a rising edge of the synchronous control signal as a starting point, outputting a first level of the reestablished synchronous control signal by taking a falling edge of the start pulse as a starting point, and starting counting;
and stopping outputting the first level and generating the second level of the reestablishment synchronization control signal and forming a falling edge when the accumulated count value is equal to the first parameter.
19. The signal reconstruction method of claim 18, wherein: the at least one parameter further comprises a second parameter characterizing the number of second level states of the periodic synchronization signal in any frame time of the initial stage; the step of stopping outputting the first level and generating the second level of the re-synchronization control signal and forming a falling edge when the accumulated count value is equal to the first parameter further comprises:
detecting whether the reestablishment synchronization control signal is abnormal or not;
if the reestablishment synchronization control signal is abnormal, generating a compensation signal according to the second parameter;
carrying out logical OR gate operation on the compensation signal and the reconstruction synchronization control signal to obtain a compensated reconstruction synchronization control signal;
and generating a grid control signal and a source control signal according to the image data and the compensated reconstruction synchronous control signal.
20. The signal reconstruction method of claim 19, wherein: the compensation signal is at a second level when the position of the falling edge of the reestablished synchronous control signal corresponds to the first level of the synchronous control signal, the second level is switched to the first level when the recounting is carried out and the counting value is equal to the second parameter, and the first level is switched to the second level when the reestablished synchronous control signal corresponds to the falling edge of the synchronous control signal.
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