JP6612021B2 - Display driving device and display device - Google Patents

Description

  The present invention relates to a display drive device and a display device, and is particularly suitable for a display drive device and a display device that perform display drive and touch detection in a time-sharing manner.

  In recent years, an in-cell touch panel in which a liquid crystal display panel and a touch detection panel are integrally laminated and mounted has been developed, and a display driver with a built-in touch panel control has been developed. By incorporating a touch panel control function in a conventional display drive device, touch drive can be performed while avoiding mixing of display system drive noise into the touch detection system. Thereby, there exists a merit which touch accuracy improves. For example, Patent Document 1 discloses a display device that suppresses the influence of noise by alternately driving an in-cell touch center and a display area in a time-sharing manner.

JP 2012-59265 A

  As a result of examination of the patent document 1 by the present inventors, it has been found that there are the following new problems.

  A display driving device such as a liquid crystal display driver internally generates a timing signal based on a synchronization signal supplied from the outside. For example, the vertical synchronization signal Vsync_ext and the horizontal synchronization signal Hsync_ext are input from the outside, and the vertical synchronization signal Vsync_int and the horizontal synchronization signal Hsync_int are internally generated based on the vertical synchronization signal Vsync_ext and used for internal timing control.

  Here, in order to perform time-sharing control of display driving and touch detection, the horizontal synchronization signal Hsync_int is generated within one frame period by shortening the cycle of the internally generated horizontal synchronization signal Hsync_int and increasing the number of pulses per frame. A display period (display driving period) in which display driving is performed in synchronization with the touch detection period and a touch detection period in which touch detection is performed can be provided. For example, if 1 frame is 1/60 seconds and the number of display lines per frame is 1080 lines, the period of the horizontal synchronization signal Hsync_ext supplied from the outside is 1/60/1080 seconds = 15.4 μs. The period of the horizontal synchronization signal Hsync_int generated at 1 is 10.0 μs, which is shorter than this. Since the time required to perform display driving of 1080 lines within 1 frame period of 1/60 seconds = 16.7 ms is 10.0 μs × 1080 = 10.8 ms, the remaining 5.9 ms is used as the touch detection period. can do. Note that there are cases where display driving is not actually performed, a return line period needs to be provided separately, or touch detection is performed during the return line period.

  From the above consideration, in order to perform time division control of display driving and touch detection, the display driving device is configured so that the period of the horizontal synchronization signal Hsync_int generated internally can be arbitrarily specified, and the internal horizontal synchronization is configured. It has been found that it is preferable to perform display driving for each line in synchronization with the signal Hsync_int and perform touch detection during the remaining period.

  However, at this time, since one frame period needs to coincide with the outside, the period of the internal horizontal synchronization signal Hsync_int generated within one frame period is not necessarily an integral number of one frame period. Therefore, it was found that discontinuities occur in that cycle. It has been found that when this discontinuous point occurs within the display drive period, there is a problem that the display becomes abnormal, and when it occurs within the touch detection period, there is a problem that the detection accuracy is lowered.

  An object of the present invention is set in a display driving device configured to be able to arbitrarily specify a cycle of a horizontal synchronization signal Hsync_int generated internally in order to perform time-sharing control of display driving and touch detection. Even when the period and one frame period are not in the relation of the integer ratio, the display abnormality is not caused and the deterioration of the touch detection accuracy is prevented.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, it is a display drive device mounted on a display device that performs display drive and touch detection in a time-sharing manner, and includes a display drive circuit, a touch panel control circuit, and a timing generation circuit. The timing generation circuit generates an internal vertical synchronization signal and an internal horizontal synchronization signal from an external vertical synchronization signal and an external horizontal synchronization signal supplied from the outside. The display drive circuit performs a display drive operation in synchronization with the internal horizontal synchronization signal during the display drive period, and the touch panel control circuit performs a touch detection operation in synchronization with the internal horizontal synchronization signal during the touch detection period. The timing generation circuit repeatedly generates an internal horizontal synchronization signal for each set period from a switching timing defined based on an external or internal vertical synchronization signal. The switching timing is adjusted to a period other than the display drive period and the touch detection period.

  The effect obtained by the one embodiment will be briefly described as follows.

In other words, without causing Viewing abnormal, and it is possible to prevent deterioration in the touch detection accuracy.

FIG. 1 is a block diagram of a display device according to an embodiment of the present invention. FIG. 2 is a timing chart illustrating an operation example of the display driving device that does not perform time-division operation for display driving and touch detection. FIG. 3 is a timing chart illustrating an operation example of the display driving device that performs time-division operation of display driving and touch detection. FIG. 4 is a timing chart showing an example in which a discontinuous point of the internal horizontal synchronization signal occurs during the display drive period. FIG. 5 is a timing chart showing an example in which a discontinuous point of the internal horizontal synchronization signal occurs in the touch detection period. FIG. 6 is a block diagram illustrating a configuration example of the timing generation circuit according to the first embodiment. FIG. 7 is a timing chart illustrating an operation example of the display driving apparatus according to the first embodiment. FIG. 8 is a timing chart showing an example of the generation timing of the internal horizontal synchronizing signal in the display driving apparatus corresponding to FIG. FIG. 9 is a timing chart showing another example of the generation timing of the internal horizontal synchronization signal. FIG. 10 is a block diagram illustrating a configuration example of the timing generation circuit according to the second embodiment. FIG. 11 is a timing chart illustrating an operation example of the display driving apparatus according to the second embodiment. FIG. 12 is a more detailed timing chart showing an example of the generation timing of the internal horizontal synchronization signal in the display driving apparatus of the second embodiment. FIG. 13 is a block diagram illustrating another configuration example of the timing generation circuit according to the second embodiment. FIG. 14 is a block diagram of a display device according to another embodiment of the present invention. FIG. 15 is a timing chart showing an operation example of the display driving apparatus of FIG.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Set discontinuous point of internal horizontal sync signal at arbitrary timing>
A representative embodiment disclosed in the present application is a display drive device (100) mounted on a display device (1000) that performs display drive and touch detection in a time-sharing manner, and includes a timing generation circuit (10) and a display. A drive circuit (20) and a touch panel control circuit (30) are provided.

  The timing generation circuit generates an internal vertical synchronization signal (Vsync_int) and an internal horizontal synchronization signal (Hsync_int) from an external vertical synchronization signal (Vsync_ext) and an external horizontal synchronization signal (Hsync_ext) supplied from the outside.

  The display drive circuit performs a display drive operation in synchronization with the internal horizontal synchronization signal during a display drive period, and the touch panel control circuit performs a touch detection operation in synchronization with the internal horizontal synchronization signal during a touch detection period. Do.

  The timing generation circuit repeatedly generates the internal horizontal synchronization signal every set period (HSW1, Hcyc) from a switching timing (POS1) defined based on the external vertical synchronization signal or the internal vertical synchronization signal. .

  The switching timing is set to a period other than the display driving period and the touch detection period.

  As a result, even when a pulse is generated with a cycle shorter than the cycle in which the internal horizontal sync signal is set at the switching timing (discontinuous point), display abnormality does not occur and deterioration of touch detection accuracy is prevented. can do.

[2] <HSW1 × M + HSW2>
In item 1, the period is defined as a first period (HSW1). The timing generation circuit generates the internal horizontal synchronization signal for a plurality of times in the first cycle and once in a second cycle (HSW2, α) for each cycle (frame cycle: Fcyc) of the internal vertical synchronization signal. To do.

  Thereby, the timing generation circuit can be configured simply. Here, the number M of internal lines is the sum of the number N of display lines, the number of lines in the touch detection period, and the number of lines in the blanking period.

[3] <Register for setting POS1, HSW1, and HSW2>
In Item 2, the display driving device includes a register (1) in which the switching timing (POS1), the first period (HSW1), and the second period (HSW2) are set.

  As a result, the timing generation circuit can be simply configured, and the switching timing can be freely adjusted from the outside.

[4] <Hcyc × (M−α) + (Hcyc + 1) × α>
In item 1, the period is defined by the count number (Hcyc) of the clock (PCLK).

  The timing generation circuit generates the internal horizontal synchronization signal by counting the clocks. The timing generation circuit is configured such that, for each cycle (Fcyc) of the internal vertical synchronization signal, the internal horizontal synchronization signal having the cycle according to the count number and the internal horizontal synchronization having a cycle (Hcyc + 1) once more than the count number. Signal.

  Thereby, the timing generation circuit can be configured simply. The timing generation circuit generates an internal horizontal synchronization signal of cycle Hcyc M-α times and an internal horizontal synchronization signal of cycle Hcyc + 1 α times for each cycle (one frame cycle) of the internal vertical synchronization signal. The horizontal synchronization signal (discontinuous point) having a period shorter than the period Hcyc is not generated.

[5] <Register for setting Hcyc and M-α or α>
In the item 4, the display driving device may generate the internal horizontal sync signal in the cycle based on the count number and the count number for each cycle of the internal vertical sync signal, or a cycle that is one more than the count number. A register (1) for setting the number of times of generation of the internal horizontal synchronizing signal is provided.

  As a result, the timing generation circuit can be simply configured, and the switching timing can be freely adjusted from the outside.

[6] <Calculation circuit for Hcyc and α>
In item 4, the display driving device includes a register (1) in which the number of generations of the internal horizontal synchronization signal is set for each cycle (Fcyc) of the internal vertical synchronization signal. Further, the display driving device generates the internal horizontal synchronization signal having the cycle based on the count number (Hcyc) and the count number for each cycle of the internal vertical synchronization signal based on a value set in the register. There is provided an arithmetic circuit (6, 7, 8, 9) for calculating the number of times (M-α) or the number of times (α) of the internal horizontal synchronization signal to be generated with a period one time larger than the count number.

  As a result, external register settings can be minimized.

[7] <IC (Integrated Circuit) that combines display drive and touch detection function>
Item 7. The display driver according to any one of Items 1 to 6, wherein the display driving device is formed on a single semiconductor substrate.

  As a result, it is possible to provide an IC in which display driving and a touch detection function are mixedly mounted.

[8] <Display drive device with a separate chip configuration from the touch panel controller>
A typical embodiment disclosed in the present application is a display driving device (101) mounted on a display device (1001) including a display panel (200), a touch panel (300), and a touch panel controller (500). And a timing generation circuit (10) and a display drive circuit (20).

  The timing generation circuit generates an internal vertical synchronization signal (Vsync_int) and an internal horizontal synchronization signal (Hsync_int) from an external vertical synchronization signal (Vsync_ext) and an external horizontal synchronization signal (Hsync_ext) supplied from the outside.

  The display driving circuit performs a display driving operation in synchronization with the internal horizontal synchronization signal during a display driving period, and performs a touch detection operation in synchronization with the internal horizontal synchronization signal for the touch panel controller during a touch detection period. Outputs a control signal for causing

  The timing generation circuit repeatedly generates the internal horizontal synchronization signal for each set cycle (HSW1, Hcyc) from the switching timing (POS1) defined based on the external or internal vertical synchronization signal.

  The switching timing is set to a period other than the display driving period and the touch detection period.

  Thereby, when performing a time-division operation of display drive and touch detection using a touch panel controller and a display drive device constituted by another chip, the same effect as item 1 can be obtained.

[9] <HSW1 × M + HSW2>
In item 8, the period is defined as a first period (HSW1). The timing generation circuit generates the internal horizontal synchronization signal for a plurality of times in the first cycle and once in a second cycle (HSW2, α) for each cycle (Fcyc) of the internal vertical synchronization signal.

  Thereby, the timing generation circuit can be configured simply.

[10] <Register for setting POS1, HSW1, and HSW2>
In item 9, the display driving device includes a register (1) in which the switching timing, the first period, and the second period are set.

  As a result, the timing generation circuit can be simply configured, and the switching timing can be freely adjusted from the outside.

[11] <Hcyc × (M−α) + (Hcyc + 1) × α>
In item 8, the period is defined by the count number (Hcyc) of the clock (PCLK).

  The timing generation circuit generates the internal horizontal synchronization signal by counting the clocks. The timing generation circuit is configured such that, for each cycle (Fcyc) of the internal vertical synchronization signal, the internal horizontal synchronization signal having the cycle according to the count number and the internal horizontal synchronization having a cycle (Hcyc + 1) once more than the count number. Signal.

  Thereby, the timing generation circuit can be configured simply. The timing generation circuit generates an internal horizontal synchronization signal of cycle Hcyc M-α times and an internal horizontal synchronization signal of cycle Hcyc + 1 α times for each cycle of the internal vertical synchronization signal. A horizontal synchronization signal (discontinuous point) with a short cycle is not generated.

[12] <Register for setting Hcyc and M-α or α>
In the item 11, the display driving device has the number of generations of the internal horizontal synchronization signal in the cycle based on the count number and the count number for each cycle of the internal vertical synchronization signal, or a cycle that is one more than the count number. A register (1) for setting the number of times of generation of the internal horizontal synchronizing signal is provided.

  As a result, the timing generation circuit can be simply configured, and the switching timing can be freely adjusted from the outside.

[13] <Hcyc and α calculation circuit>
In Item 11, the display driving device includes a register (1) in which the number of generations of the internal horizontal synchronization signal is set for each cycle (Fcyc) of the internal vertical synchronization signal. Further, the display driving device generates the internal horizontal synchronization signal having the cycle based on the count number (Hcyc) and the count number for each cycle of the internal vertical synchronization signal based on a value set in the register. There is provided an arithmetic circuit (6, 7, 8, 9) for calculating the number of times (M-α) or the number of times (α) of the internal horizontal synchronization signal to be generated with a period one time larger than the count number.

  As a result, external register settings can be minimized.

[14] <Display driver IC using a touch panel controller chip>
In any one of Items 8 to 13, the display driving device is formed on a single semiconductor substrate.

  Thereby, it is possible to provide a display driving IC as a chip by touch panel controller.

[15] <Display device>
A typical embodiment disclosed in the present application is a display device (1000; 1001) including a display panel (200), a touch panel (300), a touch panel controller (30; 500), and a display driving device (100; 101). And, it is configured as follows.

  The display driving device includes a timing generation circuit (10) and a display driving circuit (20). The timing generation circuit generates an internal vertical synchronization signal (Vsync_int) and an internal horizontal synchronization signal (Hsync_int) from an external vertical synchronization signal (Vsync_ext) and an external horizontal synchronization signal (Hsync_ext) supplied from the outside. The display driving circuit performs a display driving operation in synchronization with the internal horizontal synchronization signal during a display driving period.

  The touch panel controller includes a touch panel control circuit (30) that performs a touch detection operation on the touch panel in synchronization with the internal horizontal synchronization signal during a touch detection period.

  The timing generation circuit repeatedly generates the internal horizontal synchronization signal for each set cycle (HSW1, Hcyc) from a switching timing defined based on the external or internal vertical synchronization signal.

  The switching timing is set to a period other than the display driving period and the touch detection period.

  Thus, in a display device that includes a display panel, a touch panel, a touch panel controller, and a display drive device and that performs time-division operations for display drive and touch detection, the same operational effects as in item 1 can be achieved.

[16] <HSW1 × M + HSW2>
In item 15, the period is defined as a first period (HSW1). The timing generation circuit generates the internal horizontal synchronization signal for a plurality of times in the first cycle and once in a second cycle (HSW2, α) for each cycle (Fcyc) of the internal vertical synchronization signal.

  Thereby, the timing generation circuit can be configured simply.

[17] <Register for setting POS1, HSW1, and HSW2>
In item 16, the front display device includes a register (1) in which the switching timing, the first period, and the second period are set.

  As a result, the timing generation circuit can be simply configured, and the switching timing can be freely adjusted from the outside.

[18] <Hcyc × (M−α) + (Hcyc + 1) × α>
In item 15, the period is defined by the count number (Hcyc) of the clock (PCLK). The timing generation circuit generates the internal horizontal synchronization signal by counting the clocks. The timing generation circuit is configured such that, for each cycle (Fcyc) of the internal vertical synchronization signal, the internal horizontal synchronization signal having the cycle according to the count number and the internal horizontal synchronization having a cycle (Hcyc + 1) once more than the count number. Signal.

  Thereby, the timing generation circuit can be configured simply. The timing generation circuit generates an internal horizontal synchronization signal of cycle Hcyc M-α times and an internal horizontal synchronization signal of cycle Hcyc + 1 α times for each cycle of the internal vertical synchronization signal. A horizontal synchronization signal (discontinuous point) with a short cycle is not generated.

[19] <Register for setting Hcyc and M-α or α>
Item 18. The display device according to Item 18, wherein the display device is configured to generate the internal horizontal synchronization signal in the cycle based on the count number and the count number for each cycle of the internal vertical synchronization signal, or the cycle having a cycle one more than the count number. A register (1) in which the number of internal horizontal synchronization signal generations is set is provided.

  As a result, the timing generation circuit can be simply configured, and the switching timing can be freely adjusted from the outside.

[20] <Calculation circuit for Hcyc and α>
In Item 18, the display device includes a register (1) in which the number of generations of the internal horizontal synchronization signal for each cycle of the internal vertical synchronization signal is set. Further, the display device generates the internal horizontal synchronization signal of the cycle based on the count number (Hcyc) and the count number of each cycle of the internal vertical synchronization signal based on a value set in the register. And an arithmetic circuit (6, 7, 8, 9) that calculates (M-α) or the number of generations (α) of the internal horizontal synchronization signal having a cycle one more than the count number.

  As a result, external register settings can be minimized.

2. Details of Embodiments Embodiments will be further described in detail.

[Embodiment 1] <Discontinuous point of internal horizontal sync signal is set to arbitrary timing>
FIG. 1 is a block diagram of a display device 1000 according to an embodiment of the present invention.

  The display device 1000 includes, for example, a display panel 200, a touch panel 300, a display driving device 100, and a host processor (HOST) 400. The display device 1000 may be externally attached without including the host processor 400.

  The display panel 200 is, for example, a liquid crystal display (LCD) panel, and a plurality of pixel cells arranged at a plurality of gate lines, a plurality of source lines orthogonal to the gate lines, and intersections of the gate lines and the source lines. Consists of. Luminance signals corresponding to image data to be displayed from the plurality of source lines are supplied to the plurality of pixel cells arranged on one line selected by one gate line, and selected by the gate line. Each pixel cell takes in its luminance signal and displays the corresponding luminance. The plurality of gate lines are sequentially scanned within one frame period, and a luminance signal is supplied to all the pixel cells in one frame. The pixel cell holds the supplied luminance signal and maintains the display of the corresponding luminance.

  The touch panel 300 is stacked on the display panel 200 by, for example, an in-cell method, and has a function of performing, for example, capacitive touch detection. A capacitance value of the sensor capacitance is detected by applying a pulse for charging a plurality of sensor capacitors arranged on the touch panel and detecting the amount of electric charge to be discharged. When the user's finger approaches or touches the touch panel 300 (referred to as “touch” including “approach” and “contact” in this specification), the capacitance value of the sensor capacitance changes. By detecting, the touched coordinates are detected. For capacitive touch detection, a mutual capacitance method, a self-capacitance method, or the like is employed.

  The display drive device 100 includes, for example, a display drive circuit 20, a touch detection circuit 30, a timing generation circuit 10, a sub processor (MPU) 40, and a power supply circuit 50. The display driving circuit 20 supplies a signal for scanning the gate line and a signal for driving the source line to the display panel 200. The touch detection circuit 30 supplies a drive signal for charging the sensor capacitance to the touch panel 300 and receives a signal for detecting a change in the capacitance of the sensor capacitance. The timing generation circuit 10 uses an internal vertical synchronization signal Vsync_int used internally based on a vertical synchronization signal Vsync_ext, a horizontal synchronization signal Hsync_ext, a pixel clock PCLK, an image data enable signal ENAB, and the like supplied from the outside such as the host processor 400. In addition, a timing control signal such as the internal horizontal synchronization signal Hsync_int is generated and supplied to the display drive circuit 20 and the touch detection circuit 30. The power supply circuit 50 boosts, steps down, stabilizes power such as Vcc supplied from the outside, and supplies it to internal circuits of the display driving device 100 such as the display driving circuit 20 and the touch detection circuit 30.

  The display drive circuit 20 includes a host interface (HOST I / F) 21, a control circuit 22, a line memory 23, a bidirectional shift register (S / R) 24, a latch circuit 25, a source line drive circuit 26, It includes a gate line driving circuit 27, a gradation voltage generating circuit 28, and the like. The display drive circuit 20 receives image data (DATA_R7-0, DATA_G7-0, DATA_B7-0), vertical synchronization signal Vsync_ext, horizontal synchronization signal Hsync_ext, pixel clock PCLK, image data from the host processor 400 via the host interface 21. A timing signal such as an enable signal ENAB and a control command are received. Although FIG. 1 specifically illustrates 8-bit image data DATA_R7-0, DATA_G7-0, DATA_B7-0, etc. for each of the three primary colors, the specifications of the communication interface are arbitrary. The control circuit 22 incorporates a register (not shown) for holding various control modes and control parameters, and the display drive circuit 20 has a control mode and control parameters written into the registers via the host interface 21 from the host processor 400. Control the behavior.

  The gate line driving circuit 27 generates a control signal for sequentially scanning a plurality of gate lines of the display panel 200 and supplies the control signal to the display panel 200. When the display panel 200 includes terminals corresponding to the plurality of gate lines, a signal for driving the plurality of gate lines is supplied. When the display panel 200 includes a circuit that scans the gate line, for example, when the display panel 200 includes a shift register called a gate in panel (GIP), a start flag supplied to the shift register And supply the clock.

  Image data (DATA_R7-0, DATA_G7-0, DATA_B7-0) received from the host processor 400 via the host interface 21 is latched as image data for one line via the line memory 23 and the bidirectional shift register 24. It is written in the circuit 25. The line memory 23 and the bidirectional shift register 24 perform buffering and timing adjustment between received image data and displayed image data. If the reception and display are synchronized accurately, timing adjustment is not necessary. However, if there is a difference in speed, the received image data is temporarily buffered to absorb the difference, and The data is transferred to the latch circuit 25 at a proper timing. The image data for one line held in the latch circuit 25 is supplied to the source line driving circuit 26 in parallel. The gradation voltage generation circuit 28 generates a plurality of gradation voltages that are analog voltage values corresponding to the gradations of the image data that are digital values, and supplies them to the source line driving circuit 26. The source line driving circuit 26 selects or generates a gradation voltage corresponding to the supplied image data, and drives the source line of the display panel 200.

  The touch detection circuit 30 includes, for example, a sensor capacitance drive circuit 32, a capacitance change detection circuit 33, a RAM 34, and a control circuit 31. The sensor capacitance drive circuit 32 generates and supplies drive pulses for sequentially driving a plurality of sensor capacitors arranged on the touch panel 300. The capacitance change detection circuit 33 is a circuit that detects the movement of charges that are generated when the sensor capacitance is charged and discharged by a drive pulse. The capacitance change detection circuit 33 converts the detected charge amount or change amount into a digital value and stores it in the RAM 34. Write. The control circuit 31 incorporates a register (not shown) that holds various control modes and control parameters, and controls the operation of the touch detection circuit 30 in accordance with the control mode and control parameters written from the sub processor 40 to these registers.

  The problem to be solved by the invention will be described in more detail.

  FIG. 2 is a timing chart showing an operation example when the time division operation of display driving and touch detection is not performed. The horizontal axis represents time, and in the vertical axis direction, external vertical synchronization signal Vsync_ext, external horizontal synchronization signal Hsync_ext, image data, internal vertical synchronization signal Vsync_int, internal horizontal synchronization signal Hsync_int, and source output are schematically shown from the top. It is. The external vertical synchronization signal Vsync_ext is a synchronization signal indicating the start timing of one frame period, and the external horizontal synchronization signal Hsync_ext is a synchronization signal indicating the start timing of one line period. Both are negative logic and are shown as being asserted at low level and negated at high level, but may be positive logic. Several line periods VFP (time t1 to t3) before the external vertical synchronization signal Vsync_ext is asserted and several line periods VBP (time t3 to t4) after the assertion are in a blanking period (non-display period) described later. Correspondingly, the input image data is invalid data. The supply of valid image data is started after VBP (time t4) from the time (time t3) when the external vertical synchronization signal Vsync_ext is asserted. The internal vertical synchronization signal Vsync_int and the internal horizontal synchronization signal Hsync_int are synchronized with the external vertical synchronization signal Vsync_ext and the external horizontal synchronization signal Hsync_ext, respectively. After the VBP (time t4) from the time when the external vertical synchronization signal Vsync_ext is asserted (time t4), the supply of valid image data is started, and after the one line period (time t5), the Nth The source line drive circuit 26 supplies the corresponding source output to the display panel 200 up to the line. The period from time t2 to t5 is a blanking period and a non-display period. Source output corresponding to invalid image data input during a period corresponding to the blanking period is stopped. Here, the non-display period is paired with the display period or the display drive period, the non-display period is a period during which the source line is not driven, and the display period or the display drive period is a period during which the source line is driven. For example, in the case of a liquid crystal display panel, the charge corresponding to the pixel value is held in the pixel capacitor and the display itself is maintained, but the pixel from the source line to the pixel capacitor is not the entire period during which the display is maintained. Only the period during which values are transferred is called a display period or a display drive period.

  FIG. 3 is a timing chart illustrating an operation example of the display driving device that performs time-division operation of display driving and touch detection. As in FIG. 2, the horizontal axis is time, and in the vertical axis direction, from the top, external vertical synchronization signal Vsync_ext, external horizontal synchronization signal Hsync_ext, image data, internal vertical synchronization signal Vsync_int, internal horizontal synchronization signal Hsync_int, and source The output is shown schematically. As in the case of not performing the time division shown in FIG. 2, several line periods VFP (time t1 to t3) before the external vertical synchronization signal Vsync_ext is asserted and several line periods VBP (times t3 to 3) after being asserted. The image data input at t4) is invalid data. The supply of valid image data is started after VBP (time t4) from the time (time t3) when the external vertical synchronization signal Vsync_ext is asserted. The internal vertical synchronization signal Vsync_int is synchronized with the external vertical synchronization signal Vsync_ext, but the cycle of the internal horizontal synchronization signal Hsync_int is shorter than that of the external horizontal synchronization signal Hsync_ext, and is given by, for example, a register setting value HSW1. In the case of FIG. 2 in which the time division operation is not performed, the number of pulses of the internal horizontal synchronization signal Hsync_int per frame is the sum of the number of lines N displayed in one frame and the number of pulses corresponding to the blanking period. Thus, the number of pulses (internal line number M) of the internal horizontal synchronization signal Hsync_int per frame in the case of FIG. It can be. After the time when the external vertical synchronization signal Vsync_ext is asserted (time t3) and after the VBP (time t4), the supply of valid image data is started, and after time t7 after a delay corresponding to the line memory, every line. The source line driving circuit 26 supplies the corresponding source output to the display panel 200 up to the Nth line. FIG. 3 shows the end of the previous frame. By the time t4, the source output of the Nth line is finished and the source output is stopped. Among the times t4 to t7 when the source output is stopped, the period from time t4 to t6 is set as the touch detection period TW, and the period from time t6 to t7 is set as the retrace period. The delay corresponding to the line memory at times t5 to t7 is a period necessary for accumulating data in a buffer provided to absorb the difference between the input speed of the image data and the speed of the source output. Since the source output speed is faster than the input speed, it is necessary to buffer the image data in order to prevent a shortage of image data to be output. For example, in the display driving apparatus 100 shown in FIG. 1, the line memory 23 and the bidirectional shift register 24 constitute a buffer.

  As described above, the internal horizontal synchronization signal Hsync_int is given a period, for example, by the register setting value HSW1, and is periodically output after the internal vertical synchronization signal Vsync_int is asserted. The period HSW1 is arbitrarily set and does not necessarily become an integer of one frame period. Therefore, at the end of one frame period, a period (time t2 to t3) having a period α shorter than the given period HSW1, that is, There is a possibility that discontinuity of the internal horizontal synchronization signal Hsync_int occurs. As shown in FIG. 3, when this discontinuity occurs in the effective source output period, the period is not sufficient to transfer the grayscale voltage to the pixel capacitor, which may cause abnormal display. This is as explained in “Problems to be Solved by the Invention”.

  FIG. 4 is a timing chart showing an example in which a discontinuous point of the internal horizontal synchronization signal Hsync_int occurs during the display drive period. FIG. 4 is an enlarged view in the vicinity of a period from time t1 to t3 in FIG. 3. As described above, at times t2 to t3 which are the end of one frame period, a discontinuous point having a cycle α shorter than the cycle HSW1 to which the cycle of the internal horizontal synchronization signal Hsync_int is given occurs.

  When the cycle HSW1 is made smaller and the touch detection period TW is lengthened, or when the amount of buffered data (number of lines) is reduced, the discontinuous point of the internal horizontal synchronization signal Hsync_int is touched instead of the display period. May occur during the detection period. FIG. 5 is a timing chart illustrating an example in which a discontinuous point of the internal horizontal synchronization signal Hsync_int occurs in the touch detection period. The source output of the final line N is completed at time t8 before time t12 when the internal vertical synchronization signal Vsync_int is asserted, and the touch detection period (time t8 to t12) is started. In the touch detection operation, a drive period (time t8 to t9 and t10 to t11) for driving the sensor capacity and a sense period (time t9 to t10 and t11 to t12) for detecting a capacity change are alternately repeated. In the example shown in FIG. 5, since the cycle of the last internal horizontal synchronization signal Hsync_int at times t11 to t12 is a discontinuous point that is shorter than the cycle HSW1 to be given, the corresponding sense period is It will be shorter than other sense periods. For this reason, the accuracy of touch detection may be reduced. When the discontinuous point of the internal horizontal synchronization signal Hsync_int occurs during the drive period, the sensor capacitance is insufficiently charged, and the touch detection accuracy may similarly decrease.

  The display driving circuit and the display device according to the present invention include a timing generation circuit 10 in order to solve the above-described problems.

  FIG. 6 is a block diagram illustrating a configuration example of the timing generation circuit 10 according to the first embodiment. The timing generation circuit 10 is supplied with an external vertical synchronization signal Vsync_ext and a pixel clock PCLK, and is supplied with register setting values HSW1, HSW2, and POS1 from the register circuit 1, and an internal vertical synchronization signal Vsinc_int and an internal horizontal synchronization signal. Hsync_int is generated and output. The timing generation circuit 10 includes an internal synchronization signal generation circuit 2, a line counter 3, a comparison circuit 4 and a selector 5. The internal synchronization signal generation circuit 2 generates an internal vertical synchronization signal Vsinc_int that is synchronized with the external vertical synchronization signal Vsync_ext, and generates an internal horizontal synchronization signal Hsync_int at a period given by Hcyc_SEL from the time when the internal vertical synchronization signal Vsinc_int is asserted. . The line counter 3 is reset by the internal vertical synchronization signal Vsinc_int, counts the internal horizontal synchronization signal Hsync_int, and outputs a line count value LCNT. The comparison circuit 4 compares the line count value LCNT with the set value POS1 given from the register 1, and asserts the output SEL when the line count value LCNT exceeds POS1. The selector 5 outputs HSW1 as Hcyc_SEL during the period when SEL is negated and HSW2 during the period when SEL is asserted.

  FIG. 7 is a timing chart illustrating an operation example of the display driving apparatus 100 according to the first embodiment. Similar to FIGS. 2 and 3, the horizontal axis represents time, and in the vertical axis direction, from the top, external vertical synchronization signal Vsync_ext, external horizontal synchronization signal Hsync_ext, image data, internal vertical synchronization signal Vsync_int, internal horizontal synchronization signal Hsync_int, And the source output is shown schematically. As in the case of not performing time division shown in FIG. 2, several line periods VFP (time t1 to t3) before the external vertical synchronization signal Vsync_ext is asserted and several line periods VBP (time t3) after being asserted. The image data input at t5) is invalid data. The supply of valid image data is started after VBP (time t5) from the time (time t3) when the external vertical synchronization signal Vsync_ext is asserted. The internal vertical synchronization signal Vsync_int is synchronized with the external vertical synchronization signal Vsync_ext, but the cycle of the internal horizontal synchronization signal Hsync_int is shorter than that of the external horizontal synchronization signal Hsync_ext and is given by the set value HSW1 of the register 1. After the VBP (time t5) from the time when the external vertical synchronization signal Vsync_ext is asserted (time t5), the supply of valid image data is started, and then from time t7 after a delay corresponding to the line memory, every line. The source line driving circuit 26 supplies the corresponding source output to the display panel 200 up to the Nth line. FIG. 7 shows the end of the previous frame as in FIG. By the time t4, the source output of the Nth line is finished and the source output is stopped. Among the times t4 to t7 when the source output is stopped, the period from time t4 to t6 is set as the touch detection period TW, and the period from time t6 to t7 is set as the blanking period. The delay corresponding to the line memory at times t5 to t7 is a period necessary for accumulating data in a buffer provided to absorb the difference between the input speed of the image data and the speed of the source output.

  In the operation example shown in FIG. 7, a discontinuous point having a cycle α shorter than the cycle HSW1 to which the cycle of the internal horizontal synchronization signal Hsync_int is given occurs during a period from time t8 to t9. In the example shown in FIG. 3, a new cycle HSW1 of the internal horizontal synchronization signal Hsync_int is forcibly started when the internal vertical synchronization signal Vsync_int is asserted. On the other hand, in the present embodiment, the switching of the cycle of the internal horizontal synchronization signal Hsync_int is delayed until the value of POS1 set in the register 1 matches the line count value LCNT. By appropriately adjusting the register setting value of POS1, the timing at which the discontinuity occurs can be within the blanking period that is neither the display drive period nor the touch detection period. Even if the cycle of the internal horizontal synchronization signal Hsync_int is a value α shorter than the normal cycle, by setting the period during which neither the display drive nor the touch detection is performed, without causing a display abnormality, and Thus, it is possible to prevent a decrease in touch detection accuracy.

  The set values POS1, HSW1, and HSW2 for the register 1 will be described in more detail.

  FIG. 8 is a timing chart showing an example of the generation timing of the internal horizontal synchronization signal Hsync_int in the display driving apparatus 100 corresponding to FIG. The horizontal axis represents time, and the waveforms of the internal vertical synchronization signal Vsync_int and the internal horizontal synchronization signal Hsync_int are schematically shown in the vertical axis direction. This is an example in which a cycle α of discontinuous points is set in HSW2. Within one frame period Fcyc, an internal horizontal synchronization signal Hsync_int having a period HSW1 corresponding to the number M of internal lines is generated, and finally a period α of a discontinuous point set in HSW2 appears. This corresponds to the operation of FIG. Here, the number M of internal lines is the sum of the number N of display lines, the number of lines in the touch detection period, and the number of lines in the blanking period. By setting an appropriate value for POS1, it is possible to arbitrarily adjust the time at which a discontinuity occurs with respect to the internal vertical synchronization signal Vsync_int (see FIG. 7).

  FIG. 9 is a timing chart showing another example of the generation timing of the internal horizontal synchronization signal Hsync_int. HSW1 is the same, but HSW1 + α is set in HSW2. As a result, the cycle of the internal horizontal synchronization signal Hsync_int of the Mth line becomes HSW1 + α, which is larger than HSW1. In the display drive period and the touch detection period, when the internal horizontal synchronization signal Hsync_int has a specification that does not cause a problem as long as the cycle of the internal horizontal synchronization signal Hsync_int is equal to or higher than HSW1, the generation time of the discontinuous point is determined by the POS1 in the blanking period There is no need to adjust.

[Embodiment 2] <Embodiment in which discontinuous points are not generated in the internal horizontal synchronizing signal>
In the example shown in FIG. 9, the period of the internal horizontal synchronization signal Hsync_int at the discontinuous point is made longer than the normal period HSW1, so that even if the discontinuous point occurs in the display period or the touch detection period, an abnormal display is displayed. It is not generated, and a decrease in touch detection accuracy can be prevented. In the second embodiment, this is further developed, and the display driving apparatus 100 is configured so as not to generate discontinuous points. The configurations of the display device 1000 and the display driving device 100 are the same as those of the display device 1000 and the display driving device 100 of the first embodiment shown in the block diagram of FIG. 1, but the configurations of the timing generation circuit 10 are different.

  FIG. 10 is a block diagram illustrating a configuration example of the timing generation circuit 10 according to the second embodiment. The timing generation circuit 10 is supplied with the external vertical synchronization signal Vsync_ext and the pixel clock PCLK. The register circuit 1 is supplied with Hcyc, Hcyc + 1, and α as register setting values, and the internal vertical synchronization signal Vsinc_int and the internal horizontal synchronization signal. Hsync_int is generated and output. The timing generation circuit 10 includes an internal synchronization signal generation circuit 2, a line counter 3, a comparison circuit 4 and a selector 5. The internal synchronization signal generation circuit 2 generates an internal vertical synchronization signal Vsinc_int that is synchronized with the external vertical synchronization signal Vsync_ext, and generates an internal horizontal synchronization signal Hsync_int at a period given by Hcyc_SEL from the time when the internal vertical synchronization signal Vsinc_int is asserted. . The line counter 3 is reset by the internal vertical synchronization signal Vsinc_int, counts the internal horizontal synchronization signal Hsync_int, and outputs a line count value LCNT. The comparison circuit 4 compares the line count value LCNT with the set value α given from the register 1 and asserts the output SEL when the line count value LCNT exceeds α. The selector 5 outputs Hcyc + 1 as Hcyc_SEL when SEL is negated and Hcyc + 1 when SEL is asserted. Here, Hcyc is a period which is normally required as the internal horizontal synchronization signal Hsync_int, and α is a remaining period when the internal horizontal synchronization signal Hsync_int having M periods Hcyc is generated in one frame period Fcyc. Hcyc and α are expressed as integers as the count number of the pixel clock PCLK.

  FIG. 11 is a timing chart illustrating an operation example of the display driving apparatus 100 according to the second embodiment. As in FIGS. 8 and 9, the horizontal axis represents time, and the waveforms of the internal vertical synchronization signal Vsync_int and the internal horizontal synchronization signal Hsync_int are schematically shown in the vertical axis direction. The internal horizontal synchronization signal Hsync_int is generated with the cycle Hcyc + 1 for the α line after the internal vertical synchronization signal Vsync_int is asserted, and with the cycle Hcyc for the subsequent M-α line. The remaining period α when the internal horizontal synchronization signal Hsync_int having M cycles Hcyc is generated in one frame period Fcyc is distributed to the α line, and the cycle is increased by 1 from Hcyc to Hcyc + 1. Accordingly, it is possible to configure so that discontinuous points are not generated in the internal horizontal synchronization signal Hsync_int. Strictly speaking, the cycle is discontinuous due to switching from the cycle Hcyc + 1 to Hcyc, but display drive and touch detection do not adversely affect the operation even if there is an error in the cycle of the internal horizontal synchronization signal Hsync_int. So there is no problem.

  FIG. 12 is a more detailed timing chart showing an example of the generation timing of the internal horizontal synchronization signal in the display driving apparatus of the second embodiment. In this example, one frame period Fcyc is set to 300,000 as the period of the pixel clock PCLK, and the number of internal lines M = 510 lines. If Fcyc is divided by the number of internal lines M (300000 ÷ 510), the quotient is 588 and the remainder is 120. α = 120, Hcyc = 588, and Hcyc + 1 = 589 are set. As shown in FIG. 12, the α (120) line after the internal vertical synchronization signal Vsync_int is asserted has a period Hcyc + 1 (589), and the remaining M-α (390) line has a period Hcyc (588). Is done.

  FIG. 13 is a block diagram illustrating another configuration example of the timing generation circuit 10 according to the second embodiment. In the timing generation circuit 10 shown in FIG. 10, Hcyc, Hcyc + 1 and α are all set in the register 1, whereas in FIG. 13, the number of internal lines M is set in the register 1, and Hcyc, Hcyc + 1 and α are set. Is calculated and supplied to a circuit similar to the timing generation circuit 10 shown in FIG. (FIG. 13 shows only a circuit added to FIG. 10.) In addition to the configuration shown in FIG. 10, the timing generation circuit 10 further includes a Vcyc counter 6, a Vcyc latch 7, a divider circuit 8, and a +1 circuit. 9 is further included. The Vcyc counter 6 counts the internal vertical synchronization signal Vsync_int by the pixel clock PCLK. The count value of the Vcyc counter 6 is latched in the Vcyc latch 7 and the Vcyc counter 6 is reset every one cycle of the internal vertical synchronization signal Vsync_int, that is, every one frame cycle Fcyc. In the Vcyc latch 7, the frame period Fcyc (Vcyc value) is obtained by automatic measurement and held (latched). Since the frame period Fcyc does not fluctuate, the operation of the Vcyc counter 6 needs to be performed only once when the power is turned on. In an application in which the frame period Fcyc fluctuates, it may be re-measured at appropriate times. The division circuit 8 calculates Hcyc as a quotient when the measured frame period Fcyc (Vcyc value) is divided by the number M of internal lines, and calculates α as a remainder. The +1 circuit 9 adds 1 to the Hcyc value and obtains and outputs the calculated Hcyc + 1 value. As a result, the storage capacity of the register 1 is reduced, and the parameter setting operation for the register 1 is simplified.

[Embodiment 3] <Structure of touch panel controller in a separate chip>
In the first and second embodiments, the display driver 1000 has been described on the premise of the configuration example shown in FIG. 1 in which the display driving device 20 and the touch detection circuit 30 are integrated in the display driving device 100. However, the display driver IC is a display driver IC. The display drive device 101 and the touch panel controller 500 may be configured as separate chips.

  FIG. 14 is a block diagram of a display device 1001 according to another embodiment of the present invention.

  The display device 1001 includes a display panel 200, a touch panel 300, a display driving device 101 that is a display driver IC, a touch panel controller 500, and a host processor (HOST MPU) 401. In some cases, the host processor 401 is not included in the display device 1001 and is externally attached. The display panel 200 and the touch panel 300 are as described with reference to FIG.

  The display drive device 101 which is a display driver IC is similar to the display drive circuit 20 in the display drive device 100 shown in FIG. 1, a host interface (HOST I / F) 21, a control circuit 22, a line memory 23, a bidirectional The circuit includes a shift register (S / R), a latch circuit 25, a source line driver circuit 26, a gate line driver circuit 27, a gradation voltage generation circuit 28, and further includes a timing generation circuit 10 and a power supply circuit 50. The touch panel controller 500 includes a sensor capacitance drive circuit 32, a capacitance change detection circuit 33, a RAM 34, and a control circuit 31. The operations of the display driving device 101 and the touch panel controller 500 are the same as the operations of the display driving circuit 20 and the touch detection circuit 30 described with reference to FIG. The sub processor (MPU) 40 shown in FIG. 1 is omitted, and the host processor 401 also has the function.

  The timing generation circuit 10 incorporated in the display driving device 101 is based on the vertical synchronization signal Vsync_ext, the horizontal synchronization signal Hsync_ext, the pixel clock PCLK, the image data enable signal ENAB, and the like supplied from the host processor 401. Timing control signals such as Vsync_int and internal horizontal synchronization signal Hsync_int are generated and supplied to the control circuit 22 in the display driving device 101 and also supplied to the control circuit 31 of the touch panel controller 500. The power supply circuit 50 boosts, steps down, stabilizes power such as Vcc supplied from the outside, and supplies it to the gate line drive circuit 27, the source line drive circuit 26, the gradation voltage generation circuit 28, and the like.

  In order to operate display drive and touch detection in a time-sharing manner, the display drive device 101 supplies a touch detection enable signal TEN to the touch panel controller 500 in addition to the internal vertical synchronization signal Vsync_int and the internal horizontal synchronization signal Hsync_int. In the one frame period, when the display period ends, the display driving device 101 asserts the touch detection enable signal TEN to cause the touch panel controller 500 to perform the touch detection operation, and before the display driving period of the next frame starts, The touch detection enable signal TEN is negated to cause the touch panel controller 500 to stop the touch detection operation. Instead of the touch detection enable signal TEN, the display drive enable signal may be supplied to the display drive device 101 from the touch panel controller 500 side. Further, the control circuits 22 and 31 of the display drive device 101 and the touch panel controller 500 count internal horizontal synchronization signals, respectively, and are configured to autonomously perform display drive and touch detection operations based on the count values, As a result, it may be configured to perform a time division operation.

  FIG. 15 is a timing chart showing an operation example of the display driving apparatus of FIG. As in FIG. 7, the horizontal axis is time, and in the vertical axis direction, from the top, external vertical synchronization signal Vsync_ext, external horizontal synchronization signal Hsync_ext, image data, internal vertical synchronization signal Vsync_int, internal horizontal synchronization signal Hsync_int, and source An output is schematically shown, and a touch detection enable signal TEN is also shown. The operations of the external vertical synchronization signal Vsync_ext, the external horizontal synchronization signal Hsync_ext, image data, the internal vertical synchronization signal Vsync_int, the internal horizontal synchronization signal Hsync_int, and the source output are the same as those described in the first and second embodiments. be able to. That is, as shown in FIG. 7, the POS 1 can adjust the generation time of the discontinuous point of the internal horizontal synchronization signal Hsync_int to be delayed until the retrace period. Further, as shown in FIG. 9, the discontinuous point of the internal horizontal synchronizing signal Hsync_int can be set to HSW1 + α longer than the normal cycle HSW1. Further, as shown in FIG. 11, it can be configured not to generate a discontinuous point of the internal horizontal synchronization signal Hsync_int. In any of the modifications, the touch detection enable signal TEN is asserted during the touch detection period TW from time t4 to t6 as illustrated in FIG. During the period when the touch detection enable signal TEN is asserted, the control circuit 31 of the touch panel controller 500 drives the sensor capacitance of the touch panel by the sensor capacitance driving circuit 32 and detects the capacitance change of the sensor capacitance by the capacitance change detection circuit 33. The touch detection operation is executed.

  As described above, even when the display driver IC and the touch panel controller are configured as separate chips, the present invention can be similarly implemented.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the block division shown in the figure is an example, and the same function may be divided and implemented in different blocks, or a plurality of functions may be implemented in an integrated block. Further, the use of positive logic / negative logic of the signal is arbitrary. Although the case where the vertical synchronization signal and the horizontal synchronization signal are negative logic has been illustrated, all or part of them may be changed to positive logic. The same applies to other signals.

DESCRIPTION OF SYMBOLS 1 Register circuit 2 Internal synchronous signal generation circuit 3 Line counter 4 Comparison circuit 5 Selector 6 Fcyc counter 7 Fcyc latch 8 Division circuit 9 + 1 circuit 10 Timing generation circuit 20 Display drive circuit 21 Host interface (HOST I / F)
22 Control circuit 23 Line memory 24 Bidirectional shift register (S / R)
25 latch circuit 26 source line drive circuit 27 gate line drive circuit 28 gradation voltage generation circuit 30 touch detection circuit 31 control circuit 32 sensor capacitance drive circuit 33 capacitance change detection circuit 34 RAM
40 Subprocessor (MPU)
50 Power supply circuit 100, 101 Display driver 200 Display panel 300 Touch panel 400, 401 Host processor (HOST)
500 Touch panel controller 1000, 1001 Display device

Claims (10)

A timing generation circuit for generating an internal vertical synchronization signal and an internal horizontal synchronization signal from an external vertical synchronization signal supplied from the outside;
A display drive circuit for performing a display drive operation in synchronization with the internal horizontal synchronization signal during a display drive period;
A touch panel control circuit that performs a touch detection operation in synchronization with the internal horizontal synchronization signal during a touch detection period,
The timing generation circuit switches a cycle of the internal horizontal synchronization signal from a first cycle to a second cycle different from the first cycle at a switching timing defined based on the external vertical synchronization signal or the internal vertical synchronization signal. ,
The switching timing is set to a period other than the display driving period and the touch detection period.
Display drive device. The timing generation circuit generates the internal horizontal synchronization signal for each cycle of the internal vertical synchronization signal a plurality of times in the first cycle and once in the second cycle.
The display driving device according to claim 1. A register in which the switching timing, the first period, and the second period are set;
The display driving device according to claim 2. A timing generation circuit for generating an internal vertical synchronization signal and an internal horizontal synchronization signal from an external vertical synchronization signal supplied from the outside;
A display drive circuit for performing a display drive operation in synchronization with the internal horizontal synchronization signal during a display drive period;
A touch panel control circuit that performs a touch detection operation in synchronization with the internal horizontal synchronization signal during a touch detection period;
The timing generation circuit sets a cycle of the internal horizontal synchronization signal of a plurality of lines to a first cycle for each cycle of the internal vertical synchronization signal , and uses the external vertical synchronization signal or the internal vertical synchronization signal as a reference. A display driving device that switches the cycle of the internal horizontal synchronization signal of the last one line from the first cycle to a second cycle longer than the first cycle at a prescribed switching timing. A timing generation circuit for generating an internal vertical synchronization signal and an internal horizontal synchronization signal from an external vertical synchronization signal supplied from the outside;
A display drive circuit for performing a display drive operation in synchronization with the internal horizontal synchronization signal during a display drive period;
A touch panel control circuit that performs a touch detection operation in synchronization with the internal horizontal synchronization signal during a touch detection period;
The period of the internal horizontal synchronization signal is defined by the number of clock counts,
The timing generation circuit generates the internal horizontal synchronization signal by counting the clock;
The timing generation circuit includes, for each cycle of the internal vertical synchronization signal, a cycle of the internal horizontal synchronization signal, a first cycle for counting the clock up to a predetermined count number, and the clock according to the predetermined count number. Switch between the second cycle that counts once more ,
Display drive device. A register in which the count number and the number of generations of the internal horizontal synchronization signal in the first period or the number of generations of the internal horizontal synchronization signal in the second period are set;
The display driving device according to claim 5. Further, a register in which the number of generations of the internal horizontal synchronization signal for each cycle of the internal vertical synchronization signal is set, the count number based on a value set in the register, and the internal frequency in the first cycle An arithmetic circuit that calculates the number of horizontal synchronization signal generations or the number of generations of the internal horizontal synchronization signal in the second period,
The display driving device according to claim 5. A display device comprising a display panel, a touch panel, a touch panel controller, and a display driving device,
The display driver includes a timing generation circuit that generates an internal vertical synchronization signal and an internal horizontal synchronization signal from an external vertical synchronization signal supplied from outside, and a display drive operation in synchronization with the internal horizontal synchronization signal during a display drive period. A display drive circuit for performing
The touch panel controller includes a touch panel control circuit that performs a touch detection operation on the touch panel in synchronization with the internal horizontal synchronization signal during a touch detection period.
The timing generation circuit switches a cycle of the internal horizontal synchronization signal from a first cycle to a second cycle different from the first cycle at a switching timing defined based on the external vertical synchronization signal or the internal vertical synchronization signal. ,
The switching timing is set to a period other than the display driving period and the touch detection period.
Display device. A display device comprising a display panel, a touch panel, a touch panel controller, and a display driving device,
The display driving device includes a timing generation circuit that generates an internal vertical synchronizing signal and an internal horizontal synchronizing signal from an external vertical synchronizing signal supplied from the outside, and display driving in synchronization with the internal horizontal synchronizing signal during a display driving period. A display driving circuit for performing the operation,
The touch panel controller includes a touch panel control circuit that performs a touch detection operation in synchronization with the internal horizontal synchronization signal during a touch detection period.
The timing generation circuit sets a cycle of the internal horizontal synchronization signal of a plurality of lines to a first cycle for each cycle of the internal vertical synchronization signal , and uses the external vertical synchronization signal or the internal vertical synchronization signal as a reference. in defined the switching timing, the last one line of the internal horizontal synchronizing signal display period from the first period switching to longer second period than the first period of the. A display device comprising a display panel, a touch panel, a touch panel controller, and a display driving device,
The display driving device includes a timing generation circuit that generates an internal vertical synchronizing signal and an internal horizontal synchronizing signal from an external vertical synchronizing signal supplied from the outside, and display driving in synchronization with the internal horizontal synchronizing signal during a display driving period. A display driving circuit for performing the operation,
The touch panel controller includes a touch panel control circuit that performs a touch detection operation in synchronization with the internal horizontal synchronization signal during a touch detection period.
The period of the internal horizontal synchronization signal is defined by the number of clock counts,
The timing generation circuit generates the internal horizontal synchronization signal by counting the clock;
The timing generation circuit includes, for each cycle of the internal vertical synchronization signal, a cycle of the internal horizontal synchronization signal, a first cycle for counting the clock up to a predetermined count number, and the clock according to the predetermined count number. Switch between the second cycle that counts once more ,
Display device.

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