TWI802138B - Display driving circuit and display driving method threrof - Google Patents

Abstract

A display driving circuit and a display driving method are provided. The display driving circuit includes a timing control circuit and a display control circuit. The timing control circuit receives a synchronization signal, charge a plurality of gate lines in sequence with a charging time corresponding to the highest frame rate according to the synchronization signal, and disabling a display enable signal at the end of charging the gate lines. The display control circuit performs a display control according to the display enable signal. The timing control circuit determines whether to disable the display control circuit according to the display enable signal.

Description

Display driving circuit and display driving method thereof

The present invention relates to a display driving circuit, and in particular to a display driving circuit of a touch panel sensor chip and a display driving method thereof.

A touch panel sensor chip (Touch with Display Driver, TDDI) is widely used in the integrated application of the driver and the touch panel. In TDDI, the display drive circuit switches between high frame rate and low frame rate (HFR/LFR). The traditional method is to switch the display frequency by directly changing the charging time of each gate line. For example, when the frame rate is switched between 120Hz and 60Hz, the charging time of each gate line is set to be twice different between the frame rate of 120Hz and 60Hz, so as to change the display frequency. However, due to the change of the charging time of the gate line, the transmission speed (MIPI rate) of the mobile industry processor interface needs to be changed in the traditional method, which is prone to problems of antenna adaptation and EMI interference. Moreover, since the charging time of each gate line is different, an additional set of reference voltages is required in design, which will increase production time and cost. On the other hand, with the thinning of 3C products and battery thickness, the power saving performance of touch panel sensing chips will be a key challenge.

The present invention provides a display driving circuit and a display driving method thereof, which can reduce power consumption by disabling a display enable signal when the charging of the gate line is completed, and judging whether to disable the display control circuit according to the display enable signal.

An embodiment of the present invention provides a display driving circuit. The display driving circuit includes but not limited to a timing control circuit and a display control circuit. The timing control circuit receives the synchronous signal and sequentially charges the multiple gate lines at the charging time corresponding to the highest frame rate according to the synchronous signal, and disables the display enable signal when the charging of the multiple gate lines is completed. The display control circuit is coupled to the timing control circuit, and the display control circuit performs display control according to the display enabling signal. The timing control circuit judges whether to disable the display control circuit according to the display enable signal.

An embodiment of the present invention provides a display driving method, which is suitable for a display driving circuit. The display driving circuit includes a timing control circuit and a display control circuit. The display driving method includes: receiving a synchronization signal. Charge multiple gate lines sequentially with the charging time corresponding to the highest frame rate according to the synchronous signal. Disable display enable signal at the end of multiple gate line charging. According to the display enable signal, it is judged whether to disable the display control circuit.

Based on the above, in some embodiments of the present invention, by disabling the display enable signal when the charging of the gate line ends, and judging whether to disable the display control circuit according to the display enable signal, thereby reducing the analog circuit in the non-display time Power consumption, improve battery life.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

The term "coupled (or connected)" used throughout the specification (including claims) of this application may refer to any direct or indirect means of connection. For example, if it is described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or certain A connection means indirectly connected to the second device. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

FIG. 1 is a block diagram of a display driving circuit according to an embodiment of the invention. FIG. 2 is a flowchart of a display driving method according to an embodiment of the invention. 1 and 2, the display driver circuit 10 may be a touch panel sensing chip (Touch with Display Driver, TDDI), including but not limited to a timing control circuit 110 and a display control circuit 120, the display control circuit 120 is coupled to the timing control circuit 110. In one embodiment, the display driving circuit 10 receives the synchronization signal SYNC and the display data through the Mobile Industry Processor Interface (MIPI) (not shown), and the display driving circuit 10 receives the synchronization signal SYNC and the display data according to the synchronization signal SYNC and the display data. Display control is performed to provide display driving signals, and the display driving signals are used to drive the touch panel (not shown) to display images.

In one embodiment, the timing control circuit 110 includes digital circuits such as counters, comparators, registers, and logic gates. The timing control circuit 110 is used to receive the synchronization signal SYNC and display data, and the timing control circuit is switched according to the synchronization signal SYNC. The frame, for example, is switched from frame N to frame N+1, and the display enable signal DE is generated according to the synchronous signal SYNC to control the display control circuit 120 to be turned on and off. The display control circuit 120 includes display-related analog control circuits, such as a Gamma Voltage Generator, a Source Driver, a Charge Pump and a Low Dropout Regulator (LDO). )wait. The timing control circuit 110 can provide display data to the source driver of the display control circuit 120 . The display control circuit 120 performs display control to provide display driving signals for driving the touch panel.

Please refer to FIG. 2 , in step S210 , the timing control circuit 110 receives the synchronization signal VSYNC from the mobile industry processor interface MIPI. Next, in step S220 , the timing control circuit 110 sequentially charges a plurality of gate lines at the charging time corresponding to the highest frame rate of the display driving circuit 10 according to the synchronization signal VSYNC. For example, in one embodiment, the display driving circuit 10 has three frame rates: 120Hz, 90Hz or 60Hz. No matter what the current frame rate is, the timing control circuit 110 uses the charging time corresponding to the highest frame rate of 120hz, for example, 3 μs Multiple gate lines are charged sequentially, so the charging time for each gate line is fixed. In step S230 , the timing control circuit 110 disables the display enable signal DE when the charging of the plurality of gate lines ends. In step S240 , the timing control circuit 110 determines whether to disable the display control circuit 120 according to the display enable signal DE, so as to save power consumption of the display control circuit 120 . It must be noted that when the timing control circuit 110 determines to disable or enable the display control circuit 120 according to the display enable signal DE, the timing control circuit 110 provides a control signal (not shown) to the display control The circuit 120 is used to disable or enable the display control circuit 120 . The way of obtaining the end time of charging the gate line, the way of generating the display enable signal DE, and the way of judging whether to disable the display control circuit 120 will be described in detail in FIG. 3A and FIG. 3B .

FIG. 3A is a timing diagram of a display driving circuit at a high frame rate according to an embodiment of the present invention. FIG. 3B is a timing diagram of a display driving circuit at a low frame rate according to an embodiment of the present invention. Please refer to FIG. 3A and FIG. 3B. Specifically, each frame (for example, frame N) in FIG. 3A and FIG. 3B includes a display time TD and a non-display time TN, and the timing control circuit 110 makes the display driving circuit A plurality of gate lines in 10 are charged, while a plurality of gate lines are not charged in the non-display time TN. Furthermore, the display time TD is the time for the display driving circuit 10 to charge the touch panel, and the non-display time TN is the rest time for the display driving circuit 10 to transition to the next frame. In some embodiments, the display time TD may include a vertical sync pulse frame timing (Vertical active line, VACTL), and the non-display time TN may include a vertical sync pulse end timing (Vertical front porch, VFP) and a vertical sync pulse start timing ( Vertical back porch, VBP), not limited thereto.

For example, in frame N−1, when the synchronization signal VSYNC is switched from disabled (low logic level) to enabled (high logic level), the frame N−1 is switched to frame N. After a period of non-display time TN after switching to frame N, the synchronization signal VSYNC changes from enable to disable, and the display enable signal DE changes from disable to enable, the non-display time TN is switched to the display time TD, and The timing control circuit 110 charges the first gate line among the plurality of gate lines in the display drive circuit 10 at the charging time corresponding to the highest frame rate of the display drive circuit 10 in the display time TD, and then charges the second gate line Charge, and so on, until the final gate line is charged.

At the same time, the timing control circuit 110 can count the total charging time of multiple gate lines according to the synchronization signal SYNC and the initial data stored in the timing control circuit 110 to obtain the charging end time of multiple gate lines. The initial data includes each gate The charging time corresponding to the highest frame rate and the resolution of the display data. It must be noted that, in this embodiment, since the multiple gate lines are charged at the charging time corresponding to the highest frame rate, the total charging time of the multiple gate lines is a fixed value. Specifically, the initial data can be stored in the timing control circuit 110 in advance. In one embodiment, the charging time of each gate line at the highest frame rate such as 120 Hz is, for example, 3 μs, and the resolution of the display data includes the number of gate lines in the display driving circuit 10, for example, 2400 gate lines . Therefore, the total charging time of multiple gate lines is the product of the charging time corresponding to each gate line at the highest frame rate and the number of gate lines, that is, 7.2 ms. When the charging of 2400 gate lines ends, that is, when the fixed total charging time of 7.2 ms is counted, the timing control circuit 110 obtains the charging end time of 2400 gate lines, and disables the display of the enable signal at this time DE, so that the display enabling signal DE changes from a high logic level to a low logic level, and at the same time, the frame N switches from the display time TD to the non-display time TN.

In one embodiment, the timing control circuit 110 can provide a control signal to the display control circuit 120 to enable the display control circuit 120 during the display time TD and disable the display control circuit 120 during the non-display time TN. In other words, from the timing of FIG. 3A and FIG. 3B , when the display enable signal DE is at a low logic level, the timing control circuit 110 can judge that the display driving circuit 10 is in the non-display time TN at this time, so it can be disabled. Display control circuit 120 . Then, when the synchronization signal VSYNC is enabled, switch from frame N to frame N+1. The timing of other frames can be deduced as above, and will not be repeated here.

The difference between FIG. 3A and FIG. 3B is that FIG. 3A is a timing diagram of a high frame rate, such as 120 Hz, while FIG. 3B is a timing diagram of a low frame rate, such as 60 Hz. Therefore, the period of the synchronization signal VSYNC in FIG. 3A is twice as long as that of the synchronization signal VSYNC in FIG. 3B . Therefore, compared with FIG. 3A , FIG. 3B has a longer non-display time TN, and the time for which the display control circuit 120 is disabled is correspondingly longer.

In another embodiment, the timing control circuit 110 judges whether to disable the display control according to the low logic level maintenance time of the display enable signal DE, that is, the non-display time TN during which the display enable signal DE remains at a low logic level. circuit 120. Specifically, the timing control circuit 110 can compare the low logic level sustaining time of the display enable signal DE with the first threshold, and the first threshold depends on design requirements, but is not limited thereto. When the low logic level of the display enable signal DE is maintained for a time greater than or equal to the first threshold, the timing control circuit 110 disables the display control circuit 120 . When the low logic level is maintained for less than the first threshold, the timing control circuit 110 cannot help the display control circuit 120 . For example, it can be designed to disable the display control circuit 120 during the non-display time TN at a high frame rate, and disable the display control circuit 120 during the non-display time TN at a low frame rate. Since the analog circuit in the display control circuit 120 needs a stable time to restart, proper threshold design can prevent the display time from being disabled for less than the stable time.

In yet another embodiment, the timing control circuit 110 can use logic gates to make logical judgments on the synchronization signal VSYNC and the display enable signal DE. When both the synchronization signal VSYNC and the display enable signal DE are at a low logic level, the timing control circuit 110 to disable the display control circuit 120 . In other words, there is no situation in FIG. 3A where both the synchronization signal VSYNC and the display enable signal DE are at low logic levels, and the timing control circuit 110 cannot disable the display control circuit 120 . On the other hand, in FIG. 3B , during the non-display time TN of the frame N, the timing control circuit 110 disables the display control circuit 120 because both the synchronization signal VSYNC and the display enable signal DE are at low logic levels.

To sum up, the present invention disables the display enabling signal when the charging of the gate line ends, and judges whether to disable the display control circuit according to the display enabling signal, thereby reducing the power consumption of the analog circuit during the non-display time and improving battery life. In addition, since the present invention uses a fixed charging time in both high frame rate and low frame rate, the MIPI Rate is fixed, which can overcome the problems of antenna adaptation and EMI interference, and does not need to add a reference voltage, which can save production time and cost.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Display drive circuit

110: Timing control circuit

120: display control circuit

SYNC: synchronization signal

DE: Display enable signal

TD: display time

TN: non-display time

S210, S220, S230, S240: steps

FIG. 1 is a block diagram of a display driving circuit according to an embodiment of the invention. FIG. 2 is a flowchart of a display driving method according to an embodiment of the invention. FIG. 3A is a timing diagram of a display driving circuit at a high frame rate according to an embodiment of the present invention. FIG. 3B is a timing diagram of a display driving circuit at a low frame rate according to an embodiment of the present invention.

S210, S220, S230, S240: steps

Claims (17)

A display driving circuit, comprising: a timing control circuit configured to receive a synchronous signal and sequentially charge a plurality of gate lines at a charging time corresponding to the highest frame rate according to the synchronous signal, and charge the gate lines on the plurality of gate lines The display enabling signal is disabled when the charging is completed; and the display control circuit is coupled to the timing control circuit and configured to perform display control to provide a display driving signal, wherein the timing control circuit judges whether the display is enabled according to the display enabling signal The display control circuit is disabled. The display driving circuit according to claim 1, wherein the display driving circuit further receives the synchronization signal and display data through a mobile industry processor interface. The display driving circuit according to claim 1, wherein the timing control circuit further switches frames according to the synchronization signal. The display driving circuit according to claim 1, wherein the timing control circuit counts the total charging time of the plurality of gate lines according to the synchronization signal and the initial data stored in the timing control circuit to obtain the plurality of gate lines The charging end time of each gate line, the initial data includes the charging time corresponding to each gate line at the highest frame rate and the resolution of the display data. The display driving circuit according to claim 1, wherein the display control circuit includes a gamma voltage generator, a source driver, a charge pump and a linear voltage regulator. The display driving circuit according to claim 1, wherein the timing control circuit further judges whether to disable the display control circuit according to the duration of the low logic level of the display enable signal. The display driving circuit according to claim 6, wherein the timing control circuit compares the low logic level maintenance time with a first threshold, and when the low logic level maintenance time is greater than or equal to the first threshold, the The timing control circuit disables the display control circuit, and when the low logic level is maintained for less than the first threshold, the timing control circuit disables the display control circuit. The display driving circuit according to claim 1, wherein the timing control circuit disables the display control circuit when both the synchronization signal and the display enable signal are at a low logic level. The display driving circuit according to claim 1, wherein when the timing control circuit determines to disable the display control circuit, the timing control circuit outputs a control signal to the display control circuit to disable the display control circuit. A display driving method, which is suitable for a display driving circuit, the display driving circuit includes a timing control circuit and a display control circuit, the display driving method includes: receiving a synchronous signal; charging time corresponding to the highest frame rate according to the synchronous signal sequentially charging a plurality of gate lines; disabling the display enable signal when the charging of the plurality of gate lines is completed; and It is judged whether to disable the display control circuit according to the display enabling signal. The display driving method described in claim 10 further includes: receiving the synchronization signal and display data through a mobile industry processor interface. The display driving method according to claim 10 further includes: switching frames according to the synchronization signal. The display driving method according to claim 10, further comprising: counting the total charging time of the plurality of gate lines according to the synchronization signal and the initial data stored in the timing control circuit to obtain the plurality of gates The charging end time of the line, wherein the initial data includes the charging time corresponding to the highest frame rate of each gate line and the resolution of the display data. The display driving method according to claim 10 further includes: judging whether to disable the display control circuit according to the duration of the low logic level of the display enable signal. The display driving method according to claim 14, further comprising: comparing the maintenance time of the low logic level with the first threshold; and judging whether to disable the display control circuit according to the comparison result, wherein when the low logic level When the maintenance time is greater than or equal to the first threshold, the timing control circuit disables the display control circuit; when the low logic level maintenance time is less than the first threshold, the timing control circuit disables the display control circuit. Shows the control circuit. The display driving method as described in claim item 10, further comprising: When both the synchronization signal and the display enable signal are at low logic levels, the display control circuit is disabled. The display driving method according to claim 10 further includes: when it is determined that the display control circuit is to be disabled, outputting a control signal to the display control circuit to disable the display control circuit.

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