CN104581134A - Video signal resolution detection device and method - Google Patents
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Abstract
The embodiment of the invention discloses a video signal resolution detection method which comprises the following steps of inputting a video signal and a row and field synchronization signal; detecting the input signals, performing dejitter filtering after the 1-bit row and field synchronization signal is extended to W bits if the input video signal is a VGA (Video Graphics Array) signal, otherwise directly performing dejitter filtering on the input row and field synchronization signal; detecting the polarity Hp and Vp of the row and field synchronization signal, and simultaneously performing counting to obtain the widths Hcount and Vcount of the row and field synchronization signal; obtaining the current resolution of the video signal by adopting a quadruple time sharing judgment method. The invention further discloses a detection device based on the method. According to the scheme, the quadruple time sharing judgment method is used for a judgment and decision-making machine, so that the shortcomings of an ordinary resolution detection system in terms of accuracy and compatibility are overcome, and meanwhile, the cost of a chip is lowered.
Description
Technical Field
The invention relates to the field of automatic detection of the resolution of an input video signal, in particular to the field of automatic detection of the resolution of an input VGA and YPbPr video signal.
Background
With the increasing abundance of electronic products, more and more devices are provided with VGA (video graphics array) interfaces or YPbPr (color difference component) interfaces, such as PCs, MACs, video cameras, DVDs, and the like. In the fields of multimedia teaching, interactive training, video conference systems, and the like, there is a demand for converting VGA or YPbPr signals output from devices such as computers and DVDs into TV (television video) signals.
Vga (video Graphics array) is a display Graphics array, a standard for computers using analog signals proposed by IBM in 1987. The VGA signal is composed of five types: RGBHV, three primary colors red, green and blue and a line field sync signal, respectively, i.e. with separate line sync signal and field sync signal.
YPbPr is also called a color difference component interface, adopts the EIA-770.2a standard of the American electronic industry Association, and is a progressive scanning color difference output. And the color difference output decomposes the chrominance signal P transmitted by the S-Video into color differences Pr and Pb, thereby avoiding the process of mixing, decoding and separating again two color differences, and also keeping the maximum bandwidth of a chrominance channel, and Y is a luminance signal. YPbPr has no separate sync interface, and its sync is transmitted in a composite in the video signal.
In a VGA/YPbPr-TV video conversion chip, VGA/YPbPr signals with different input resolutions need to be coded into standard CVBS signals for output after being processed by Scaler, frame rate conversion and the like. The VGA/YPbPr signal input resolution is high, and the detection of the resolution determines whether the subsequent various processing is correct, which is the premise of the normal work of the whole conversion chip. Currently, the resolution detection is to perform sampling counting on horizontal synchronization signals and vertical synchronization signals of all resolutions to obtain information of input line field synchronization signals, including line/field synchronization pulse time, duration active level time and scanning time, and to establish a resolution information table, and to compare the input resolution information with values stored in the resolution information table when detecting the resolution, so as to obtain the currently input resolution. The existing method for detecting the resolution ratio has the following defects:
only VGA signals input by a separated line field which accords with VESA standards can be detected, YPbPr and other composite line field input signals cannot be detected, and VGA/YPbPr input resolution ratio simultaneous detection is not supported.
Due to the difference of video output devices, the resolution information table established only by the line/field synchronization pulse time, the duration active level time and the scanning time cannot accurately distinguish the resolutions with the similar line frequency and field frequency, which may reduce the accuracy of detection. Meanwhile, for the same resolution output by different devices, the line frequency and the field frequency are also different to a certain extent, and if the line/field synchronous pulse time, the continuous effective level time and the scanning time in the resolution information table are used for judgment, the resolution is inevitably judged incorrectly, so that the detection compatibility is poor.
The conventional resolution information table is to store the line synchronization time, the active level time and the total scan time, and each resolution corresponds to a set of tables, which requires a large amount of memory space and comparison logic.
Disclosure of Invention
In view of the above, there is a need to provide a method and an apparatus for detecting the input resolutions of VGA and YPbPr simultaneously, which have better accuracy and compatibility, and do not consume too much resources.
The embodiment of the invention provides a method for detecting the resolution of a video signal, which comprises the following steps:
step S100: inputting a video signal and a line-field synchronizing signal;
step S101: judging whether the input signal is a VGA signal or a YPbPr signal; if the input video signal is a VGA signal, the step S102 is carried out, otherwise, the step S103 is carried out;
step S102: expanding 1 bit line field synchronous signals into W bit multi-bit signals, wherein W is a positive integer;
step S103: carrying out de-jitter filtering processing on the input synchronous signal;
step S104: detecting polarities Hp and Vp of the line field synchronizing signals according to the line field synchronizing signals subjected to the de-jitter filtering processing, and counting to obtain widths Hcount and Vcount of the line field synchronizing signals;
step S105: and obtaining the resolution of the current video signal by adopting a quadruple time-sharing judgment method.
The step S104 further includes the steps of:
step S400: inputting a line field synchronizing signal after de-jitter filtering processing;
step S401: configuring a cutting level value slicr _ lv through a register;
step S402: subtracting the slicing level slice _ lv from the field synchronizing signal to obtain a sliced field synchronizing signal Vt;
step S403: subtracting the cutting level slice _ lv from the line synchronizing signal to obtain a reconstructed line synchronizing signal Hout after cutting;
step S404: the cut field synchronizing signal Vt is used for obtaining a reconstructed field synchronizing signal Vout through an integrating circuit;
step S405: judging the polarities of the reconstructed line-field synchronizing signals Hout and Vout, and outputting Hp and Vp;
step S406: counting to obtain the number Hcount of points in a line;
step S407: counting to obtain the number of rows Vcount in one field.
The method further comprises a step between the step S400 and the step S401: and the input signal is output after passing through a low-pass filter.
The step S401 may also be replaced by the following steps:
finding out the minimum value of the N rows of signals;
and adding the minimum value to a set bias voltage Reg _ b to obtain a cutting level value slice _ lV.
The step S105 further includes the steps of:
step S501: and (3) the currently detected four resolution information: comparing the line synchronization width Hcount, the field synchronization width Vcount, the line synchronization polarity Hp and Vp with corresponding parameters in a resolution information table one by one, if four comparison difference values with a resolution are all within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
the resolution information table stores four values of line-field polarity, line synchronization width and field synchronization width of each VGA signal and YPbPr signal;
if the matching number is 1, the matched resolution is the resolution of the input video signal;
if the matching number is greater than 1, the process goes to step S502; if the matching number is zero, the process proceeds to step S503;
step S502: after reducing the error tolerance value according to a set step length, repeating the step S501;
step S503: two resolution information of current detection: comparing the line synchronization width Hcount and the field synchronization width Vcount with corresponding parameters in a resolution information table one by one, if four comparison difference values with one resolution are within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
when the matching number is 1, the detection is successful; if the matching number is greater than 1, go to step S504; if the matching number is zero, the detection fails;
step S504: the error tolerance is decreased by a set step size, and step S503 is repeated.
The step sizes set in step S502 and step S504 are equal.
An apparatus for detecting resolution of a video signal, the apparatus comprising: the device comprises an input source detection unit, a line field bit expansion unit, a de-jitter filtering unit, a line field polarity and width detection unit and a quadruple time-sharing judgment unit; wherein,
the input source detection unit is used for detecting the input signal and judging whether the input signal is a VGA signal or a YPbPr signal;
the line field bit extension unit is used for extending a line synchronization signal and a field synchronization signal of one bit to W bits;
the de-jitter filtering processing unit comprises a filter for removing jitter noise in the line-field synchronizing signal;
the line field polarity and width detection unit is used for detecting the polarities Hp and Vp of the line field synchronizing signals and obtaining the widths Hcount and Vcount of the line field synchronizing signals through counting;
and the quadruple time-sharing judging unit is used for obtaining the resolution of the current video signal by adopting a quadruple time-sharing judging method according to the line and field polarities Hp and Vp, the line synchronization width Hcount and the field synchronization width Vcount obtained by detection and counting.
The line field polarity and width detection unit further includes:
the cutting level generating unit is used for configuring a cutting level value slicr _ lv through a register;
the field synchronization cutting unit is used for subtracting the cutting level slice _ lv from the field synchronization signal to obtain a cut field synchronization signal Vt;
the line synchronization reconstruction unit is used for subtracting the cutting level slice _ lv from the line synchronization signal to obtain a reconstructed line synchronization signal Hout after cutting;
the field synchronization reconstruction unit is used for obtaining a reconstructed field synchronization signal Vout from the cut field synchronization signal Vt through an integrating circuit;
the line synchronization counting unit is used for counting to obtain the number Hcount of points in a line through a counter;
the field synchronous counting unit is used for counting through a counter to obtain the number of lines Vcount in a field;
and the line field polarity judging unit is used for judging the polarities of the reconstructed line field synchronous signals Hout and Vout and outputting Hp and Vp.
The slice level generation unit may be further replaced with:
a slice level calculation unit comprising:
the minimum unit is used for finding out the minimum value of the N rows of signals;
and the superposition unit is used for adding the minimum value and a set bias voltage Reg _ b to obtain a cutting level value slice _ lv.
The line-field polarity and width detection unit further comprises two low-pass filters for performing low-pass filtering on the input signal and inputting the input signal.
The quadruple time-sharing judgment unit further comprises:
the first judging unit comprises a first comparing unit, a resolution information table and a first control unit, wherein:
the comparison unit one is used for comparing the currently detected four resolution information: comparing the line synchronization width Hcount, the field synchronization width Vcount, the line synchronization polarity Hp and Vp with corresponding parameters in a resolution information table one by one, if four comparison difference values with a resolution are all within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
the resolution information table is a storage space and is used for storing four values of line-field polarity, line synchronization width and field synchronization width of each VGA signal and YPbPr signal;
the first control unit is used for judging according to the matching number obtained by the first comparison unit, if the matching number is 1, the detection is successful, and the resolution obtained by the detection is considered to be the resolution of the input video signal; if the matching number is larger than 1, starting a first tolerance reducing unit; if the matching number is zero, the second judgment unit is started.
The first tolerance reducing unit is used for reducing the error tolerance value according to a set step length and then inputting the reduced error tolerance value into the first judging unit;
the second judgment unit comprises a second comparison unit, a resolution information table and a second control unit, wherein:
the second comparing unit is configured to compare the currently detected two resolution information: comparing the line synchronization width Hcount and the field synchronization width Vcount with corresponding parameters in a resolution information table one by one, if four comparison difference values with one resolution are within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
the resolution information table is the resolution information table in the first judging unit;
the second control unit is used for judging according to the matching number obtained by the second comparison unit, and if the matching number is 1, the detection is successful; if the matching number is 0, the detection fails; if the matching number is larger than 1, entering a second tolerance reduction unit;
and the second tolerance reducing unit is used for reducing the error tolerance according to a set step length and inputting the reduced error tolerance into the second judging unit.
The first margin reduction unit and the second margin reduction unit are the same unit.
The detection device and the method in the embodiment of the invention can simultaneously detect the resolution of VGA and YPbPr input, and can overcome the defects of the conventional resolution detection system in accuracy and compatibility by using the quadruple time-sharing judgment method and greatly reduce the cost of a chip on the premise of reducing the horizontal synchronous pulse time, the horizontal continuous effective level time, the vertical synchronous pulse time and the vertical continuous effective level time in the content of the conventional resolution information table and on the premise of reducing the combined judgment conditions of line scanning time, field scanning time, line synchronous polarity and field synchronous polarity.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a general flow chart of a method for automatically detecting resolution according to an embodiment of the present invention;
FIG. 2 is a flow chart of an embodiment of a line field polarity and width calculation unit according to the present invention;
FIG. 3 is a block diagram of a resolution detection apparatus according to an embodiment of the present invention;
FIG. 4 is a block diagram of an exemplary implementation of a line field polarity and width detection unit according to an embodiment of the present invention;
FIG. 5 is a block diagram of another exemplary implementation of a horizontal field polarity and width detection unit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a flow chart of a method for detecting the resolution of a video signal, which includes the following steps:
step S100: inputting a video signal and a line-field synchronizing signal;
step S101: detecting an input signal, and judging whether the input signal is a VGA signal or a YPbPr signal; if the input video signal is a VGA signal, the step S102 is carried out, otherwise, the step S103 is carried out;
step S102: expanding the 1-bit line field synchronous signals into W-bit multi-bit signals; w is a positive integer, and expansion enables the bit number of the line-field synchronous signal to be consistent with the bit number of other signals in the system, such as cutting level slice _ lv and the like, so that subsequent processing of noise reduction, jitter removal and the like is facilitated;
step S103: carrying out de-jitter filtering processing on the input synchronous signal; if the input is a VGA signal, the sync signal is the line-field sync signal expanded in step S102, and if the input is a YPbPr signal, the sync signal includes the line-field sync signal and is all multiplexed on the Y signal, i.e., the multiplexed sync signal.
The de-jitter filtering is generally completed by mean filtering or IIR filtering and the like; after the de-jitter filtering processing, more ideal line synchronizing signal Hin1 and field synchronizing signal Vin1 are obtained.
Step S104: detecting polarities Hp and Vp of the line field synchronizing signals according to the line field synchronizing signals subjected to the de-jitter filtering processing, and meanwhile, obtaining widths Hcount and Vcount of the line field synchronizing signals through counting;
step S105: and obtaining the resolution of the current video signal by adopting a quadruple time-sharing judgment method according to the line and field polarities Hp and Vp obtained by detection and counting and the line synchronization width Hcount and the field synchronization width Vcount obtained by counting.
The implementation method of step S101 may determine whether the input signal is a YPbPr signal by detecting whether the composite synchronization signal input end has normal composite video signal input data, or else, it is a VGA signal;
the implementation method of step S101 may further detect whether the input ends of the horizontal synchronization signal and the field synchronization signal have normal horizontal synchronization signals or normal field synchronization signals, if so, the input ends are VGA signals, otherwise, the input ends are YPbPr signals;
in step S101, whether there is a corresponding input signal at both the line-field synchronizing signal input end and the composite synchronizing signal input end can be detected at the same time, and since the input signals cannot be two signals at the same time, a unique input signal detection result can be obtained.
The step S104 may further include the following steps, as shown in fig. 2:
step S400: inputting a line field synchronizing signal after de-jitter filtering processing;
step S401: configuring a cutting level value slicr _ lv through a register;
step S402: subtracting the slicing level slice _ lv from the field synchronizing signal to obtain a sliced field synchronizing signal Vt;
step S403: subtracting the cutting level slice _ lv from the line synchronizing signal to obtain a reconstructed line synchronizing signal Hout after cutting;
step S404: the cut field synchronizing signal Vt is used for obtaining a reconstructed field synchronizing signal Vout through an integrating circuit;
step S405: judging the polarities of the reconstructed line-field synchronizing signals Hout and Vout, and outputting Hp and Vp;
step S406: counting to obtain the number Hcount of points in a line;
step S407: counting to obtain the number of rows Vcount in one field.
It should be noted that, in addition to being configurable by a register, the slicing level value slicr _ lv in step S401 may also be obtained by the following steps:
finding out the minimum value of the N rows of signals;
and adding the minimum value and a set bias voltage Reg _ b to obtain a cutting level value slice _ lv.
The level value calculated by the method is more consistent with the currently input video signal, so that an ideal synchronous signal can be obtained by cutting more ready.
The step S400 and the step S401 may further include a step: the input signal is output after passing through a low-pass filter;
the method for determining the quadruple time division in the step S105 includes the following steps:
step S501: in a judgment period, the information of four resolution ratios detected currently is: comparing the line synchronization width Hcount, the field synchronization width Vcount, the line synchronization polarity Hp and Vp with corresponding parameters in a resolution information table one by one, if four comparison difference values with a resolution are all within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
judging the obtained matching number, if the matching number is unique, the detection is successful, and the resolution obtained by the detection is considered to be the resolution of the input video signal;
if the matching number is greater than 1, the process goes to step S502; if the matching number is zero, the process proceeds to step S503.
The resolution information table includes four values of the line-field polarity, the line sync width, and the field sync width of each of the VGA signals and the YPbPr signals detectable by the present invention, which are different according to the sampling frequency, and which can be configured by a register, or written by a control system.
Step S502: after the error tolerance is decreased by a set step size, the detection in step S501 is repeated.
Step S503: and (4) reducing the parameters judged in the step (S501) into two parameters including the line synchronization width Hcount and the field synchronization width Vcount, and repeating the judgment in the step (S501) to obtain the number of the matched resolutions. Namely:
two resolution information of current detection: comparing the horizontal synchronizing width Hcount and the field synchronizing width Vcount with corresponding parameters in a resolution information table one by one, and if the error is within a set error tolerance value, considering the error to be the same;
if the two parameters are the same, the matching with the resolution ratio is considered to be successful; when the matching number is 1, the current matched resolution is considered as the resolution of the input video signal; if the matching number is greater than 1, go to step S504; if the matching number is zero, the detection fails, and the currently input video signal is not considered to be in the range listed in the resolution information table.
Step S504: after the error tolerance is decreased by a set step size, the determination of step S503 is repeated.
It should be noted that the step sizes in steps S502 and S504 may be the same, or different step sizes may be adopted.
Generally, after the steps S501 and S502, the resolution of the current video signal can be uniquely determined, and the steps S503 and S504 can determine some resolutions deviating from the video standard, so that the resolution output by different devices can be maximally compatible due to the relaxed determination condition.
Based on the above method for detecting the resolution of the video signal, the present invention further provides a device for detecting the resolution of the video signal, as shown in fig. 3, which is a specific implementation structure block diagram of the device, and the device includes an input source detecting unit 101, a line-field bit expanding unit 102, a de-jitter filtering unit 103, a line-field polarity and width detecting unit 104, and a quadruple time-sharing judging unit 105; the input signals are a horizontal synchronization signal Hin, a field synchronization signal Vin and a composite synchronization signal Yin, and the input horizontal synchronization signal Hin and the field synchronization signal Vin are input to the input source detection unit 101 and the horizontal and field bit extension unit 102; the composite synchronization signal Yin is respectively input to the input source detection unit 101 and the debounce filter unit 103, the line field bit expansion unit 102 outputs the expanded line field synchronization signal to the debounce filter unit 103, the input source detection unit 101 outputs a detection result signal to the line field polarity and width detection unit 104 and the quadruple time-sharing judgment unit 105, the debounce filter unit 103 outputs the filtered line field synchronization signal and the composite synchronization signal to the line field polarity and width detection unit 104, and the obtained line field polarity values Hp and Vp, the obtained line width values Hcount and the obtained field width values Vcount are input to the quadruple time-sharing judgment unit 105, so as to obtain the resolution type of the final VGA signal or the YPbPr signal.
The input source detecting unit 101 determines whether the input signal is a YPbPr signal by detecting whether the composite synchronization signal input end has normal composite video signal input data, and otherwise, determines that the input signal is a VGA signal;
the input source detecting unit 101 may further detect whether the input end of the horizontal synchronization signal and the field synchronization signal has a normal horizontal synchronization signal or a normal field synchronization signal, if so, the input end of the horizontal synchronization signal and the field synchronization signal is a VGA signal, otherwise, the input end of the horizontal synchronization signal and the field synchronization signal is a YPbPr signal;
the input source detecting unit 101 may further detect whether there is a corresponding input signal at both the line-field synchronizing signal input end and the composite synchronizing signal input end.
The line field bit extension unit 102 extends the line synchronization signal and the field synchronization signal of one bit to W bits, so as to facilitate processing such as filtering and cutting in the later period, and obtain a more ideal and accurate line field synchronization signal, thereby more accurately detecting the resolution of the input video signal.
The de-jitter filtering unit 103 is used to remove jitter noise in the horizontal-field synchronization signal, and may be an average filter, an IIR filter, or other filters with equivalent filtering effects. After passing through the de-jitter filtering unit 103, a more ideal horizontal synchronizing signal Hin1, field synchronizing signal Vin1 and composite synchronizing signal Yin1 are obtained.
Fig. 4 is a block diagram of a specific implementation structure of the line-field polarity and width detection unit 104, which includes a slice level generation unit 401, a field sync slice unit 402, a line sync reconstruction unit 403, a field sync reconstruction unit 404, a line sync counting unit 405, a field sync counting unit 406, and a line-field polarity determination unit 407; the horizontal synchronizing signal Hin1, the composite synchronizing signal Yin1 and the offset level Reg _ b processed by the units are all input to the slice level production unit 401 to obtain a slice level slice _ lv, the slice level slice _ lv is respectively input to the field synchronization cutting unit 402 and the horizontal synchronization reconstruction unit 403, the field synchronizing signal Vin1 and the composite synchronizing signal Yin1 processed by the units are both input to the field synchronization cutting unit 402, the field synchronization cutting unit 402 outputs a sliced field synchronizing signal Vt to the field synchronization reconstruction unit 404, the reconstructed field synchronizing signal Vout is respectively input to the field synchronization counting unit 406 and the line field polarity judgment unit 407, and the number of lines Vcount and the field polarity Vp in each field are obtained; the line synchronization reconstruction unit 403 outputs the regenerated line synchronization signal Hout to the line synchronization counting unit 405 and the line field polarity determination unit 407, so as to obtain the number of points Hount and the line polarity Hp in each line.
The cutting level generating unit 401 includes a register configuration unit, and configures a cutting level value slice _ lv by configuring a register value;
in another embodiment, the slice level generating unit 401 includes N rows of detecting units, an adder, and a register configuration unit, and first obtains the minimum value in N rows of data through the detecting units, and configures a bias voltage Reg _ b through the configuration register, where the minimum value in N rows of data and the bias voltage Reg _ b are input to the adder to be added to obtain the slice level value slice _ lv, where N is a natural number greater than or equal to 1.
The line synchronization reconstruction unit 403 includes a subtractor, and the input line synchronization signal Hin1 and the slice level slice _ lv are subtracted in the subtractor to obtain a reconstructed ideal line synchronization signal Hout, which is output to the polarity determination unit and the line synchronization counting unit.
The field sync slicing unit 402 comprises a subtractor, and the input field sync signal Vin1 and the slicing level slice _ lv are subtracted in the subtractor to obtain a field sync signal Vt, which is input to the field sync reconstruction unit 404.
The field synchronization reconstruction unit 404 includes a field synchronization integration unit and a comparator, the field synchronization signal, especially the field synchronization signal in the composite line field synchronization signal, needs to be obtained by an integration circuit, the integration circuit uses accumulative calculation, only the actual field synchronization signal can be integrated to generate a new field synchronization signal, and the signals of line synchronization or interference and the like are filtered after being processed by the integration circuit, so as to enhance the stability of reconstructing the generated field synchronization signal.
The line synchronization count unit 405 includes a counter that counts the number of points in a line.
The field sync counting unit 406 includes a counter for counting the number of lines in one field.
The line-field polarity determining unit 407 determines whether the line synchronization signal start point and the field synchronization signal start point are rising pulses or falling pulses, and distinguishes between signals 0 and 1.
In another embodiment, the line-field polarity and width detection unit 104 further includes two low pass filters 408 and 409; as shown in fig. 5. When the input video signal is in VGA format, the line-field signal is low-pass filtered by two low-pass filters 408 and 409 and then input to the slice level generating unit 401, the line synchronous reconstruction unit 403 and the field synchronous slice unit 402. After the low-pass filter is added, the synchronous signals in VGA format and the synchronous signals in the composite signals can be better filtered out.
The quadruple time-sharing determination unit 105 includes:
the first judging unit comprises a first comparing unit, a resolution information table and a first control unit, wherein:
the comparison unit I is used for comparing the currently detected four resolution information line synchronization widths Hcount, field synchronization width Vcount, line synchronization polarities Hp and Vp with corresponding parameters in a resolution information table one by one, if four comparison difference values with one resolution are all within an error tolerance value, the four comparison difference values are matched with the resolution, and the matching number is added by 1; otherwise, the matching numbers are not matched, and the matching numbers are kept unchanged;
the resolution information table is a storage space for storing four values of the line-field polarity, the line synchronization width and the field synchronization width of each of the VGA signals and the YPbPr signals detectable by the present invention, which are different according to the sampling frequency, and can be configured by a register or written into the storage space by a control system.
The first control unit is used for judging according to the matching number obtained by the first comparison unit, if the matching number is 1, the detection is successful, and the resolution obtained by the detection is considered to be the resolution of the input video signal; if the matching number is larger than 1, starting a first tolerance reducing unit; if the matching number is zero, the second judgment unit is started.
The first tolerance reducing unit is used for reducing the error tolerance value according to a set step length and then inputting the error tolerance value into the first judging unit again for comparison;
the second judgment unit comprises a second comparison unit, a resolution information table and a second control unit, wherein:
the second comparing unit is configured to compare the currently detected two resolution information: comparing the line synchronization width Hcount and the field synchronization width Vcount with corresponding parameters in a resolution information table one by one, if four comparison difference values with one resolution are within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
the resolution information table is the resolution information table in the first judging unit;
the second control unit is used for judging according to the matching number obtained by the second comparison unit, and if the matching number is 1, the detection is successful; if the matching number is 0, the detection fails; if the matching number is larger than 1, entering a second tolerance reduction unit;
and the second margin reducing unit is used for reducing the error margin value according to a set step length and then inputting the error margin value into the second judging unit again for judgment.
The first margin reduction unit and the second margin reduction unit may be the same unit or different units.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above detailed description of the embodiments of the present invention, and the detailed description of the embodiments of the present invention used herein, is merely intended to facilitate the understanding of the methods and apparatuses of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (12)
1. A method for detecting resolution of a video signal, the method comprising the steps of:
step S100: inputting a video signal and a line-field synchronizing signal;
step S101: judging whether the input signal is a VGA signal or a YPbPr signal; if the input video signal is a VGA signal, the step S102 is carried out, otherwise, the step S103 is carried out;
step S102: expanding 1 bit line field synchronous signals into W bit multi-bit signals, wherein W is a positive integer;
step S103: carrying out de-jitter filtering processing on the input synchronous signal;
step S104: detecting polarities Hp and Vp of the line field synchronizing signals according to the line field synchronizing signals subjected to the de-jitter filtering processing, and counting to obtain widths Hcount and Vcount of the line field synchronizing signals;
step S105: and obtaining the resolution of the current video signal by adopting a quadruple time-sharing judgment method.
2. The detection method according to claim 1, wherein the step S104 further comprises the steps of:
step S400: inputting a line field synchronizing signal after de-jitter filtering processing;
step S401: configuring a cutting level value slicr _ lv through a register;
step S402: subtracting the slicing level slice _ lv from the field synchronizing signal to obtain a sliced field synchronizing signal Vt;
step S403: subtracting the cutting level slice _ lv from the line synchronizing signal to obtain a reconstructed line synchronizing signal Hout after cutting;
step S404: the cut field synchronizing signal Vt is used for obtaining a reconstructed field synchronizing signal Vout through an integrating circuit;
step S405: judging the polarities of the reconstructed line-field synchronizing signals Hout and Vout, and outputting Hp and Vp;
step S406: counting to obtain the number Hcount of points in a line;
step S407: counting to obtain the number of rows Vcount in one field.
3. The detection method according to claim 2, further comprising a step between step S400 and step S401: and the input signal is output after passing through a low-pass filter.
4. The detection method according to claim 2, wherein the step S401 is further replaced by the steps of:
finding out the minimum value of the N rows of signals;
and adding the minimum value and a set bias voltage Reg _ b to obtain a cutting level value slice _ lv.
5. The detection method according to claim 1, wherein the step S105 further comprises the steps of:
step S501: and (3) the currently detected four resolution information: comparing the line synchronization width Hcount, the field synchronization width Vcount, the line synchronization polarity Hp and Vp with corresponding parameters in a resolution information table one by one, if four comparison difference values with a resolution are all within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
the resolution information table stores four values of line-field polarity, line synchronization width and field synchronization width of each VGA signal and YPbPr signal;
if the matching number is 1, the matched resolution is the resolution of the input video signal;
if the matching number is greater than 1, the process goes to step S502; if the matching number is zero, the process proceeds to step S503;
step S502: after reducing the error tolerance value according to a set step length, repeating the step S501;
step S503: two resolution information of current detection: comparing the line synchronization width Hcount and the field synchronization width Vcount with corresponding parameters in a resolution information table one by one, if four comparison difference values with one resolution are within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
when the matching number is 1, the detection is successful; if the matching number is greater than 1, go to step S504; if the matching number is zero, the detection fails;
step S504: the error tolerance is decreased by a set step size, and step S503 is repeated.
6. The method according to claim 5, wherein the step sizes set in step S502 and step S504 are equal.
7. A video signal resolution detection apparatus according to the detection method of claim 1, the apparatus comprising: the device comprises an input source detection unit, a line field bit expansion unit, a de-jitter filtering unit, a line field polarity and width detection unit and a quadruple time-sharing judgment unit; wherein,
the input source detection unit is used for detecting the input signal and judging whether the input signal is a VGA signal or a YPbPr signal;
the line field bit extension unit is used for extending a line synchronization signal and a field synchronization signal of one bit to W bits;
the de-jitter filtering processing unit comprises a filter for removing jitter noise in the line-field synchronizing signal;
the line field polarity and width detection unit is used for detecting the polarities Hp and Vp of the line field synchronizing signals and obtaining the widths Hcount and Vcount of the line field synchronizing signals through counting;
and the quadruple time-sharing judging unit is used for obtaining the resolution of the current video signal by adopting a quadruple time-sharing judging method according to the line and field polarities Hp and Vp, the line synchronization width Hcount and the field synchronization width Vcount obtained by detection and counting.
8. The detecting device according to claim 7, wherein the line-field polarity and width detecting unit further comprises:
the cutting level generating unit is used for configuring a cutting level value slicr _ lv through a register;
the field synchronization cutting unit is used for subtracting the cutting level slice _ lv from the field synchronization signal to obtain a cut field synchronization signal Vt;
the line synchronization reconstruction unit is used for subtracting the cutting level slice _ lv from the line synchronization signal to obtain a reconstructed line synchronization signal Hout after cutting;
the field synchronization reconstruction unit is used for obtaining a reconstructed field synchronization signal Vout from the cut field synchronization signal Vt through an integrating circuit;
the line synchronization counting unit is used for counting to obtain the number Hcount of points in a line through a counter;
the field synchronous counting unit is used for counting through a counter to obtain the number of lines Vcount in a field;
and the line field polarity judging unit is used for judging the polarities of the reconstructed line field synchronous signals Hout and Vout and outputting Hp and Vp.
9. The detection apparatus according to claim 7, wherein the slice level generation unit is further replaceable with:
a slice level calculation unit comprising:
the minimum unit is used for finding out the minimum value of the N rows of signals;
and the superposition unit is used for adding the minimum value and a set bias voltage Reg _ b to obtain a cutting level value slice _ lv.
10. The detection device as claimed in claim 8, wherein the line-field polarity and width detection unit further comprises two low pass filters for performing low pass filtering on the input signal and inputting the low pass filtered input signal.
11. The detecting device according to claim 7, wherein the quartering time-sharing judging unit further includes:
the first judging unit comprises a first comparing unit, a resolution information table and a first control unit, wherein:
the comparison unit one is used for comparing the currently detected four resolution information: comparing the line synchronization width Hcount, the field synchronization width Vcount, the line synchronization polarity Hp and Vp with corresponding parameters in a resolution information table one by one, if four comparison difference values with a resolution are all within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
the resolution information table is a storage space and is used for storing four values of line-field polarity, line synchronization width and field synchronization width of each VGA signal and YPbPr signal;
the first control unit is used for judging according to the matching number obtained by the first comparison unit, if the matching number is 1, the detection is successful, and the resolution obtained by the detection is considered to be the resolution of the input video signal; if the matching number is larger than 1, starting a first tolerance reducing unit; if the matching number is zero, the second judgment unit is started.
The first tolerance reducing unit is used for reducing the error tolerance value according to a set step length and then inputting the reduced error tolerance value into the first judging unit;
the second judgment unit comprises a second comparison unit, a resolution information table and a second control unit, wherein:
the second comparing unit is configured to compare the currently detected two resolution information: comparing the line synchronization width Hcount and the field synchronization width Vcount with corresponding parameters in a resolution information table one by one, if four comparison difference values with one resolution are within an error tolerance value, matching the resolution, and adding 1 to the matching number; otherwise, the signals are not matched;
the resolution information table is the resolution information table in the first judging unit;
the second control unit is used for judging according to the matching number obtained by the second comparison unit, and if the matching number is 1, the detection is successful; if the matching number is 0, the detection fails; if the matching number is larger than 1, entering a second tolerance reduction unit;
and the second tolerance reducing unit is used for reducing the error tolerance according to a set step length and inputting the reduced error tolerance into the second judging unit.
12. The detecting device according to claim 11, wherein the first margin narrowing unit and the second margin narrowing unit are the same unit.
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Address after: 518057 4 room 406, phase 1, two software park, Nanshan District science and technology, Guangdong, Shenzhen Patentee after: Shenzhen Shenyang electronic Limited by Share Ltd Address before: 518057 4 room 406, phase 1, two software park, Nanshan District science and technology, Guangdong, Shenzhen Patentee before: Aike Chuangxin Microelectronic Co., Ltd. |
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Denomination of invention: Video signal resolution detection device and method Effective date of registration: 20180625 Granted publication date: 20170818 Pledgee: Shenzhen high tech investment and financing Company limited by guarantee Pledgor: Shenzhen Shenyang electronic Limited by Share Ltd Registration number: 2018990000484 |
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