CN1925593A - Allowable data signal processing device for interactive digital video system interface - Google Patents
Allowable data signal processing device for interactive digital video system interface Download PDFInfo
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- CN1925593A CN1925593A CN 200510047108 CN200510047108A CN1925593A CN 1925593 A CN1925593 A CN 1925593A CN 200510047108 CN200510047108 CN 200510047108 CN 200510047108 A CN200510047108 A CN 200510047108A CN 1925593 A CN1925593 A CN 1925593A
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Abstract
This invention relates to one interact digital visual frequency interface data signal process device, which comprises the following parts: receiving vertical and level synchronous signals and testing work status LPF through above digital visual system DVI interface; turning the signals and keeping original output cathode correction part according to LPF output work status information; getting cathode level and vertical signals and permitting data DE signals relate DE signals to generate level and vertical synchronous signals.
Description
Affiliated technical field
The present invention relates to a kind of Digital Video Interactive DVI interface, particularly relate to a kind of permission data DE (Data Enable) signal processing apparatus of Digital Video Interactive DVI interface.
Background technology
Recently along with the style of image display is advanced,, Digital Video Interactive DVI interface function is set in digital television usually in order to show images with high image quality.
The digital television receiver that possesses above-mentioned DVI interface function receives DE signal and level and vertical synchronizing signal, also has rgb signal, and after these signal processing, embodies image through the video scaler integrated circuit (IC).Particularly, above-mentioned DE signal is, the signal of difference actual displayed time and blanking time, and above-mentioned digital television receiver is the starting point that benchmark is provided with level and vertical image with the DE signal, to form the image that does not rock.
Above-mentioned DE signal and vertical and horizontal-drive signal are described as follows with reference to Fig. 1 and Fig. 2:
With reference to Fig. 1, the DE signal is the signal that keeps low level state in 800 horizontal clock pulse during 160 horizontal clock pulse, and horizontal-drive signal is positioned on the assigned position of DE signal.
With reference to Fig. 2, the DE signal does not produce and produces in the image demonstration time period in the vertical blanking time section.
As shown in Figures 1 and 2, the DE signal is interval consistent just with picture signal.Therefore, when embodying image, form the image that has no to rock and not only become possibility by the DE signal, and, can be complete expression between the actual effect image area that has no to change.
, in the scaler in use,, therefore can not utilize the DE signal to show best image at present because some scaler can not be handled the DE signal.
Promptly, can not obtain the information in real image interval by the DE signal, image display can only begin datum mark with the image that horizontal-drive signal is sought horizontal direction, if produce the horizontal-drive signal of the shake of the clock that the DVI specification guarantees, then occurs showing the dither image phenomenon sometimes.
And, with opposite between the actual effect image area in above-mentioned DE signal display image interval, above-mentioned level and vertical synchronizing signal can not embody the specifying information such as begin between the actual effect image area, because set-top box, DVD player, also have multiple signal sources such as home computer, begin display image at diverse location separately, therefore reduce the degree of reliability of product.
And, because the level and the vertical synchronizing signal of each PC specification of appointment are different with the position in display image interval among specifications such as 480i, 480P, 720P, 1080i or the VESA of VESA, if so do not reset the starting point of image respectively by individual form certainly, image is not then at the picture center position, and its position is just becoming not.
For overcoming these shortcomings, also, be necessary to utilize above-mentioned DE signal that signal is processed for corresponding off-gauge signal input flexibly.
Summary of the invention
The purpose of this invention is to provide a kind of DE of utilization signal, regeneration level and vertical synchronizing signal, thereby overcome because of level and the unstable flating that causes of vertical synchronizing signal, to not handling the scaler of DE signal, also can make image be positioned at the DE signal processing apparatus of DVI interface of the center position of picture.
In order to achieve the above object, the DE signalling of DVI interface of the present invention is to be made of following part: by above-mentioned DVI interface, receive the vertical low pass filter LPF that reaches horizontal-drive signal and detect operating state; According to the work state information of low pass filter LPF output, upset is vertical to reach horizontal-drive signal or the polarity correction portion of the output of keeping intact; Obtain level and vertical synchronizing signal and DE signal that polarity has been corrected, the level and the vertical synchronizing signal reproducing unit of level that regeneration can corresponding DE signal and vertical synchronizing signal and output.
Above-mentioned horizontal-drive signal reproducing unit is to be made of following part: the 1st gate circuit portion that produces the 1st signal of the above-mentioned permission data-signal starting point of expression; Produce the 2nd gate circuit portion of the 2nd signal of the expression horizontal-drive signal starting point of above-mentioned polarity correction portion output; To clock pulse count, the counter that resets according to the 2nd signal; According to the 1st signal, the count value of above-mentioned counter is carried out the buffer of buffer memory; The count value of cache size and above-mentioned counter is carried out subtraction, and the subtraction portion of result's output; The 1st comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and rising; The 2nd comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and decline; According to the above-mentioned the 1st and the 5th gate circuit portion that exports repeatedly of the output of the 2nd comparator.
Above-mentioned vertical synchronizing signal reproducing unit is to be made of following part: the 3rd gate circuit portion that produces the 3rd signal of the above-mentioned permission data-signal starting point of expression; Produce the 4th gate circuit portion of the 4th signal of the expression vertical synchronizing signal starting point of above-mentioned polarity correction portion output; With double horizontal-drive signal counting, and the counter that resets according to the 4th signal; According to above-mentioned the 3rd signal, the count value of above-mentioned counter is carried out the buffer of buffer memory; The count value of the value sum counter of above-mentioned buffer is carried out subtraction, and output subtracts the subtraction portion of calculating the result; The 3rd comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and rising; The 4th comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and decline; The 6th gate circuit portion that exports repeatedly according to the output of the 3rd and the 4th comparator.
The invention has the beneficial effects as follows:
Utilize DE signal regeneration level and vertical synchronizing signal, thereby reduce, also can make image be positioned at the middle position of picture the scaler that can not import the DE signal because of level and the unstable flating that causes of vertical synchronizing signal.
Description of drawings
Fig. 1 and Fig. 2 are the oscillograms of DE.
Fig. 3 is an enforcement illustration of forming the DE signal processing apparatus of DVI interface of the present invention.
Fig. 4 is the composition diagram of the horizontal-drive signal reproducing unit of presentation graphs 3.
Fig. 5 is the composition diagram of the vertical synchronizing signal reproducing unit of presentation graphs 3.Among the figure:
100: level and vertical synchronizing signal reproducing unit 102: polarity correction portion
104:LPF AND1-AND4: 1-the 4th and door
D1-D6: 1-the 6th trigger CNT1, CNT2: the 1st and the 2nd counter
B1, B2: the 1st and the 2nd buffer S1, S2: the 1st and the 2nd subtracter
C1-C4: 1-the 4th comparator T1, T2: the 1st and the 2nd trigger
Embodiment
The DE signal processing apparatus of DVI interface of the present invention is described as follows with reference to Fig. 3 with by way of example:
The LPF104 of above-mentioned DE signal processing apparatus is the operating state that detects above-mentioned level or vertical synchronizing signal after level or the vertical synchronizing signal low-pass filtering high level state or low level state.Above-mentioned detected polarity information, offer level and vertical synchronizing signal polarity correction portion 102.
Above-mentioned level and vertical synchronizing signal polarity correction portion 102, receive vertical and horizontal-drive signal, according to above-mentioned polarity information, not the state of being scheduled to if vertically reach the operating state of horizontal-drive signal, then above-mentioned vertical and horizontal-drive signal upset back output.
The level of above-mentioned level and 102 outputs of vertical synchronizing signal polarity correction portion and vertical synchronizing signal and DE signal are imported into level and vertical synchronizing signal reproducing unit 100.
Above-mentioned level and vertical synchronizing signal reproducing unit 100 are benchmark with above-mentioned DE signal, and regeneration level and vertical synchronizing signal with maintenance level and vertical synchronizing signal, and are shown in image the middle position of picture.
Above-mentioned level and vertical synchronizing signal reproducing unit 100 are made up of horizontal-drive signal and vertical synchronizing signal reproducing unit, with reference to Fig. 4 and Fig. 5, describe the composition of horizontal-drive signal reproducing unit and vertical synchronizing signal reproducing unit in detail and move as follows:
The detailed composition of above-mentioned horizontal-drive signal reproducing unit is described with reference to Fig. 4.The DE signal is imported into the input of the 1st AND gate AND1 and the 1st trigger D1.Above-mentioned the 1st trigger D1 is a clock pulse with the horizontal-drive signal that polarity is corrected, and above-mentioned DE signal and horizontal-drive signal are exported synchronously.Above-mentioned the 1st AND gate AND1 with above-mentioned DE signal and the signal by the 1st trigger D1 output and upset " with " back output.That is, above-mentioned the 1st AND gate AND1 produces the signal of the starting point of expression DE signal.
The horizontal-drive signal that above-mentioned polarity has been corrected is input to the input of the 2nd trigger D2, will be input to the 2nd AND gate AND2 after its upset simultaneously.Above-mentioned the 2nd trigger D2, output is synchronized with the horizontal-drive signal that the above-mentioned polarity of clock pulse has been corrected, and this output is imported into the 2nd AND gate AND2.Above-mentioned the 2nd AND gate AND2, horizontal-drive signal that above-mentioned polarity of having overturn has been proofreaied and correct and the above-mentioned signal that passes through the 2nd trigger D2 output " with " back output.That is, above-mentioned the 2nd AND gate AND2 produces the signal of the above-mentioned horizontal-drive signal starting point of expression.
Also have, the 1st counter cnt 1 behind horizontal clock pulse count, is exported the result, and is resetted according to the output of the 2nd AND gate AND2.That is, above-mentioned counter cnt 1, counting when the starting point of each above-mentioned horizontal-drive signal resets.
And the 1st buffer B1 is started by the output of above-mentioned the 1st AND gate AND1, exports the count value of above-mentioned the 1st counter cnt 1.That is, above-mentioned the 1st buffer B1 output begins during produce the DE signal from previously generated horizontal synchronization starting point, and the numerical value of clock pulse, this numerical value are imported into the 3rd trigger D3.The above-mentioned numerical value of output that above-mentioned the 3rd trigger D3 and clock pulse are synchronous.
Also have, the 1st subtracter S1, the numerical value that above-mentioned the 1st counter cnt 1 is exported deducts the numerical value that the 3rd trigger D3 exports, and offers the 1st and the 2nd comparator C 1, C2 subtracting the calculation result.
Above-mentioned the 1st comparator C 1 is calculated relatively its result of back output of result with the side-play amount and the subtracting of above-mentioned subtracter S1 output that rise.Above-mentioned the 2nd comparator C 2, with subtracting of the side-play amount that descends and above-mentioned subtracter S2 output calculate the result relatively after, export its result.
The the above-mentioned the 1st and the 2nd comparator C 1, the output of C2 are combined into one and are imported into the 1st trigger T1.Above-mentioned the 1st trigger T1, according to the above-mentioned the 1st and the 2nd comparator C 1, the output of C2 produces continuous output signal, and this output is used as new horizontal-drive signal output.
In sum, as follows to the action schematic illustration of horizontal-drive signal reproducing unit: above-mentioned the 1st counter cnt 1, the starting point of horizontal-drive signal is reset before each, begins new counting.That is, in Fig. 1
Become the starting point of above-mentioned counter.If produce the DE signal, buffer B1 then inputs to subtracter to the count value in above-mentioned counter of the generation starting point of DE signal.That is, DE signal generation starting point is in Fig. 1
, above-mentioned subtracter deducts the count value of the generation starting point of above-mentioned DE signal from the count value that continue to increase, and it subtracts calculates the corresponding trailing edge side-play amount of result, exports after then triggering the 1st trigger T1.That is, in Fig. 1
Become the continuous signal starting point.If above-mentioned subtracting calculated the corresponding rising edge side-play amount of result, export after then triggering the 1st trigger T1.That is, in Fig. 1
Become the continuous signal starting point.
So, above-mentioned horizontal-drive signal reproducing unit is exported after making horizontal-drive signal corresponding to the DE signal.
Below, with reference to Fig. 5 above-mentioned vertical synchronizing signal reproducing unit is described.The DE signal is imported into the input of the 3rd AND gate AND3 and the 4th trigger D4.Above-mentioned the 4th trigger D4 is a clock pulse with the vertical synchronizing signal that polarity is corrected, and above-mentioned DE signal and above-mentioned vertical synchronizing signal are exported synchronously.Above-mentioned the 3rd AND gate AND3, with above-mentioned DE signal and the signal by the 4th trigger D4 output and upset " with " back output.That is, above-mentioned the 3rd AND gate AND3 produces the signal of expression DE signal starting point.
The vertical synchronizing signal that above-mentioned polarity is corrected is input to the input of the 5th trigger D5, will be input to the 4th AND gate AND4 after its upset simultaneously.The vertical synchronizing signal that the synchronous above-mentioned polarity of above-mentioned the 5th trigger D5 output and double horizontal-drive signal is corrected, this output is imported into the 4th AND gate AND4.Above-mentioned the 4th AND gate AND4, vertical synchronizing signal that above-mentioned polarity of having overturn has been proofreaied and correct and the above-mentioned signal that passes through the 5th trigger D5 output " with " back output.That is, above-mentioned the 4th AND gate AND4, the signal of the starting point of the above-mentioned vertical synchronizing signal of generation expression.
Also have, the 2nd counter cnt 2 to its result of output behind the above-mentioned clock pulse count, and resets according to the output of the 4th AND gate AND4.That is, the 2nd counter cnt 2, counting when each starting point that above-mentioned vertical synchronizing signal produces resets.
Also have, the 2nd buffer B2 is started by the output of the 3rd AND gate AND3, exports the count value of above-mentioned the 2nd counter cnt 2.That is, above-mentioned the 2nd buffer B2 output, from before the starting point of generation vertical synchronizing signal begin during produce the DE signal, the numerical value of clock pulse, this numerical value input to the 6th trigger D6.Above-mentioned the 6th trigger D6 and clock pulse be the above-mentioned numerical value of output synchronously.
The 2nd subtracter S2, the numerical value that above-mentioned the 2nd counter cnt 2 is exported deducts the numerical value that above-mentioned the 6th trigger D6 exports, and the result is offered the 3rd and the 4th comparator C 3, C4.
Above-mentioned the 3rd comparator C 3, relatively side-play amount of Shang Shenging and above-mentioned the 2nd subtracter S2 output subtract the calculation result, export its result.The side-play amount that above-mentioned the 4th comparator C 4 relatively descends and above-mentioned the 2nd subtracter S2 output subtract the calculation result, export its result.
The the above-mentioned the 3rd and the 4th comparator C 3, the output of C4 is combined into one, is input to the 2nd trigger T2.Above-mentioned the 2nd trigger T2 is according to the above-mentioned the 3rd and the 4th comparator C 3, and the output of C4 produces continuous output information, and this output is output as new vertical synchronizing signal.
So, above-mentioned vertical synchronizing signal reproducing unit is processed into vertical synchronizing signal can export behind the corresponding DE signal.
Claims (3)
1, a kind of permission data-signal processing unit of interactive digital video system interface is characterized in that being made of following part:
By above-mentioned interactive digital video system interface, receive the vertical low pass filter that reaches horizontal-drive signal and detect operating state;
Reach horizontal-drive signal or the polarity correction portion of the output of keeping intact according to the work state information upset of low pass filter output is vertical;
Obtain level and vertical synchronizing signal and permission data-signal that polarity has been corrected, make it can correspondingly allow data-signal, the level and the vertical synchronizing signal reproducing unit of regeneration level and vertical synchronizing signal and output.
2, the permission data-signal processing unit of interactive digital video system interface according to claim 1 is characterized in that described horizontal-drive signal reproducing unit is to be made of following part:
Produce the 1st gate circuit portion of the 1st signal of the above-mentioned permission data-signal starting point of expression;
Produce the 2nd gate circuit portion of the 2nd signal of the expression horizontal-drive signal starting point of above-mentioned polarity correction portion output;
To clock pulse count, the counter that resets according to the 2nd signal;
According to the 1st signal, the count value of above-mentioned counter is carried out the buffer of buffer memory;
The count value of cache size and above-mentioned counter is carried out subtraction, and the subtraction portion of result's output;
The 1st comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and rising;
The 2nd comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and decline;
According to the above-mentioned the 1st and the 5th gate circuit portion that exports repeatedly of the output of the 2nd comparator.
3, the permission data-signal processing unit of interactive digital video system interface according to claim 1 is characterized in that described vertical synchronizing signal reproducing unit is to be made of following part:
Produce the 3rd gate circuit portion of the 3rd signal of the above-mentioned permission data-signal starting point of expression;
Produce the 4th gate circuit portion of the 4th signal of the expression vertical synchronizing signal starting point of above-mentioned polarity correction portion output;
With double horizontal-drive signal counting, and the counter that resets according to the 4th signal;
According to above-mentioned the 3rd signal, the count value of above-mentioned counter is carried out the buffer of buffer memory;
The count value of the value sum counter of above-mentioned buffer is carried out subtraction, and output subtracts the subtraction portion of calculating the result;
The 3rd comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and rising;
The 4th comparator of the relatively back output of the side-play amount of the output of above-mentioned subtraction portion and decline;
The 6th gate circuit portion that exports repeatedly according to the output of the 3rd and the 4th comparator.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102025890A (en) * | 2009-09-22 | 2011-04-20 | 康佳集团股份有限公司 | Method and system for restoring video line synchronizing signal |
| CN102158655A (en) * | 2011-01-27 | 2011-08-17 | 大连科迪视频技术有限公司 | Jitter-free post-correction system for digital video interface (DVI)/high definition multimedia interface (HDMI)/display port (DP)/video graphics array (VGA) signals |
| CN102439974A (en) * | 2009-05-22 | 2012-05-02 | 株式会社巨晶片 | Video playback system and video playback method |
| CN109618074A (en) * | 2018-12-23 | 2019-04-12 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of Robust Design method to nonstandard input vesa timing |
-
2005
- 2005-08-30 CN CN 200510047108 patent/CN1925593A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102439974A (en) * | 2009-05-22 | 2012-05-02 | 株式会社巨晶片 | Video playback system and video playback method |
| CN102439974B (en) * | 2009-05-22 | 2015-01-28 | 株式会社巨晶片 | Video playback system and video playback method |
| CN102025890A (en) * | 2009-09-22 | 2011-04-20 | 康佳集团股份有限公司 | Method and system for restoring video line synchronizing signal |
| CN102025890B (en) * | 2009-09-22 | 2015-01-28 | 康佳集团股份有限公司 | Method and system for restoring video line synchronizing signal |
| CN102158655A (en) * | 2011-01-27 | 2011-08-17 | 大连科迪视频技术有限公司 | Jitter-free post-correction system for digital video interface (DVI)/high definition multimedia interface (HDMI)/display port (DP)/video graphics array (VGA) signals |
| CN102158655B (en) * | 2011-01-27 | 2012-09-26 | 大连科迪视频技术有限公司 | Jitter-free post-correction system for digital video interface (DVI)/high definition multimedia interface (HDMI)/display port (DP)/video graphics array (VGA) signals |
| CN109618074A (en) * | 2018-12-23 | 2019-04-12 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of Robust Design method to nonstandard input vesa timing |
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