CN109427276A - Display device, sequential control circuit and its signal reconstruction method - Google Patents
Display device, sequential control circuit and its signal reconstruction method Download PDFInfo
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- CN109427276A CN109427276A CN201710765651.3A CN201710765651A CN109427276A CN 109427276 A CN109427276 A CN 109427276A CN 201710765651 A CN201710765651 A CN 201710765651A CN 109427276 A CN109427276 A CN 109427276A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The present invention provides a kind of display device, including sequential control circuit and image processing system.Sequential control circuit receives image data, clock signal and the multiple synchronous control signals of image processing system output.Multiple synchronous control signals include at least one periodic synchronous control signal and acyclic synchronous control signal.Sequential control circuit includes signal reconstruction module and signal processing module.Signal reconstruction module synchronous control signal of detection cycle in the initial stage obtains the first parameter, is voluntarily generated according to the first parameter with counting mode and rebuilds synchronous control signal.Signal processing module generates grid control signal and source control signal according to image data, reconstruction synchronous control signal and acyclic synchronous control signal.The present invention also provides a kind of sequential control circuit and its signal reconstruction methods.
Description
Technical field
The present invention relates to a kind of display device, sequential control circuit and its signal reconstruction methods.
Background technique
With the continuous development of electronic technology, mobile phone, portable computer, personal digital assistant (PDA), plate calculate
The consumer electrical products such as machine, media player are mostly all using display as input-output equipment, so that product has more
Friendly man-machine interaction mode.Usual display includes display panel and the display driving for driving display panel display image
Circuit.Driving circuit includes sequence controller, scan drive circuit and data drive circuit.Sequence controller is received by image
The viewdata signal and synchronous control signal that processing system issues, export scan control signal to scan drive circuit and export
Data controlling signal is to data drive circuit.Wherein, display control signal includes vertical synchronizing signal (Vertical
Synchronization, Vsync), horizontal synchronizing signal (Horizontal synchronization, Hsync), master clock
(Main system clock, MCLK), data enable signal (Data enable, DE) etc..In general, data enable signal is week
The pulse signal of phase property, and high level is effective.When data enable signal is effective, the data information of the corresponding output of sequence controller
Effectively to show data and being shown by display panel.It is two chips in image processing system and sequential control circuit,
Data make signal between in transmission process, and the input pin of sequence controller is easy by electrostatic (Electro
Static Discharge, ESD) etc. factors interference so that received input generate jump or concussion.Work as data enable signal
When DE jump or concussion, so that data drive circuit in such as display device mistakenly driving data line, leads to display panel
Display picture it is abnormal.
Summary of the invention
In view of this, it is necessary to provide a kind of preferable display devices of interference resistant jamming performance.
It there is a need to provide a kind of preferable sequential control circuit of interference resistant jamming performance.
It there is a need to provide a kind of preferable signal reconstruction method of interference resistant jamming performance.
A kind of display device includes display driving system and image processing system.Display driving system includes timing control
Circuit, scan drive circuit and data drive circuit.The image data of sequential control circuit reception image processing system output,
Clock signal and multiple synchronous control signals, and grid control signal is generated to control scan drive circuit and source electrode control letter
Number to control data drive circuit.Multiple synchronous control signals include at least one periodic synchronous control signal and aperiodic
The synchronous control signal of property.Sequential control circuit includes signal reconstruction module and signal processing module.Signal reconstruction module is first
The synchronous control signal of detection cycle obtains the first parameter when stage beginning, voluntarily generates weight with counting mode according to the first parameter
Synchronous control signal is built, influences the reconstruction synchronous control signal to avoid noise noise.First parameter is for characterizing periodicity
The cycle length of synchronization signal.Rebuilding synchronous control signal is the signal for having identical first parameter with cyclical signal.Signal
Processing module generates grid control letter according to image data, reconstruction synchronous control signal and acyclic synchronous control signal
Number and source control signal.
A kind of sequential control circuit receives the image data, clock signal and multiple synchronous controls of image processing system output
Signal processed, and grid control signal is generated to control scan drive circuit and source control signal to control data drive circuit.
Multiple synchronous control signals include at least one periodic synchronous control signal and acyclic synchronous control signal.Timing
Control circuit includes signal reconstruction module and signal processing module.Signal reconstruction module in the initial stage detection cycle it is same
Step control signal obtains the first parameter, is voluntarily generated according to the first parameter with counting mode and rebuilds synchronous control signal, to avoid
Noise noise influences the reconstruction synchronous control signal.First parameter is used to characterize the cycle length of periodic synchronization signal.Weight
Building synchronous control signal is the signal for having identical first parameter with cyclical signal.Signal processing module according to image data,
It rebuilds synchronous control signal and acyclic synchronous control signal generates grid control signal and source control signal.
A kind of signal reconstruction method, in the sequential control circuit of display device；Sequential control circuit receives image system
Image data, clock signal and the multiple synchronous control signals of system output.Multiple synchronous control signals include at least one week
The synchronization signal of phase property and acyclic synchronization signal.Signal reconstruction method includes the following steps:
Receive image data, clock signal and synchronous control signal, and in the initial stage detection cycle synchronization
Signal is controlled to obtain the first parameter；
Initial pulse is generated according to synchronous control signal；
It is voluntarily generated according to periodic initial pulse and the first parameter with counting mode and rebuilds synchronous control signal, with
Noise noise is avoided to influence the reconstruction synchronous control signal；
According to image data, rebuild synchronous control signal and acyclic synchronous control signal generation grid control letter
Number and source control signal.
The sequential control circuit of above-mentioned display device, by simulate externally input periodic synchronous control signal and
Internal voluntarily generate rebuilds synchronous control signal, and the pin for preventing system noise from scurrying into sequential control circuit causes output to scanning
The synchronous control signal of driving circuit and data drive circuit generates mutation, and then has ensured the steady of sequential control circuit work
It is qualitative.
Detailed description of the invention
Fig. 1 is a kind of schematic equivalent circuit of the display device of better embodiment.
Fig. 2 is the functional block diagram of the signal reconstruction module of display device shown in Fig. 1.
Fig. 3 is the synchronous control signal of first embodiment reconstruction unit shown in Fig. 2, initial pulse, counter and again
Build the time diagram of synchronous control signal.
Fig. 4 is the received synchronously control during the first level with noise noise of signal reconstruction module shown in Fig. 2
Signal, counter and the time diagram for rebuilding control signal.
Fig. 5 is the received synchronously control during second electrical level with noise noise of signal reconstruction module shown in Fig. 2
Signal, counter and the time diagram for rebuilding synchronous control signal.
Fig. 6 is the synchronous control signal of the signal reconstruction module of second embodiment shown in Fig. 2, rebuilds synchronously control letter
Number, thermal compensation signal and it is compensated rebuild synchronous control signal time diagram.
Fig. 7 is the flow chart of the signal reconstruction method for sequential control circuit of first embodiment.
Fig. 8 is the flow chart of the signal reconstruction method for sequential control circuit of second embodiment.
Main element symbol description
Display device 1
Display panel 100
Display driving system 200
Image processing system 500
Scan line 102
Data line 104
Pixel unit 106
Sequential control circuit 20
Signal reconstruction module 21
Signal processing module 23
Computing unit 213
Reconstruction unit 215
Counter 217
Scan drive circuit 40
Data drive circuit 60
Signal reconstruction method S501-S506
The present invention that the following detailed description will be further explained with reference to the above drawings.
Specific embodiment
This exposure provides a kind of display device with sequential control circuit, and sequential control circuit detection is examined in the initial stage
The periodic synchronous control signal of altimetric image processing system input is to obtain at least one parameter and according at least one parameter
It is voluntarily generated in inside with counting mode and rebuilds synchronous control signal, the pin for preventing system noise from scurrying into sequential control circuit is led
It causes synchronous control signal to generate mutation, and then has ensured the stability of sequential control circuit work.
Referring to Fig. 1, Fig. 1 is the schematic equivalent circuit of the display device 1 of one embodiment of the invention.The display device
1 includes display panel 100, display driving system 200 and image processing system 500.Display panel 100 includes a plurality of mutually flat
Capable scan line 102 and a plurality of data line 104 being parallel to each other.Multi-strip scanning line 102 and 104 mutually insulated of multiple data lines
Setting, defines multiple pixel units 106 arranged in arrays.Display driving system 200 includes sequential control circuit 20, scanning
Driving circuit 40 and data drive circuit 60.Every one-row pixels unit passes through a scan line 102 and scan drive circuit 40
It is electrically connected, each column pixel unit 106 is electrically connected by a data line 104 with data drive circuit 60.In this implementation
In mode, image processing system 500 is for outputting data signals and synchronous control signal to display driving system 200.
Sequential control circuit 20 is electrically connected with scan drive circuit 40 and data drive circuit 60 respectively.Timing control
Circuit 20 receives image data, multiple synchronous control signals and the clock signal (Main that image processing system 500 inputs
System clock, MCLK), image data is buffered, and according to image data, multiple synchronous control signals and clock
Signal generates grid control signal to scan drive circuit 40 and source control signal to data drive circuit 60.Multiple synchronizations
Controlling signal may include periodic synchronous control signal and acyclic synchronous control signal.Multiple synchronous control signal packets
Include vertical synchronizing signal (Vertical synchronization, Vsync), horizontal synchronizing signal (Horizontal
Synchronization, Hsync) and data enable signal (Data Enable, DE).Wherein, data enable signal DE is
Periodic synchronous control signal.Periodic synchronous control signal is class square-wave signal, is by the first level and second electrical level
The pulse signal periodically alternately constituted, wherein the first level is high level, and second electrical level is low level.In present embodiment
In, sequential control circuit 20 is the chip with multiple pins.However, synchronous control signal image processing system 500 and when
When being transmitted between sequence control circuit 20, since the pin that electrostatic or other factors scurry into sequential control circuit 20 can lead to week
The synchronous control signal of phase property generates mutation and has noise noise, during can produce the output of the first level and/or second
During level exports, and noise noise is usually expressed as the oscillation that frequency of oscillation is apparently higher than periodic synchronous control signal
Wave.For example, synchronous control signal as shown in Figure 4, periodic synchronization signal is when script should maintain the first level
In section, noise noise is generated.That is, including that there is the periodic synchronous of noise noise to believe in multiple synchronous control signal
Number.
Sequential control circuit 20 is in addition to the basic function of sequential control circuit 20, additionally it is possible to eliminate in periodic synchronization signal
Noise noise, sequential control circuit 20 include signal reconstruction module 21 and signal processing module 23.Signal reconstruction module 21 is used
In initial stage detection cycle synchronous control signal with obtain at least one parameter and according at least one above-mentioned parameter with
Counting mode regeneration rebuilds synchronous control signal.The parameter can characterize the period of ideal periodic synchronization signal.At this
In exposure, which includes that characterization periodic synchronization signal is in the first level state in any one frame time of initial stage
Quantity the first parameter.Further, which further comprises characterizing periodic synchronization signal appointing in the initial stage
Second parameter of the interior quantity in second electrical level state of a frame time of anticipating.Utilize the first parameter and sequential control circuit itself
Crystal oscillator pulse width can define the pulse width of the first level in the period, utilize the second parameter and sequential control circuit itself
Crystal oscillator pulse width can second electrical level in the period width.
It is found through studying with the waveform for the synchronous control signal for observing output, the signified initial stage in this exposure, including
Following several situations it is one of or several:
One, under an initial stage, the booting power up phase of display device 1 was exported to the period of sequential control circuit 20
Property synchronization signal is influenced small by the external world, and the waveform of periodic synchronization signal is more accurate, and the parameter detected is more accurate.?
In the present embodiment, it has been investigated that, following four frame time after booting powers on, the received periodicity of sequential control circuit 20
Synchronization signal is influenced small by the external world, is suitable for the period of the measurement period synchronization signal within this period, and further calculate first
Parameter.
Two or under another initial stage, it is shown to next frame picture in frame picture completion and exports and give timing control electricity
Before road 20, it will usually the Electro-static Driven Comb process for carrying out display device 1, initial stage after the completion of Electro-static Driven Comb, as electrostatic is released
Four frame times immediately after the completion of putting, exporting is influenced small, week by the external world to the periodic synchronization signal of sequential control circuit 20
The waveform of phase property synchronization signal is more accurate, and the parameter detected is more accurate.
Three or the initial stage after other situations or other Electro-static Driven Comb, as after the completion of Electro-static Driven Comb immediately
Four frame times, exporting is influenced to the periodic synchronization signal of sequential control circuit 20 by the external world also smaller, is also appropriate for the period
More accurate parameter of the waveforms detection of property synchronization signal to obtain.
It is appreciated that no matter in which kind of above-mentioned situation, the when a length of scheduled duration of initial stage, in the present embodiment,
The when a length of four frames duration of the initial stage.Acquisition for the first parameter, can be in the four frame durations within the initial stage
Any one frame is object, or the first parameter summation corresponding to whole frame is averaged in the four frame durations of initial stage
Value.
Signal processing module 23 is according to image data, aperiodicity synchronization signal and rebuilds synchronous control signal generation grid
Pole control signal to scan drive circuit 40 and generates source control signal to data drive circuit 60.Wherein, synchronous control is rebuild
Signal processed is that sequential control circuit 20 is voluntarily generated according to parameter, and does not have the periodic synchronization signal of noise noise.Also
It is to say, rebuilding synchronous control signal is the alternate pulse signal of periodicity being made of the first level and second electrical level, and first
The pulse width of level is determined according to the first parameter.
Please refer to figs. 2 and 3 together, and Fig. 2 discloses the structural block diagram of an embodiment of signal reconstruction module 21, Fig. 3
The waveform of announcement is for explaining the working principle of this exposure signal reconstruction module 21.For ease of illustration of principle, Fig. 3 is disclosed same
Step control signal waveform is that the cycle synchronisation without noise noise controls signal or can be regarded as the period in the initial stage
Synchronous control signal.
Signal reconstruction module 21 includes computing unit 213 and reconstruction unit 215.The monitoring of computing unit 213 and calculating are first
The cycle synchronisation control signal received when stage beginning is to obtain the first parameter.Wherein, the initial stage is above-mentioned listed initial rank
Several situations of section are one kind of or several.In the present embodiment, the first parameter is that periodic synchronous controls signal first
The quantity of the first level state is in during stage beginning.
Reconstruction unit 215 is built-in with an at least counter 217.The counter 217 stores the first parameter, and with first ginseng
Number is used as count value.Reconstruction unit 215 generates initial pulse in the rising edge of received cycle synchronisation control signal, according to first
Parameter is generated with counting mode and rebuilds synchronous control signal.Specifically, reconstruction unit 215 is by the received week in the initial stage
Phase synchronous control signal rises to starting point along initial pulse SV is generated, using the failing edge of initial pulse SV as starting point output first
Level and this hour counter 217 starts counting, wherein initial pulse SV has a scheduled pulse width or scheduled duty
Than, scheduled pulse width/duty ratio of initial pulse is less than pulse width/duty ratio of periodic synchronous control signal, this
In pulse width refer to that the duration for maintaining the first level in one cycle, duty ratio refer to the ratio in the first level and period；
When the stored count value of counter 217 is equal to the first parameter, stops the first level of output and export second electrical level, resetting counts
Device 217, the i.e. reconstruction of the synchronous control signal of completion a cycle.Wherein, initial pulse by synchronous control signal rising edge
Triggering, i.e., synchronous control signal is switched to the first level by second electrical level.In the present embodiment, the pulse width of initial pulse
It is determined by the clock widths of the intrinsic crystal oscillator generation of sequential control circuit 20 itself.
Illustrate the working principle of signal reconstruction module 21 by taking the data enable signal of input as an example below.Wherein, data make
Energy signal is used for whether the data-signal that control sequential control circuit 20 receives can be shown by display panel 100, and
It can be shown by display panel 100 in the image data that sequential control circuit 20 receives is controlled in high level.
Also referring to Fig. 3, computing unit 213 monitors and is calculated the first parameter N according to data enable signal.Its
In, the first parameter N is the quantity that data enable signal DE is in the first level state in a corresponding frame time.In the present embodiment
In, the period that obtains of first parameter N is any one frame time in period initial stage.Change ground, first parameter N
Are as follows: in all four frame times of period initial stage, the data enable signal DE for monitoring each frame time is in the first level
The average value of the summation of the quantity of state.
Reconstruction unit 215 generates initial pulse according to data enable signal DE, according to the failing edge of initial pulse as weight
The starting point that data enable signal exports the first level is built, with the pulse width or a timing control of one initial pulse of every output
The intrinsic crystal oscillator pulse width of circuit 20 processed is unit width, and continuously exports N number of unit from the starting point according to the first parameter N
First level of width is to generate reconstruction data enable signal.Specifically, reconstruction unit 215 by data enable signal DE rising
It is starting point along initial pulse is generated, exports the first level by starting point of the failing edge of initial pulse, unison counter 217 starts to count
Number, reconstruction unit 215 keep the output of the first level during 217 keeping count of counter, and the first level of every output when
When length is equal to a unit width duration, counter 217, which counts, adds one；When the stored count value of counter 217 is equal to N, stop
It only exports the first level and exports second electrical level until the failing edge of next initial pulse, reset counter 217, that is, complete one
The reconstruction of a cycle data enable signal.Wherein, initial pulse is triggered by the rising edge of data enable signal DE, i.e., data are enabled
Signal is switched to the first level by second electrical level.
Referring to Fig. 4, noise noise can enter sequential control circuit 20 by pin after the initial stage, can lead
The synchronous control signal for causing sequential control circuit 20 to receive during the first level of script there is frequency of oscillation to be higher than itself
Waveform, due to reconstruction unit 215 can according to the rising edge of data enable signal DE generate initial pulse SV, and with rise
The failing edge of initial pulse SV is that starting point exports the first level, and unison counter 217 starts counting, and reconstruction unit 215 is in counter
The output of the first level is kept during 217 keeping counts, and the duration of the first level of every output is equal to a unit width duration
When, counter 217, which counts, adds one；When the stored count value of counter 217 is equal to the first parameter, stop the first level of output simultaneously
Second electrical level is exported until the failing edge of next initial pulse, counter 217 is reset, completes a cycle.Reconstruction unit 215
Masking is generated using the tally function of counter 217, the synchronous control signal with noise noise is avoided and is directly output to letter
Number processing module 23, and then ensure that the stability of the received synchronous control signal of signal processing module 23.
Referring to Fig. 5, noise noise can enter sequential control circuit 20 by pin after the initial stage, can lead
The synchronous control signal for causing sequential control circuit 20 to receive during the second electrical level of script there is frequency of oscillation to be higher than itself
Waveform, since reconstruction unit 215 generates initial pulse SV according to the rising edge of data enable signal DE, and to originate arteries and veins
The failing edge for rushing SV is that starting point exports the first level, and unison counter 217 starts counting, and reconstruction unit 215 is held in counter 217
It is continuous count during keep the output of the first level, and when the duration of the first level of every output is equal to a unit width duration, meter
Number device 217, which counts, adds one；When the stored count value of counter 217 is equal to the first parameter N, stops the first level of output and export
Second electrical level resets counter 217 until the failing edge of next initial pulse, completes a cycle.Reconstruction unit 215 utilizes
The tally function of counter 217 generates masking, avoids the synchronous control signal with noise noise and is directly output at signal
Module 23 is managed, and then ensure that the stability of the received synchronous control signal of signal processing module 23.
The sequential control circuit of the display device of above-described embodiment can prevent system noise from scurrying into sequential control circuit
Pin causes synchronous control signal to generate mutation, and then has ensured the stability of sequential control circuit work.
Referring to Figure 6 together, for this exposure second embodiment sequential control circuit signal reconstruction module when
Sequence figure.In this second embodiment, identical as element name with the same function in first embodiment.In the present embodiment
In, the parameter includes the first parameter and the second parameter, and the first parameter is identical as the first parameter of first embodiment.
Further detection rebuilds synchronous control signal with the presence or absence of exception to signal reconstruction module 21, is rebuilding synchronously control letter
It number deposits and thermal compensation signal to be generated according to the second parameter when abnormal, synchronous control signal will be rebuild and thermal compensation signal carries out logical operation
After obtain compensated reconstruction synchronous control signal, and the signal is exported to signal processing module 23.When noise noise generates
When inputting the rising edge of synchronous control signal, the reconstruction synchronous control signal that signal reconstruction module 21 generates can cover next
The initial pulse of the synchronous control signal in period, so that the first parameter for rebuilding synchronous control signal is less than the synchronously control of input
First parameter of signal, and then rebuild synchronous control signal and there is exception.
The monitoring of computing unit 213 and calculating obtain the first parameter and second in initial stage received synchronous control signal and join
Number.Wherein, the first parameter N is the quantity that data enable signal DE is in the first level state in a corresponding frame time.In this reality
It applies in example, the period that obtains of first parameter N is any one frame time in period initial stage.Ground is changed, this first
Parameter N are as follows: in all four frame times of period initial stage, the data enable signal DE for monitoring each frame time is in first
The average value of the summation of the quantity of level state.Second parameter is the synchronous control signal of a corresponding frame time periodically first
The quantity of second electrical level state is in during stage beginning.In the present embodiment, the acquisition period of second parameter is the initial stage
Any one frame time in period.Change ground, the second parameter are as follows: in all four frame times of period initial stage, prison
Survey each frame time data enable signal DE be in second electrical level state quantity summation average value.
Reconstruction unit 215 is built-in with an at least counter 217.Reconstruction unit 215 is generated according to data enable signal DE
Initial pulse, according to the failing edge of initial pulse as the starting point for rebuilding data enable signal the first level of output, with every output
The pulse width of one initial pulse or the intrinsic crystal oscillator pulse width of a sequential control circuit 20 are unit width, and according to
First parameter N exports the first level of N number of unit width continuously from the starting point to generate reconstruction data enable signal, monitoring weight
Synchronous control signal is built with the presence or absence of the first level for corresponding to synchronous control signal at failing edge place just.Control is synchronized when rebuilding
When corresponding to the first level of synchronous control signal at where the failing edge of signal processed, reconstruction unit 215 is generated according to the second parameter
Thermal compensation signal.Thermal compensation signal is pulse signal.Wherein, thermal compensation signal corresponds to where the failing edge for rebuilding synchronous control signal
Second electrical level is in when the first level of synchronous control signal, in the counting again of counter 217 and count value is equal to the second ginseng
The first level is switched to by second electrical level when number, and when rebuilding synchronous control signal and corresponding to the failing edge of synchronous control signal by
First level is switched to second electrical level.Reconstruction unit 215 is by thermal compensation signal and after rebuilding synchronous control signal progress logical operation
It exports to signal processing module 23.Wherein, the first electricity of synchronous control signal is corresponded in the failing edge for rebuilding synchronous control signal
Usually, it rebuilds synchronous control signal and there is exception, can lead to the corresponding initial pulse quilt of synchronous control signal of next cycle
Masking, can not generate corresponding reconstruction synchronous control signal.The first parameter for rebuilding synchronous control signal is less than synchronously control
First parameter of signal.By being exported after logic sum gate operation between thermal compensation signal and reconstruction synchronous control signal.In this implementation
In mode, the pulse width of the pulse width initial pulse of initial pulse is generated by the intrinsic crystal oscillator of sequential control circuit 20 itself
Clock widths determine.
Specifically, it is illustrated by taking data enable signal DE as an example, reconstruction unit 215 is with the rising of data enable signal DE
Along being that starting point generates initial pulse, the first level is exported by starting point of the failing edge of initial pulse, unison counter 217 starts to count
Number, reconstruction unit 215 keep the output of the first level during 217 keeping count of counter, and the first level of every output when
When length is equal to a unit width duration, counter 217, which counts, adds one；It is equal to the first ginseng in the stored count value of counter 217
When number N, stops the first level of output and export second electrical level until the failing edge of next initial pulse SV arrives, resetting counts
Device 217；Monitoring by the first level be switched to second electrical level be formed by where failing edge whether corresponding data enable signal
First level.If the first level of corresponding data enable signal, counter 217 start counting at where failing edge, reconstruction unit
215 generate thermal compensation signal, and thermal compensation signal is in second electrical level state, and thermal compensation signal is protected during 217 keeping count of counter
Hold the output of second electrical level, and when the duration of every output second electrical level is equal to a unit width duration, counter 217 count plus
One；When the stored count value of counter 217 is equal to the second parameter, thermal compensation signal is switched to the first level by second electrical level, and
When rebuilding the failing edge of data enable signal corresponding data enable signal, thermal compensation signal is switched to second electrical level by the first level；
Reconstruction unit 215 is by thermal compensation signal and rebuilds control signal by output after logic sum gate (OR gate) operation to signal processing
Module 23.Thermal compensation signal is used for the first parameter N of compensated reconstruction data enable signal, so that rebuilding the of data enable signal
One parameter is equal with the first parameter N of data enable signal.In the present embodiment, the pulse width of thermal compensation signal is less than data
The pulse width of enable signal.
The sequential control circuit of above-mentioned display device, by simulate externally input periodic synchronous control signal and
Internal voluntarily generate rebuilds synchronous control signal, and the pin for preventing system noise from scurrying into sequential control circuit causes received synchronization
It controls signal and generates mutation, and then ensured the stability of sequential control circuit work.
Referring to Fig. 7, it is the flow chart of the corresponding signal reconstruction method of sequential control circuit 20, it is applied to display dress
It sets in 1 sequential control circuit 20.Sequential control circuit 20 receives image data, the Duo Getong that image processing system 500 inputs
Step control signal and clock signal (Main system clock, MCLK).The signal reconstruction method includes the following steps:
Step S701, computing unit 213 is monitored in the initial stage and the synchronous control signal of calculating cycle obtains the
One parameter.Wherein, the initial stage is that several situations of listed initial stage above are one kind of or several.First parameter is week
Phase property synchronous control signal is in the quantity of the first level state during the initial stage.In the present embodiment, first parameter N
Obtain the period be period initial stage in any one frame time.Change ground, first parameter N are as follows: in the initial stage
All in four frame times of period, monitor each frame time synchronous control signal be in the first level state quantity summation
Average value.
Step S702, reconstruction unit 215 generate initial pulse according to synchronous control signal.Wherein, initial pulse is by same
The rising edge of step control signal triggers.Initial pulse has a scheduled pulse width or scheduled duty ratio, initial pulse
Scheduled pulse width/duty ratio is less than pulse width/duty ratio of periodic synchronous control signal, and pulse width refers to here
The duration of the first level is maintained in one cycle, and duty ratio refers to the ratio in the first level and period.In the present embodiment,
The pulse width of initial pulse is determined by the clock widths that the intrinsic crystal oscillator of sequential control circuit 20 itself generates.
Step S703, reconstruction unit 215 are regenerated with counting mode according to initial pulse and the first parameter and rebuild synchronous control
Signal processed.Specifically, the starting point of the first level is exported as reconstruction synchronous control signal according to the failing edge of initial pulse, with
The pulse width of one initial pulse of every output or the intrinsic crystal oscillator pulse width of a sequential control circuit 20 are unit width,
And the first level of N number of unit width is exported continuously from the starting point to generate the synchronously control of reconstruction letter according to the first parameter N
Number.By taking data enable signal DE as an example, when generating data enable signal, reconstruction unit 215 is by with data enable signal DE's
Starting point is risen to along initial pulse is generated, exports the first level by starting point of the failing edge of initial pulse, unison counter 217 is opened
Begin to count, reconstruction unit 215 keeps the output of the first level, and the first level of every output during 217 keeping count of counter
Duration be equal to a unit width duration when, counter 217 count plus one；It is equal to N in the stored count value of counter 217
When, stop the first level of output and export second electrical level until the failing edge of next initial pulse, resets counter 217, i.e.,
Complete the reconstruction with data enable signal DE of a cycle.Wherein, initial pulse is touched by the rising edge of data enable signal DE
Hair, i.e., synchronous control signal is switched to the first level by second electrical level.
Step S704, signal processing module 23 is according to image data, compensated reconstruction synchronous control signal and non-week
The synchronous control signal of phase property generates grid control signal and source control signal.
Referring to Fig. 8, it is the flow chart of the corresponding signal reconstruction method of sequential control circuit 20, it is applied to display dress
It sets in 1 sequential control circuit 20.Sequential control circuit 20 receives image data, the Duo Getong that image processing system 500 inputs
Step control signal and clock signal (Main system clock, MCLK).The signal reconstruction method includes the following steps:
Step S801, the synchronous control signal of detection cycle in the initial stage of computing unit 213 obtain the first parameter
With the second parameter.Wherein, the initial stage is that several situations of above-mentioned listed initial stage are one kind of or several.First parameter
The quantity that signal is in the first level state during the initial stage is controlled for periodic synchronous.In the present embodiment, this first
The period that obtains of parameter N is any one frame time in period initial stage.Change ground, first parameter N are as follows: initial
Period in stage all in four frame times, the synchronous control signal for monitoring each frame time are in the quantity of the first level state
The average value of summation；The period that obtains of second parameter is any one frame time in period initial stage.Second parameter are as follows:
In all four frame times of period initial stage, the synchronous control signal for monitoring each frame time is in second electrical level state
The average value of the summation of quantity.
Step S802, reconstruction unit 215 generate initial pulse according to synchronous control signal.Wherein, initial pulse is by same
The rising edge of step control signal triggers.Initial pulse has a scheduled pulse width or scheduled duty ratio, initial pulse
Scheduled pulse width/duty ratio is less than pulse width/duty ratio of periodic synchronous control signal, and pulse width refers to here
The duration of the first level is maintained in one cycle, and duty ratio refers to the ratio in the first level and period.In the present embodiment,
The pulse width of initial pulse is determined by the clock widths that the intrinsic crystal oscillator of sequential control circuit 20 itself generates.
Step S803, reconstruction unit 215 are regenerated with counting mode according to initial pulse and the first parameter and rebuild synchronous control
Signal processed.Specifically, the starting point of the first level is exported as reconstruction synchronous control signal according to the failing edge of initial pulse, with
The pulse width of one initial pulse of every output or the intrinsic crystal oscillator pulse width of a sequential control circuit 20 are unit width,
And the first level of N number of unit width is exported continuously from the starting point to generate reconstruction synchronous control signal according to the first parameter N.
By taking data enable signal DE as an example, reconstruction unit 215 generates initial pulse by the starting point edge that rises to of data enable signal DE, with
The failing edge of initial pulse is that starting point exports the first level, and unison counter 217 starts counting, and reconstruction unit 215 is in counter
The output of the first level is kept during 217 keeping counts, and the duration of the first level of every output is equal to a unit width duration
When, counter 217, which counts, adds one；When the stored count value of counter 217 is equal to N, stops the first level of output and export the
Two level reset counter 217 until the failing edge of next initial pulse, i.e. completion a cycle data enable signal DE's
It rebuilds.Wherein, initial pulse is triggered by the rising edge of data enable signal DE, i.e., synchronous control signal is switched to by second electrical level
First level.
Step S804, the detection of reconstruction unit 215 rebuild synchronous control signal with the presence or absence of abnormal.If rebuilding synchronously control letter
Number exist abnormal, then enters step S805；If rebuilding synchronous control signal has exception there is no exception, enter step
S806.When noise noise results from the rising edge of input synchronous control signal, the reconstruction that signal reconstruction module 21 generates is synchronous
Control signal can cover the initial pulse of the synchronous control signal of next cycle, so that rebuilding the first ginseng of synchronous control signal
Number is less than the first parameter of the synchronous control signal of input, and then rebuilds synchronous control signal in the presence of abnormal.Specifically, it rebuilds single
It is the first electric of synchronous control signal that it is just corresponding with the presence or absence of place where failing edge, which to rebuild synchronous control signal, for 215 monitoring of member
It is flat.
Step S805, reconstruction unit 215 according to the second parameter generate thermal compensation signal and by thermal compensation signal it is synchronous with reconstruction control
Signal processed exports after carrying out logical operation.Reconstruction unit 215 is corresponding where the failing edge of re-synchronization control signal to be
When the first level of synchronous control signal, counter 217 is started counting, and thermal compensation signal is in second electrical level；It is held in counter 217
It is continuous count during thermal compensation signal keep the output of second electrical level, and when the duration of every output second electrical level is equal to a unit width
When long, counter 217, which counts, adds one；When the stored count value of counter 217 is equal to the second parameter, thermal compensation signal is by the second electricity
Truncation is changed to the first level；When rebuilding synchronous control signal and corresponding to the failing edge of synchronous control signal, thermal compensation signal is by the first electricity
Truncation is changed to second electrical level.By being exported after logic sum gate (OR gate) operation between thermal compensation signal and reconstruction control signal.It mends
First parameter of the signal for compensated reconstruction synchronous control signal is repaid, so that rebuilding the first parameter of synchronous control signal and same
First parameter of step control signal is equal.Wherein, thermal compensation signal is pulse signal.In the present embodiment, the arteries and veins of thermal compensation signal
Rush the pulse width that width is less than synchronous control signal.
Step S806, signal processing module 23 is according to image data, compensated reconstruction synchronous control signal and non-week
The synchronous control signal of phase property generates grid control signal and source control signal.
The sequential control circuit of above-mentioned display device, by simulate externally input periodic synchronous control signal and
Internal voluntarily generate rebuilds synchronous control signal, and the pin for preventing system noise from scurrying into sequential control circuit causes received synchronization
It controls signal and generates mutation, and then ensured the stability of sequential control circuit work.
Those skilled in the art it should be appreciated that more than embodiment be intended merely to illustrate the present invention,
And be not used as limitation of the invention, as long as within spirit of the invention, it is to the above embodiments
Appropriate change and variation are all fallen within the scope of protection of present invention.
Claims (20)
1. a kind of display device, including display driving system and image processing system；The display driving system includes timing
Control circuit, scan drive circuit and data drive circuit；It is defeated that the sequential control circuit receives described image processing system
Image data, clock signal and synchronous control signal out, and grid control signal is generated to control the turntable driving electricity
Road and source control signal are to control the data drive circuit；It is characterized by: the sequential control circuit further includes signal
Rebuild module and signal processing module；The signal reconstruction module detects synchronous control signal in the initial stage to obtain at least
One parameter simultaneously regenerates reconstruction synchronous control signal, at least one described ginseng according at least one described parameter with counting mode
Number can characterize the cycle information of the synchronous control signal without noise signal；The signal processing module receives image data
And the reconstruction synchronous control signal, and generate the grid control signal and the source control signal.
2. display device as described in claim 1, it is characterised in that: the synchronous control signal includes by the first level and
The pulse signal that two level periods are alternately constituted, an at least parameter include characterizing the synchronous control signal in initial rank
First parameter of the quantity in any one frame time of section in the first level state, utilizes first parameter and the timing
The crystal oscillator pulse width of control circuit itself can define the pulse width of first level in a cycle.
3. display device as claimed in claim 2, it is characterised in that: the signal reconstruction module includes computing unit and reconstruction
Unit；The synchronous control signal monitors and first parameter is calculated the computing unit based on the received；It is described heavy
It builds unit and generates initial pulse by starting point of the rising edge of the synchronous control signal, the failing edge with the initial pulse is
Point the first level of output simultaneously starts counting, and stops the first level of output when stored count value is equal to first parameter and generates
Second electrical level forms failing edge.
4. display device as claimed in claim 2, it is characterised in that: an at least parameter further comprises that characterization is periodical
Second parameter of quantity of the synchronization signal in any one frame time of initial stage in second electrical level state, utilizes described the
Two parameters and the crystal oscillator pulse width of the sequential control circuit itself can define the second electrical level in a cycle
Pulse width.
5. display device as claimed in claim 2, it is characterised in that: the signal reconstruction module also monitors the synchronously control
Simultaneously the second parameter is calculated in signal；The signal reconstruction module, which detects the reconstruction synchronous control signal, whether there is exception simultaneously
The reconstruction synchronous control signal deposit when abnormal according to second parameter generate thermal compensation signal, by the thermal compensation signal with
Output is to the signal processing module after the reconstruction control signal carries out logical operation.
6. display device as claimed in claim 5, it is characterised in that: the signal reconstruction module reconstruction is synchronous to be controlled
Whether the failing edge of signal processed corresponds to the first level of the synchronous control signal；If the decline for rebuilding synchronous control signal
Along it is corresponding be the synchronous control signal the first level, the reconstruction unit generates the compensation according to second parameter
Signal；When the thermal compensation signal corresponds to the first level of synchronous control signal where the failing edge for rebuilding synchronous control signal
In second electrical level, it is switched in the counting again of the counter and when count value is equal to second parameter by second electrical level
First level, and switched when the reconstruction synchronous control signal corresponds to the failing edge of the synchronous control signal by the first level
For second electrical level.
7. display device as claimed in claim 6, it is characterised in that: the thermal compensation signal and the reconstruction synchronous control signal
Carry out logic sum gate operation.
8. display device as claimed in any one of claims 1 to 7, it is characterised in that: the initial stage is the display
The booting of device power on after a following predetermined period, one immediately that carries out after the completion of Electro-static Driven Comb of the display device it is pre-
Any one period in timing section.
9. display device as claimed in claim 8, it is characterised in that: when a length of four frame of the predetermined period.
10. display device as described in claim 1, it is characterised in that: the synchronous control signal is data enable signal.
11. a kind of sequential control circuit receives the image data, clock signal and multiple synchronous controls of image processing system output
Signal processed, and grid control signal is generated to control scan drive circuit and source control signal to control data drive circuit；
It is characterized by: the sequential control circuit includes signal reconstruction module and signal processing module；The signal reconstruction module exists
Synchronous control signal is detected when the initial stage to obtain at least one parameter and according at least one described parameter with counting mode
Regeneration rebuilds synchronous control signal, at least one described parameter can characterize the synchronous control signal without noise signal
Cycle information；The signal processing module receives image data and the reconstruction synchronous control signal, and generates the grid control
Signal processed and the source control signal.
12. sequential control circuit as claimed in claim 11, it is characterised in that: the synchronous control signal includes by the first electricity
The pulse signal that gentle second electrical level is periodically alternately constituted, an at least parameter include characterizing the synchronous control signal to exist
First parameter of the quantity in any one frame time of initial stage in the first level state, utilizes first parameter and institute
The crystal oscillator pulse width for stating sequential control circuit itself can define the pulse width of first level in a cycle.
13. sequential control circuit as claimed in claim 12, it is characterised in that: the signal reconstruction module includes computing unit
And reconstruction unit；The synchronous control signal monitors and first parameter is calculated the computing unit based on the received；
The signal reconstruction module generates initial pulse by starting point of the rising edge of the synchronous control signal, with the initial pulse
Failing edge is that starting point exports the first level and starts counting, and stops output first when stored count value is equal to first parameter
Level simultaneously generates second electrical level formation failing edge.
14. sequential control circuit as claimed in claim 12, it is characterised in that: an at least parameter further comprises characterization
Second parameter of quantity of the periodic synchronization signal in any one frame time of initial stage in second electrical level state, utilizes
Second parameter and the crystal oscillator pulse width of the sequential control circuit itself can define described second in a cycle
The pulse width of level；Simultaneously second parameter is calculated in synchronous control signal described in the signal reconstruction module monitors；Institute
Signal reconstruction module is stated to detect the reconstruction synchronous control signal with the presence or absence of exception and deposit in the reconstruction synchronous control signal
Thermal compensation signal is generated according to second parameter when abnormal, the thermal compensation signal and reconstruction control signal are subjected to logic
Output is to the signal processing module after operation.
15. sequential control circuit as claimed in claim 14, it is characterised in that: the signal reconstruction module reconstruction
Whether the failing edge of synchronous control signal corresponds to the first level of the synchronous control signal；If the reconstruction synchronous control signal
Failing edge it is corresponding be the synchronous control signal the first level, the reconstruction unit according to second parameter generate institute
State thermal compensation signal；The thermal compensation signal corresponds to the first of synchronous control signal where the failing edge for rebuilding synchronous control signal
Second electrical level is in when level, by second electrical level in the counting again of the counter and when count value is equal to second parameter
It is switched to the first level, and when the reconstruction synchronous control signal corresponds to the failing edge of the synchronous control signal by the first electricity
Truncation is changed to second electrical level.
16. sequential control circuit as claimed in claim 15, it is characterised in that: thermal compensation signal control synchronous with the reconstruction
Signal processed carries out logic sum gate operation.
17. a kind of signal reconstruction method, in the sequential control circuit of display device；The sequential control circuit receives image
Image data, clock signal and the multiple synchronous control signals of system output；Wherein, the multiple synchronous control signal includes
At least one periodic synchronization signal and acyclic synchronization signal；The signal reconstruction method includes the following steps:
Synchronous control signal is detected in the initial stage to obtain at least one parameter；
Initial pulse is generated according to the periodic synchronous control signal；
It is regenerated according at least one described parameter with counting mode and rebuilds synchronous control signal, at least one described parameter can
Characterize the cycle information of the synchronous control signal without noise signal；
Grid control signal and source control signal are generated according to described image data and the reconstruction synchronous control signal.
18. signal reconstruction method as claimed in claim 17, it is characterised in that: an at least parameter includes that characterization is described same
First parameter of quantity of the step control signal in any one frame time of initial stage in the first level state；The basis
The step of periodic synchronous control signal generates initial pulse further comprises:
Initial pulse is generated by starting point of the rising edge of the synchronous control signal, using the failing edge of the initial pulse as starting point
It exports first level for rebuilding synchronization signal and starts counting；
Stop the first level of output when stored count value is equal to first parameter and generate described to rebuild the of synchronization signal
Two level simultaneously form failing edge.
19. signal reconstruction method as claimed in claim 18, it is characterised in that: an at least parameter further comprises characterization
Second parameter of quantity of the periodic synchronization signal in any one frame time of initial stage in second electrical level state；Tired
Meter count value stops the first level of output and generates the second electrical level for rebuilding synchronization signal simultaneously when being equal to first parameter
The step of forming failing edge further comprises:
The reconstruction synchronous control signal is detected with the presence or absence of abnormal；
If the reconstruction synchronous control signal has exception, thermal compensation signal is generated according to second parameter；
The thermal compensation signal and the reconstruction synchronous control signal are subjected to logic sum gate operation to obtain compensated rebuild together
Step control signal；
Grid control signal and source electrode control are generated according to described image data and the compensated reconstruction synchronous control signal
Signal.
20. signal reconstruction method as claimed in claim 19, it is characterised in that: the thermal compensation signal is rebuilding synchronously control letter
Number failing edge where place be in second electrical level when corresponding to the first level of synchronous control signal, in the meter again of the counter
The first level is switched to by second electrical level when several and count value is equal to second parameter, and in the reconstruction synchronous control signal
Second electrical level is switched to by the first level when the failing edge of the corresponding synchronous control signal.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110262343A (en) * | 2019-06-21 | 2019-09-20 | 新里程医用加速器(无锡)有限公司 | Real-time communication network for clinac control system |
| CN110969971A (en) * | 2019-12-06 | 2020-04-07 | Tcl华星光电技术有限公司 | Display device |
| CN111629119A (en) * | 2020-05-06 | 2020-09-04 | 深圳市爱协生科技有限公司 | MIPI data processing method, device, storage medium and display terminal |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110423A (en) * | 2009-12-28 | 2011-06-29 | 乐金显示有限公司 | Liquid crystal display and method for initializing field programmable gate array |
| CN104581134A (en) * | 2013-10-24 | 2015-04-29 | 深圳艾科创新微电子有限公司 | Video signal resolution detection device and method |
| KR20160033816A (en) * | 2014-09-18 | 2016-03-29 | 삼성디스플레이 주식회사 | Timing controller, organic light emitting display device having the same, and method for driving the organic light emitting display device |
| KR20160047678A (en) * | 2014-10-22 | 2016-05-03 | 엘지디스플레이 주식회사 | Data enable signal generation method, timing controller, and display device |
| CN106057115A (en) * | 2015-04-17 | 2016-10-26 | 三星显示有限公司 | Display apparatus |
| CN106875882A (en) * | 2015-12-14 | 2017-06-20 | 乐金显示有限公司 | Display device and its power integrated circuit control method |
-
2017
- 2017-08-30 CN CN201710765651.3A patent/CN109427276B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110423A (en) * | 2009-12-28 | 2011-06-29 | 乐金显示有限公司 | Liquid crystal display and method for initializing field programmable gate array |
| CN104581134A (en) * | 2013-10-24 | 2015-04-29 | 深圳艾科创新微电子有限公司 | Video signal resolution detection device and method |
| KR20160033816A (en) * | 2014-09-18 | 2016-03-29 | 삼성디스플레이 주식회사 | Timing controller, organic light emitting display device having the same, and method for driving the organic light emitting display device |
| KR20160047678A (en) * | 2014-10-22 | 2016-05-03 | 엘지디스플레이 주식회사 | Data enable signal generation method, timing controller, and display device |
| CN106057115A (en) * | 2015-04-17 | 2016-10-26 | 三星显示有限公司 | Display apparatus |
| CN106875882A (en) * | 2015-12-14 | 2017-06-20 | 乐金显示有限公司 | Display device and its power integrated circuit control method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110262343A (en) * | 2019-06-21 | 2019-09-20 | 新里程医用加速器(无锡)有限公司 | Real-time communication network for clinac control system |
| CN110969971A (en) * | 2019-12-06 | 2020-04-07 | Tcl华星光电技术有限公司 | Display device |
| CN111629119A (en) * | 2020-05-06 | 2020-09-04 | 深圳市爱协生科技有限公司 | MIPI data processing method, device, storage medium and display terminal |
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| Publication number | Publication date |
|---|---|
| CN109427276B (en) | 2021-07-09 |
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