TWI646522B - Display system and application processor for portable device - Google Patents

Abstract

An application processor of a display system of a portable device for displaying image data on a display panel, the application processor comprising: a controller configured to obtain a frequency of a data transmission timing control signal received from a display driver integrated circuit Generating a frequency control signal for adjusting a frequency associated with an operational clock signal of the display driver integrated circuit based on the obtained frequency; a transmitter configured to generate the frequency control signal Transmitting to the display driver integrated circuit; and frequency calculation circuit, comprising: a detector configured to receive the data transmission timing control signal from the display driver integrated circuit; and a frequency calculator configured The frequency of the received data transmission timing control signal is calculated.

Description

Display system of portable device and application processor [Cross-Reference to Related Applications]

This application claims the benefit of U.S. Provisional Patent Application No. 61/845,183, filed on Jul. 11, 2013, and claims the Korean Patent Application No. 10-2013, filed on the Korean Intellectual Property Office (KIPO) on October 8, 2013. Priority of -0120011, and the priority of Korean Patent Application No. 10-2014-0080512, filed on June 30, 2014 in the Korean Intellectual Property Office (KIPO), each of which is incorporated herein by reference. The entire contents of this disclosure are hereby incorporated by reference.

An apparatus and method according to an exemplary embodiment is related to a host, and more particularly, to an operation of controlling a display driver IC based on a data transfer timing control signal output from a display driver integrated circuit (IC). A host of frequencies of clock signals, a system including the host, and a method of operating the system.

A mobile device including a liquid crystal display (LCD) panel drives the LCD panel in various modes, including video mode or command mode. The Mobile Industry Processor Interface Display Serial Interface (MIPI® DSI) is a prior art display standard for portable electronic devices.

MIPI supports two display modes, namely, video mode and command mode. In the command mode, the start of picture data transmission from the host is controlled by a tearing effect (TE) signal. In the video mode, the picture data is transferred from the host to the panel in real time.

When a still image is displayed on the display panel, the display driver IC periodically reads the still image from the picture buffer included in the display driver IC, and displays the still image on the display panel, which is called the panel self-renew (self -refresh). At this time, the display driver IC performs the panel self-renew using the clock signal output from the resistor-capacitor (RC) oscillator. Because the RC oscillator is sensitive to temperature changes, the frequency of the clock signal may vary. This deviation causes electromagnetic interference (EMI), which can interfere with the operating frequency of other devices such as touch screens, styluses, and the like.

When the display driver IC transmits the TE signal to the host in the command mode, the host transmits the picture data to the display driver IC based on the TE signal. The TE signal is used to prevent tearing or tearing of the screen. Tearing or screen tearing is displayed when image data corresponding to at least two different images are simultaneously displayed on a single screen on the display panel The current visual artifacts.

One or more exemplary embodiments may overcome the above disadvantages and other disadvantages not described above. However, it should be understood that one or more exemplary embodiments are not required to overcome the disadvantages described above, and may not overcome any of the problems described.

According to an aspect of the exemplary embodiments, a display driver integrated circuit (DDI) for driving display of image data on a display panel is provided, the DDI comprising: a control signal generator configured Generating a control signal based on the operational clock signal and transmitting the generated control signal to an external device; the receiver being configured to receive the first frequency from the external device in response to the transmitted control signal a control signal; and a controller configured to output a second frequency control signal based on the received first frequency control signal to adjust a frequency associated with the operational clock signal.

The control signal can be a tear effect signal, and the receiver can be configured to receive the image data from the external device in response to the transmitted control signal.

The DDI can further include an oscillator configured to output the operational clock signal to the control signal generator, wherein the controller can be configured to output the second frequency control signal to the The oscillator is tuned to adjust the frequency of the operational clock signal.

The controller can be configured to output the second frequency control signal to The control signal generator; and the control signal generator is configurable to adjust a frequency of the generated control signal based on the outputted second frequency control signal and the operational clock signal.

The control signal generator can be configured to adjust the resulting of the generated control signal based on a ratio between a biased frequency of the operational clock signal and the frequency of the generated control signal frequency.

The receiver can be a Mobile Industry Processor Interface (MIPI) receiver.

The DDI can further include: an image processor configured to output the image material to the display panel, wherein the processor can be configured to respond to the transmitted control signal from the The external device receives the image data.

The DDI can further include: a picture buffer configured to buffer the image material, wherein the controller can be configured to control writing the received image data to the picture buffer, and And controlling the read image data from the picture buffer to be output to the display panel according to the operation clock signal.

In accordance with an aspect of another exemplary embodiment, an application processor of a display system of a portable device that displays image data on a display panel is provided, the application processor including: a controller configured to obtain a self-display driver a data received by the integrated circuit (DDI) transmits a frequency of the timing control signal, and based on the obtained frequency, generates a frequency control signal for adjusting a frequency associated with the operational clock signal of the DDI; Transmitting the generated frequency control signal to the DDI; and frequency calculation circuitry, comprising: a detector configured to self-described The DDI receives the data transmission timing control signal; and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal.

The frequency calculator can be configured to output the calculated frequency to the controller.

The frequency calculation circuit may further include: a frequency comparator configured to determine whether the calculated frequency is within a predetermined operating frequency range of the DDI, generate a control signal according to the determination, and generate the generated signal The control signal is output to the controller.

The frequency comparator may generate a first control signal in response to the calculated frequency being lower than the predetermined operating frequency range, and generate a second control in response to the calculated frequency being within the predetermined operating frequency range And generating a third control signal as the control signal in response to the calculated frequency being higher than the predetermined operating frequency range.

The frequency calculation circuit can further include: a frequency counter configured to determine a count value of a period of the received data transmission timing control signal based on the reference clock signal, wherein the frequency calculator can be configured to be based on The frequency of the received data transmission timing control signal is calculated by the determined count value.

The detector can include an edge detector configured to detect the received data transmission timing control signal based on the received rising edge or falling edge of the data transmission timing control signal cycle.

The frequency calculation circuit can further include: a frequency divider configured to divide the reference clock signal by a predetermined factor, wherein the frequency counter can The configuration is configured to determine the count value based on the divided reference clock signal.

In accordance with an aspect of another exemplary embodiment, a method of controlling a frequency of an operational clock signal of a display, the method comprising: receiving a signal from a display driver integrated circuit (DDI) by a host; based on a reference clock signal Calculating a frequency of the received signal; generating a frequency control signal for adjusting a frequency associated with an operational clock signal of the DDI based on the calculated frequency; and transmitting the generated frequency control signal to The DDI.

The generating the frequency control signal can include generating the frequency control signal in response to the calculated frequency being outside a predetermined operating frequency range of the DDI.

The method can further include transmitting image data to the DDI in response to the received signal, wherein the received signal is a tear effect signal.

The calculating the frequency may include determining a count value of a period of the received signal based on the reference clock signal; and calculating the frequency of the received signal based on the determined count value .

According to another aspect of an exemplary embodiment, there is provided a method of controlling a frequency of an operation clock signal of a display, the method comprising: generating a control signal based on an operation clock signal by DDI; transmitting the generated control signal Receiving a first frequency control signal from the host in response to the transmitted control signal; and adjusting a frequency of the control signal based on the received first frequency control signal.

The adjusting the frequency of the control signal may include adjusting the The frequency of the control signal is adjusted by operating the frequency of the clock signal.

The adjusting the frequency of the control signal can include adjusting the frequency of the control signal based on a ratio between a frequency of the deviation of the operational clock signal and the frequency of the control signal.

The control signal can be a tear effect signal.

In accordance with an aspect of another exemplary embodiment, a display system for displaying image data is provided, the display system comprising: an application processor, comprising: a first controller configured to obtain a display driver product from a frequency calculation circuit a frequency of a signal provided by a body circuit (DDI), and based on the obtained frequency, a first frequency control signal for adjusting a frequency associated with an operational clock signal of the DDI, and a transmitter configured to Transmitting the generated first frequency control signal to the DDI; the frequency calculation circuit configured to receive the signal from the DDI, calculate a received signal based on a reference clock signal a frequency, and providing the calculated frequency to the first controller; and the DDI configured to drive display of the image material on a display panel, the DDI comprising: a control signal generator Configuring to generate the signal based on the operational clock signal and to provide the generated signal to the application processor and the frequency calculation circuit; a receiver, Configuring to receive the first frequency control signal from the application processor in response to the provided signal; and a second controller configured to output based on the received first frequency control signal A second frequency control signal is to adjust the frequency associated with the operational clock signal.

The display system can be a portable device, and the application processor can be a host.

The display system can further include the display panel, the display panel including a touch screen configured to receive input from a stylus.

The signal can be a tear effect signal.

The DDI can include an oscillator configured to output the operational clock signal, wherein the DDI can be configured to adjust a frequency of the operational clock signal in accordance with the second frequency control signal.

The DDI can be configured to adjust the frequency of the generated signal based on the second frequency control signal and the operational clock signal.

The DDI can be configured to adjust the frequency of the generated signal based on a ratio between a biased frequency of the operational clock signal and the frequency of the generated signal.

In accordance with an aspect of another exemplary embodiment, an application processor of a display system of a portable device that displays image data on a display panel is provided, the application processor including: a controller configured to obtain a self-display driver a frequency of a signal received by the integrated circuit (DDI), and based on the obtained frequency, generating a frequency control signal for adjusting a frequency associated with an operational clock signal of the DDI; and a transmitter configured to The generated frequency control signal is transmitted to the DDI.

The received signal can be a tearing effect signal, and the controller can be configured to control the transmitter to transmit the image data to the DDI in response to the received tearing effect signal .

The controller can be configured to generate the frequency control signal in response to the obtained frequency being outside a predetermined operating frequency range of the DDI.

The application processor can further include: a frequency calculation circuit configured to receive the signal from the DDI and calculate the frequency of the received signal based on a reference clock signal, wherein the controller can The frequency control signal is configured to generate based on the calculated frequency.

The frequency calculation circuit can include a frequency counter configured to determine a count value of a period of the received signal based on the reference clock signal, and a frequency calculator configured to be based on the determined The frequency of the received signal is calculated by counting the value.

The frequency calculation circuit can further include an edge detector configured to detect the period of the received signal based on the received rising edge or falling edge of the signal.

The frequency calculation circuit can further include: a frequency divider configured to divide the reference clock signal by a predetermined factor; and the frequency counter can be configured to be based on the divided reference clock A signal is used to determine the count value.

The frequency calculation circuit may further include: a frequency comparator configured to determine whether the calculated frequency is within a predetermined operating frequency range of the DDI, and outputting a control signal to the control according to the determining And the controller may generate the frequency control signal according to the outputted control signal.

The frequency comparator may output a first interrupt signal in response to the calculated frequency being less than the predetermined operating frequency range, and responsive to the calculated frequency The rate is greater than the predetermined operating frequency range and outputs a third interrupt signal as the control signal, and the controller may generate the frequency control signal in response to the outputted first interrupt signal or the output The third interrupt signal adjusts the frequency.

The controller can be a CPU.

The controller can be an image processing circuit.

10‧‧‧ interface

11‧‧‧ interface

11a‧‧‧ exclusive transmission line

12‧‧‧ interface

100, 100A, 100B, 100C‧‧‧ systems

200, 200A, 200B‧‧‧ host

201‧‧‧ busbar

210‧‧‧Central Processing Unit

220‧‧‧Read-only memory

230‧‧‧ memory controller

240‧‧‧ camera interface

250, 250A, 250B, 250C, 250D, 250E, 250F‧‧‧ frequency calculation circuit

251‧‧‧Edge detector

252‧‧‧Edge detection circuit

252-1‧‧‧ and gate

252-2‧‧‧Inverter

252-3‧‧‧Edge detector

253‧‧‧divider

255‧‧‧frequency counter

256‧‧‧frequency calculator

257‧‧‧ frequency comparison circuit

260‧‧‧Image Processing Circuit

270, 270A‧‧‧ transmission interface

290‧‧" interface

300, 300A, 300B‧‧‧ display driver integrated circuit

310, 310A‧‧‧ receiving interface

320, 320A, 320B‧‧‧ control circuit

325‧‧‧ Picture buffer

330‧‧‧Oscillator

340, 340A‧‧‧ timing controller

342‧‧‧Sequence Control Signal Generator

344‧‧‧Image Processing Circuit

350‧‧‧Drive Circuit Blocks

400‧‧‧ display panel

500‧‧‧External memory

600‧‧‧ camera

700‧‧‧Frequency calculation integrated circuit

CLK‧‧‧ exclusive clock signal

CNT‧‧‧ count value

DET‧‧‧Detection signal

DTE‧‧‧ operation results

Fcnt, fcnt1, fcnt2, fcnt3‧‧‧ frequency

Fref, frefd‧‧‧ reference clock signal

FTF, FTFa‧‧‧ second cycle

FW‧‧‧ frequency window

HCLK‧‧‧ clock signal

HIW, HIWa‧‧‧ high cycle width

Ifc‧‧‧ internal clock signal

INT‧‧‧ interrupt

LIW, LIWa‧‧‧Low cycle width

RTR, RTRa‧‧‧ first cycle

S110, S120, S130, S140‧‧‧ operations

TE‧‧‧ data transmission timing control signal

X-OSC‧‧‧ crystal oscillator

The above and other features and advantages of the present invention will become more apparent from the detailed description of the exemplary embodiments.

FIG. 1 is a block diagram of a system in accordance with an exemplary embodiment.

2 is a block diagram of a frequency calculation circuit in accordance with an exemplary embodiment.

FIG. 3 is a block diagram of a frequency calculation circuit in accordance with another exemplary embodiment.

4 is a timing diagram of the operation of a frequency calculation circuit, in accordance with an exemplary embodiment.

5A and 5B are timing diagrams of operations of a frequency calculation circuit, in accordance with another exemplary embodiment.

FIG. 6 is a block diagram of a frequency calculation circuit in accordance with still another exemplary embodiment.

Figure 7 is a timing diagram of the operation of the frequency calculation circuit illustrated in Figure 6.

FIG. 8 is a block diagram of a frequency calculation circuit in accordance with still another exemplary embodiment.

FIG. 9 is a block diagram of a frequency calculation circuit in accordance with another exemplary embodiment.

FIG. 10 is a timing chart showing the operation of the frequency calculation circuit illustrated in FIG.

11 is a block diagram of a frequency calculation circuit in accordance with yet another exemplary embodiment.

12 is a flow chart of a method of operating a system, in accordance with an illustrative embodiment.

FIG. 13 is a block diagram of a system in accordance with another exemplary embodiment.

Figure 14 is a block diagram of a system in accordance with yet another exemplary embodiment.

Figure 15 is a block diagram of a system in accordance with yet another exemplary embodiment.

The illustrative embodiments are described more fully hereinafter with reference to the drawings. However, the illustrative embodiments may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these illustrative embodiments are provided so that this disclosure will be thorough and complete, and the scope of the inventive concept will be fully conveyed by those skilled in the art. In the figures, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals indicate like elements throughout.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element or the intervening element can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, the intervening element is absent. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items and can be abbreviated as "/".

It will be understood that, although the terms "first", "second", and the like may be used herein to describe various elements, such elements are not limited by the terms. These terms are used only To distinguish one component from another. For example, a first signal could be referred to as a second signal, and similarly, a second signal could be referred to as a first signal without departing from the teachings of the present disclosure.

The terminology used herein is for the purpose of describing the exemplary embodiments and is not intended to limit the inventive concept. As used herein, the singular and " It is to be understood that the terms "comprises" or "comprises" or "an" The presence or addition of, regions, integers, steps, operations, components, components, and/or groups thereof.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the related art and/or the application, and should not be idealized or overly formal. Meaning is explained unless it is explicitly defined as such.

FIG. 1 is a block diagram of a system 100 in accordance with an illustrative embodiment. Referring to FIG. 1, system 100 includes a host 200, a display driver IC (DDI) 300, a display panel 400, an external memory 500, and a camera 600.

The system 100 can be implemented as a cellular phone, a smart phone, a tablet device, a personal computer (PC), a portable device, a multimedia player, a mobile internet device (MID), and an Internet of Things (Internet of Things, IoT) Devices, Internet of Things (IoE) devices, wearable computers, smart devices, and the like.

For example, when the system 100 supports the Mobile Industry Processor Interface (MIPI®), the System 100 can also support Panel Renewal (PSR). The PSR is an operation of periodically displaying still image data stored in the picture buffer 325 of the DDI 300 on the display panel 400.

In one or more exemplary embodiments, system 100 can support MIPI command mode and/or MIPI video mode (which supports PSR). However, it should be understood that one or more other exemplary embodiments are not limited thereto. For example, in accordance with another exemplary embodiment, system 100 can include an interface that supports an embedded display port (eDP) standard.

The host 200 can receive the data transmission timing control signal TE from the DDI 300, calculate the frequency of the data transmission timing control signal TE using the reference clock signal "fref", and generate a frequency for adjusting the frequency of the operation clock signal of the DDI 300 based on the calculation result. A frequency control signal and outputting the first frequency control signal to the DDI 300.

In addition, whenever image data (eg, still image data or motion picture data) is transmitted to the DDI 300, the host can transmit the image data to the DDI 300 based on or using the transmission timing control signal TE.

In other words, the transmission timing control signal TE controls the transmission timing of the image data from the host 200 to the DDI 300. Therefore, the data transmission timing control signal TE can be a tear effect (TE) signal for use in the MIPI. And, when the host 200 transmits the image data to the DDI 300 in response to the output from the DDI 300 to prevent the specific signal of the TE, The particular signal can be considered to operate as the transmission timing control signal TE, regardless of the type of interface between the host 200 and the DDI 300. Although in the present exemplary embodiment, the host 200 receives the data transmission timing control signal TE (such as a tear effect TE signal), it should be understood that one or more other exemplary embodiments are not limited thereto, and the host 200 is self-DDI 300 receives any signal or control signal, the frequency of which is based on the operational clock signal of the DDI 300.

The host 200 can be implemented as an integrated circuit (IC), a system chip (SoC), a processor, an application processor (AP), a mobile AP, and the like. The host 200 can include a central processing unit (CPU) 210, a read only memory (ROM) 220, a memory controller 230, a camera interface (I/F) 240, a frequency calculation circuit 250, an image processing circuit 260, and a transmission interface. (transmit interface, TX I/F) 270.

The CPU 210 can control the operation of at least one of the components 220, 230, 240, 250, 260, and 270 via the bus bar 201. The CPU 210 can include at least one core. The CPU 210 can execute an operating system (OS) output from the external memory 500 during power-on. According to the control of the OS, the CPU 210 may generate a first frequency control signal for adjusting the frequency of the operation clock signal of the DDI 300, and may transmit the first frequency control signal to the DDI 300 via the TX I/F 270.

In other words, the host 200 can transmit the first frequency control signal to the DDI 300 when it is necessary or determined that the frequency of the operational clock signal of the DDI 300 is to be adjusted. The first frequency control signal can be transmitted to the DDI 300 in the form of a command and can be transmitted to the DDI 300 via a transmission line that transmits the image data.

The ROM 220 can store code and/or data used by the CPU 210.

The memory controller 230 can store data in the external memory 500 and can read data from the external memory 500. For example, the memory controller 230 can be a collection of dynamic random access memory (DRAM) controllers and flash memory controllers. Therefore, the external memory 500 can be a collection of DRAM and flash memory.

The camera I/F 240 can receive image data captured by the camera 600 and transmit the image data to the memory controller 230 and/or the image processing circuit 260. When system 100 supports MIPI, camera 600 and camera I/F 240 can communicate with one another using a camera serial interface (CSI) (eg, CSI-2). Camera 600 can transmit image data to camera I/F 240 using low-voltage differential signaling (LVDS).

The frequency calculation circuit 250 can receive the data transmission timing control signal TE from the DDI 300, and calculate the frequency of the data transmission timing control signal TE using the reference clock signal "fref" associated with the clock signal output from the crystal oscillator X-OSC, and The bus 201 transmits the calculation result to the CPU 210. The CPU 210 can operate as a control circuit by using the calculation result to generate a first frequency control signal for adjusting the frequency of the operation clock signal of the DDI 300.

Although in the present exemplary embodiment, the frequency calculation circuit 250 calculates the frequency fcnt of the data transmission timing control signal TE, it should be understood that in one or more other exemplary embodiments, the CPU 210 may calculate the data transmission timing control signal TE. The frequency fcnt. For example, in this case, the frequency calculation circuit 250 can use the reference clock The period of the data transfer timing control signal TE is counted by the signal fref or frefd, a count value CNT corresponding to the count result is generated, and the count value CNT is supplied to the CPU 210. The CPU 210 can then calculate the frequency fcnt of the data transmission timing control signal TE using the count value CNT.

Although in one or more other exemplary embodiments, host 200 may include an independent control circuit for generating a first frequency control signal, circuitry for generating a control signal for adjusting the frequency of the operational clock signal of DDI 300 is in this document It is called a control circuit (for example, CPU 210).

Image processing circuitry 260 processes and controls the image data and/or command material to be transmitted to DDI 300. The command data contains the first frequency control signal. Image data and/or command data may be transmitted in the form of data packets as defined in MIPI. However, it should be understood that one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, image data and/or command material may be transmitted in accordance with a data format defined in an eDP standard or a high speed serial interface standard.

The TX I/F 270 can communicate with the receive interface (RX I/F) 310 of the DDI 300. The image data and/or command data may be transmitted from the host 200 to the DDI 300 via the image processing circuit 260 and the TX I/F 270. The TX I/F 270 can transmit image data using a fref or fref-based clock signal associated with the clock signal fref output from the crystal oscillator X-OSC.

The interface 10 is connected between the host 200 and the DDI 300. For example, interface 10 can be implemented to support MIPI, eDP, high speed serial interface, and the like.

The DDI 300 can be based on image data and/or commands transmitted from the host 200. The image data is processed and the processed image data can be transmitted to the display panel 400. At this time, the DDI 300 can perform the PSR using the image material stored in the picture buffer 325.

The DDI 300 can adjust the frequency of the operational clock signal of the DDI 300 in response to the first frequency control signal transmitted from the host 200. The frequency at which the clock signal is operated may be the frequency of each of the various operational clock signals used for operation of DDI 300.

For example, the operational clock signal can be an internal clock signal "ifc" output from oscillator 330 implemented in DDI 300. At this time, the internal clock signal ifc of the oscillator 330 can participate in the generation of the data transmission timing control signal TE and the generation of the control signal for the PSR. The DDI 300 can be implemented as an action DDI. The DDI 300 includes an RX I/F 310, a control circuit 320, a picture buffer 325, an oscillator 330, a timing controller 340, and a drive circuit block 350.

The RX I/F 310 can convert image data and/or command data transmitted from the TX I/F 270 of the host 200 into a format suitable for the DDI 300. For example, when the RX I/F 310 supports the MIPI, the RX I/F 310 can transmit the clock signal received via the interface 10 to the control circuit 320, and can use the clock signal from the image data (eg, data packet). Resume data, data enable signals, and sync signals (for example, vertical sync signals and horizontal sync signals).

Control circuit 320 can control the operation of picture buffer 325, oscillator 330, and/or timing controller 340 based on one or more control signals output from RX I/F 310.

In one or more exemplary embodiments, when RX I/F 310 is received for control When the DDI 300 operates the first frequency control signal (or command) of the frequency of the clock signal and outputs it to the control circuit 320, the control circuit 320 can generate the second frequency control signal based on the first frequency control signal. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command. The oscillator 330 can adjust (eg, increase or decrease) the frequency of the internal clock signal ifc in response to the second frequency control signal.

At this time, the timing control signal generator 342 can adjust the frequency of the data transmission timing control signal TE using the frequency-adjusted internal clock signal ifc, and can output the data transmission timing control signal TE whose frequency has been adjusted to the host 200.

In one or more other exemplary embodiments, when the RX I/F 310 receives the first frequency control signal for controlling the frequency of the operation clock signal of the DDI 300 and outputs it to the control circuit 320, the control circuit 320 may The timing control signal generator 342 is controlled directly using the second frequency control signal associated with the first frequency control signal. For example, in this case, the control circuit 320 can control the timing control signal generator 342 to adjust (for example, increase or increase) by adjusting the ratio between the frequency of the internal clock signal ifc and the frequency of the data transmission timing control signal TE. The frequency of the data transmission timing control signal TE is reduced, and the oscillator 330 does not adjust (eg, increase or decrease) the frequency of the internal clock signal ifc. Here, the ratio may be stored in, for example, a register of the timing control signal generator 342. For example, in this case, if the frequency of the internal clock signal ifc is different from the original frequency, the two-state thixotropic cycle of the data transmission timing control signal TE can be adjusted (for example, from every 8 cycles) a cyclic data transmission timing control signal TE in the internal clock signal The ratio is adjusted by adjusting the data transmission timing control signal TE) of one cycle of the internal clock signal every 16 cycles.

According to another exemplary embodiment, the oscillator 330 may use a second frequency control signal to adjust (eg, increase or decrease) the frequency of the internal clock signal ifc, and the control circuit 320 may directly control using the second frequency control signal. Timing control signal generator 342. For example, in this case, the control circuit 320 can control the timing control signal generator 342 to adjust the frequency of the adjusted internal clock signal ifc (adjusted by the oscillator 330) to the frequency of the data transmission timing control signal TE. The ratio is adjusted (eg, increased or decreased) by the frequency of the data transmission timing control signal TE.

The timing control signal generator 342 can adjust (eg, increase or decrease) the frequency of the data transmission timing control signal TE in response to the second frequency control signal, and can output the data transmission timing control signal TE whose frequency has been adjusted to Host 200. For example, when DDI 300 supports MIPI, timing control signal generator 342 can be implemented as a TE signal generator.

The control circuit 320 can write the image data received by the RX I/F 310 and output from the RX I/F 310 to the picture buffer 325 using the write control signal. The write control signal is a signal for writing image data to the picture buffer 325. The control circuit 320 can also read the image data from the picture buffer 325 using the read control signal generated according to the internal clock signal ifc of the oscillator 330, and transmit the image data to the image processing circuit included in the timing controller 340. 344.

The image processing circuit 344 processes the image data output from the control circuit 320 using the internal clock signal ifc of the oscillator 330, and will display the image corresponding to the processing result. The display data and the synchronization signals (for example, the vertical synchronization signal, the horizontal synchronization signal, and the data enable signal) of the display data are output to the drive circuit block 350.

The driving circuit block 350 can drive the display material to the display panel 400 according to the display data output from the image processing circuit 344 and the synchronization signal. Moreover, it should be understood that the driver circuit block 350 can include at least one source driver and at least one gate driver. The display panel 400 can be implemented as a thin-film-transistor liquid-crystal display (TFT-LCD) panel, an organic light-emitting diode (OLED) display panel, and an active matrix OLED (active). -matrix organic light-emitting diode, AMOLED) display panel, flexible display panel, LCD panel, and the like.

2 is a block diagram of a frequency calculation circuit 250A, in accordance with an exemplary embodiment. For example, frequency calculation circuit 250A can be implemented as frequency calculation circuit 250 illustrated in FIG. FIG. 4 is a timing diagram of the operation of frequency calculation circuit 250A, in accordance with an exemplary embodiment. Referring to FIG. 2, the frequency calculation circuit 250A includes an edge detector 251, a frequency counter 255, and a frequency calculator 256. The frequency calculation circuit 250A may also include a frequency divider 253.

Referring to the condition I in FIG. 4, the frequency calculation circuit 250A can transmit a specific period of the data transmission timing control signal TE using the reference clock signal fref or frefd (for example, an interval between rising edges (hereinafter, referred to as "first period") )) The RTR counts, and the frequency fcnt of the data transmission timing control signal TE can be calculated using the count value CNT corresponding to the count result.

The edge detector 251 detects in response to the reference clock signal fref or frefd The rising edge of the data transmission timing control signal TE generates a detection signal DET having a pulse waveform, and outputs the data transmission timing control signal TE to the frequency counter 255. The waveform of the detection signal DET may be the same, substantially the same or similar to the waveform of the data transmission timing control signal TE.

The frequency counter 255 can count the first period RTR using the reference clock signal fref or frefd, and generate a count value CNT corresponding to the count result. For example, the frequency counter 255 can count the number of cycles of the reference clock signal fref or frefd in the first period RTR. The frequency calculator 256 can calculate the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and can output the frequency fcnt to the CPU 210. In accordance with one or more exemplary embodiments, frequency counter 255 and frequency calculator 256 may be implemented together in a single circuit, although it should be understood that one or more other illustrative embodiments are not limited thereto.

The frequency counter 255 resets the previous count value in response to the activated detection signal DET, uses the reference clock signal fref or frefd to count the first period RTR, and generates the count value CNT.

The CPU 210 may determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, a central operating frequency range) of the DDI 300, and generate a first frequency control signal based on the determination result. The central operating frequency range can be determined based on the center operating frequency and the deviation. The center operating frequency and deviation can vary with the design specifications of the DDI 300. For example, when the center operating frequency is 60 Hz and the deviation is ±0.2%, the center operating frequency range can be determined to be 59.88 Hz to 60.12 Hz.

The DDI 300 can adjust (eg, increase or decrease) the frequency of the data transmission timing control signal TE based on a second frequency control signal associated with the first frequency control signal generated by the host 200. For example, when the frequency fcnt is not within the central operating frequency range, the host 200 outputs the first frequency control signal to the DDI 300 such that the DDI 300 can be based on the first frequency control signal or based on the first frequency control signal. The second frequency control signal adjusts the frequency of the data transmission timing control signal TE in real time. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command.

In FIG. 4, RTRa represents the first period of the data transmission timing control signal TE having the frequency adjusted by the DDI 300. Since the first period of the data transmission timing control signal TE is adjusted (eg, increased) based on the first frequency control signal generated by the host 200, the first period RTR and RTRa are different from each other, as shown in FIG.

The frequency counter 255 counts the first period RTRa using the reference clock signal fref or frefd, and generates a count value CNT corresponding to the count result. The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the frequency fcnt to the CPU 210. The CPU 210 compares the frequency fcnt with the central operating frequency range and determines whether to generate the first frequency control signal and/or determine the type of the first frequency control signal based on the comparison result (eg, indicating to increase, decrease, or maintain the data transmission timing control signal) TE frequency).

Referring to the situation II in FIG. 4, the frequency calculation circuit 250A can transmit a specific period of the data transmission timing control signal TE using the reference clock signal fref or frefd (for example, the interval between the falling edges (hereinafter, referred to as "second period") )) FTF Counting, and the frequency fcnt of the data transmission timing control signal TE can be calculated using the count value CNT corresponding to the counting result.

The edge detector 251 detects the falling edge of the data transmission timing control signal TE, generates the detection signal DET having the pulse waveform, and outputs the data transmission timing control signal TE to the frequency counter 255. The frequency counter 255 counts the second period FTF using the reference clock signal fref or frefd, and generates a count value CNT. The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the frequency fcnt to the CPU 210.

The CPU 210 may determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, a center operating frequency range) of the DDI 300, and control the generation of the first frequency control signal based on the determination result.

The DDI 300 can adjust the frequency of the data transmission timing control signal TE based on a second frequency control signal associated with the first frequency control signal generated by the host 200. For example, when the frequency fcnt is not within the central operating frequency range, the host 200 outputs the first frequency control signal to the DDI 300, so that the DDI 300 can instantly adjust the data transmission timing control signal TE based on the first frequency control signal. Frequency of.

In FIG. 4, FTFa represents the second period of the data transmission timing control signal TE having the frequency adjusted by the DDI 300. Since the second period of the data transmission timing control signal TE is adjusted (eg, increased) based on the first frequency control signal generated by the host 200, the second periods FTF and FTFa are different from each other, as shown in FIG.

The frequency counter 255 uses the reference clock signal fref or frefd to pair the second The period FTFa is counted and a count value CNT is generated. The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the frequency fcnt to the CPU 210. The CPU 210 compares the frequency fcnt with the center operating frequency range, and determines whether or not the first frequency control signal is generated based on the comparison result.

The frequency divider 253 divides the output clock signal fref of the crystal oscillator X-OSC by a predetermined division factor, and outputs the divided clock signal frefd to the frequency counter 255. Therefore, the reference clock signal can be the output clock signal fref of the crystal oscillator X-OSC or the divided clock signal frefd. The division factor can be determined according to the design specifications of the host 200. It should be understood that the frequency divider 253 may be omitted in one or more other exemplary embodiments.

In the present exemplary embodiment illustrated in FIG. 2, the frequency fcnt of the material transmission timing control signal TE is transmitted to the CPU 210. However, it should be understood that one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, the count value CNT is directly transmitted to the CPU 210. In this case, the CPU 210 can calculate the frequency fcnt of the data transmission timing control signal TE using the count value CNT, determine whether the frequency fcnt is within a predetermined range (for example, a central operating frequency range), and determine whether or not to generate the first based on the determination result. A frequency control signal.

FIG. 3 is a block diagram of a frequency calculation circuit 250B in accordance with another exemplary embodiment. For example, frequency calculation circuit 250B can be implemented as frequency calculation circuit 250 illustrated in FIG. The configuration and operation of the frequency calculation circuit 250B illustrated in FIG. 3 is identical, substantially identical, or similar to the configuration and operation of the frequency calculation circuit 250A illustrated in FIG. 2, except for the frequency comparison circuit 257 (eg, frequency comparator). Figure 5A And FIG. 5B is a timing diagram of the operation of frequency calculation circuit 250B, in accordance with another exemplary embodiment.

Referring to FIGS. 3, 5A and 5B, the frequency comparison circuit 257 can determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, the frequency window FW), and can control the signal according to the determination result (for example, The interrupt INT) is output to the CPU 210. The frequency comparison circuit 257 can function as an interrupt generation circuit that generates an interrupt INT.

The frequency window FW illustrated in Figures 5A and 5B may be substantially the same, substantially the same, or similar to the central operating frequency range of Figures 2 and 4 above. Referring to the condition I in FIGS. 5A and 5B, when the frequency fcnt (=fcnt1) calculated by the frequency calculator 256 is lower than the lower limit of the frequency window FW, the frequency comparison circuit 257 can output the first interrupt INT to the CPU 210. The CPU 210 may generate a first frequency control signal indicating a frequency of increasing the operational clock signal of the DDI 300 in response to the first interrupt INT. Therefore, the DDI 300 can increase the frequency of the data transmission timing control signal TE based on the first frequency control signal.

Referring to the condition II in FIG. 5A, when the frequency fcnt (= fcnt2) calculated by the frequency calculator 256 is between the lower limit and the upper limit of the frequency window FW or within the frequency window FW, the frequency comparison circuit 257 does not set the first interrupt INT. Output to the CPU 210. Meanwhile, referring to the situation II in FIG. 5B, when the frequency fcnt (= fcnt2) calculated by the frequency calculator 256 is between the lower limit and the upper limit of the frequency window FW or within the frequency window FW, the frequency comparison circuit 257 will be the second interrupt. The INT is output to the CPU 210. The CPU 210 may generate an operation clock signal indicating that the DDI 300 is maintained in response to the second interrupt INT. The frequency of the first frequency control signal. In one or more other exemplary embodiments, CPU 210 may not generate a first frequency control signal to cause DDI 300 to maintain the frequency of the data transmission timing control signal TE.

Referring to the situation III in FIGS. 5A and 5B, when the frequency fcnt (=fcnt3) calculated by the frequency calculator 256 is higher than the upper limit of the frequency window FW, the frequency comparison circuit 257 can output the third interrupt INT to the CPU 210. The CPU 210 may generate a first frequency control signal indicating a frequency of reducing the operation clock signal of the DDI 300 in response to the third interrupt INT. Therefore, the DDI 300 can reduce the frequency of the data transmission timing control signal TE based on the first frequency control signal.

FIG. 6 is a block diagram of a frequency calculation circuit 250C in accordance with yet another exemplary embodiment. For example, frequency calculation circuit 250C can be implemented as frequency calculation circuit 250 illustrated in FIG. FIG. 7 is a timing diagram of the operation of the frequency calculation circuit 250C illustrated in FIG. 6. Referring to FIG. 6, the frequency calculation circuit 250C includes an edge detection circuit 252, a frequency counter 255, and a frequency calculator 256. The frequency calculation circuit 250C may also include a frequency divider 253.

Referring to FIGS. 6 and 7, the frequency calculation circuit 250C may count a specific period (for example, a high period width HIW) of the data transmission timing control signal TE using the reference clock signal fref or frefd, and may use a meter corresponding to the count result. The frequency CNT is used to calculate the frequency fcnt of the data transmission timing control signal TE.

The edge detection circuit 252 can include a gate 252-1 and an edge detector 252-3. The gate 252-1 performs an AND operation on the data transmission timing control signal TE and the reference clock signal fref or frefd, and outputs the operation result DTE to the frequency. Counter 255. The edge detector 252-3 can generate the detection signal DET in response to the data transmission timing control signal TE. The edge detection circuit 252 can generate the detection signal DET that is activated in response to the rising edge of the data transmission timing control signal TE. The frequency counter 255 resets the previous count value CNT in response to the activated detection signal DET, and counts the operation result DTE output from the AND gate 252-1 using the reference clock signal fref or frefd, and the output corresponds to the count result. Current count value CNT.

The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the calculated frequency fcnt to the CPU 210. The CPU 210 may determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, a center operating frequency range) of the DDI 300, and control the generation of the first frequency control signal based on the determination result.

The DDI 300 can adjust the frequency of the data transmission timing control signal TE based on a first frequency control signal generated by the host 200 or based on a second frequency control signal of the first frequency control signal. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command.

When the calculated frequency fcnt is outside the center operating frequency range, the host 200 outputs the first frequency control signal to the DDI 300 to cause the DDI 300 to instantaneously adjust the frequency of the data transmission timing control signal TE based on the first frequency control signal.

Referring to Figure 7, HIWa represents the high cycle width of the data transfer timing control signal TE that has been adjusted by the DDI 300. Since the high period width HIW of the data transmission timing control signal TE is adjusted (for example, increased) based on the first frequency control signal generated by the host 200, the high period widths HIW and HIWa are different from each other, as shown in FIG. Show. The high cycle widths HIW and HIWa can be adjusted in line time.

FIG. 8 is a block diagram of a frequency calculation circuit 250D in accordance with yet another exemplary embodiment. For example, frequency calculation circuit 250D can be implemented as frequency calculation circuit 250 illustrated in FIG. The configuration and operation of the frequency calculation circuit 250D illustrated in FIG. 8 may be identical, substantially identical, or similar to the configuration and operation of the frequency calculation circuit 250C illustrated in FIG. 6, except for the frequency comparison circuit 257. The operation of the frequency comparison circuit 257 illustrated in FIG. 8 may be substantially the same, substantially the same as or similar to the operation of the frequency comparison circuit 257 described above with reference to FIGS. 3, 5A, and 5B.

FIG. 9 is a block diagram of a frequency calculation circuit 250E, in accordance with another exemplary embodiment. For example, frequency calculation circuit 250E can be implemented as frequency calculation circuit 250 illustrated in FIG. FIG. 10 is a timing chart showing the operation of the frequency calculation circuit 250E illustrated in FIG. The frequency calculation circuit 250E includes an edge detection circuit 252, a frequency counter 255, and a frequency calculator 256. The frequency calculation circuit 250E may also include a frequency divider 253.

Referring to FIGS. 9 and 10, the frequency calculation circuit 250E can count a specific period (for example, a low period width LIW) of the data transmission timing control signal TE using the reference clock signal fref or frefd, and can calculate the data using the count value CNT. The frequency fcnt of the timing control signal TE is transmitted.

The edge detection circuit 252 can include a AND gate 252-1, an inverter 252-2, and an edge detector 252-3. The inverter 252-2 inverts the data transfer timing control signal TE, and outputs the inverted data transfer timing control signal to the AND gate 252-1 and the edge detector 252-3. And the output signal of the gate 252-1 to the inverter 252-2 is And the reference clock signal fref or frefd performs an AND operation, and outputs the operation result DTE to the frequency counter 255.

The edge detection circuit 252 can generate the detection signal DET that is activated in response to the falling edge of the data transmission timing control signal TE. The frequency counter 255 resets the previous count value CNT in response to the activated detection signal DET, counts the operation result DTE output from the AND gate 252-1 using the reference clock signal fref or frefd, and outputs the count value CNT. The operations of elements 253, 255, and 256 illustrated in FIG. 9 may be identical, substantially identical, or similar to the operations of elements 253, 255, and 256 illustrated in FIG.

Referring to Figure 10, LIWa represents the low cycle width of the data transfer timing control signal TE that has been adjusted by the DDI 300. Since the low cycle width LIW of the material transfer timing control signal TE is adjusted (for example, increased) based on the first frequency control signal generated by the host 200, the low cycle widths LIW and LIWa are different from each other as shown in FIG.

FIG. 11 is a block diagram of a frequency calculation circuit 250F, in accordance with yet another exemplary embodiment. For example, frequency calculation circuit 250F can be implemented as frequency calculation circuit 250 illustrated in FIG. Except for the frequency comparison circuit 257, the configuration and operation of the frequency calculation circuit 250F illustrated in FIG. 11 may be substantially the same or substantially the same as the configuration and operation of the frequency calculation circuit 250E illustrated in FIG. The operation of the frequency comparison circuit 257 illustrated in FIG. 11 may be substantially the same, substantially the same as or similar to the operation of the frequency comparison circuit 257 described above with reference to FIGS. 3, 5A, and 5B.

FIG. 12 is a method of operating system 100 in accordance with an exemplary embodiment. Flow chart. Referring to FIGS. 1 through 12, the host 200 receives the data transfer timing control signal TE from the DDI 300 in operation S110.

In operation S120, the host 200 calculates the frequency fcnt of the data transmission timing control signal TE using the reference clock signal fref or frefd. For example, in operation S120, the frequency calculation circuit 250 of the host 200 counts a specific period of the data transmission timing control signal TE using the reference clock signal fref or frefd, generates a count value CNT, and uses the count value CNT to calculate data. The frequency of the timing control signal TE is transmitted. Although in the present exemplary embodiment, the host 200 calculates the frequency fcnt of the material transmission timing control signal TE (operation S120), it should be understood that one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, the external frequency calculation circuit (ie, external to the host 200) may calculate the frequency fcnt of the data transmission timing control signal TE and transmit the calculated frequency fcnt to the host 200.

In operation S130, the CPU 210 generates a first frequency control signal for adjusting the frequency of the material transmission timing control signal TE based on the calculated frequency fcnt, and transmits the first frequency control signal to the DDI 300.

The DDI 300 adjusts the frequency of the internal clock signal ifc of the oscillator 330 based on the second frequency control signal corresponding to the first frequency control signal transmitted from the host 200. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command. In operation S140, the DDI 300 adjusts the frequency of the data transmission timing control signal TE based on the second frequency control signal. The DDI 300 transmits the data transmission timing control signal TE whose frequency has been adjusted to the host 200. As described above, the operation clock signal of the DDI 300 (for example, an internal clock) The frequency of the signal ifc) is adjusted such that the DDI 300 performs the PSR using an operational clock signal having an adjusted frequency.

FIG. 13 is a block diagram of a system 100A in accordance with another exemplary embodiment. Referring to FIG. 13, system 100A includes a host 200A, a DDI 300A, a display panel 400, an external memory 500, and a camera 600. Except for the TX I/F 270A and the frequency calculation circuit 250, the structure and operation of the host 200A illustrated in FIG. 13 may be substantially the same or substantially the same as the structure and operation of the host 200 illustrated in FIG.

In addition to the clock signal for transmission of the image data, the host 200A also transmits the dedicated clock signal CLK to the DDI 300A via the dedicated transmission line 11a. In other words, the interface 11 includes a transmission line for transmission of a clock signal, a transmission line for transmission of image data, and a dedicated transmission line 11a for transmission of the dedicated clock signal CLK. When the interface 11 supports MIPI or eDP, the interface 11 further includes a dedicated transmission line 11a for transmission of the dedicated clock signal CLK.

The DDI 300A can use the dedicated clock signal CLK as an operation clock signal. In the present exemplary embodiment, DDI 300A does not include an oscillator. The dedicated clock signal CLK does not care about program changes, voltage changes, and/or temperature changes.

The RX I/F 310A of the DDI 300A recovers the data, the data enable signal, and the sync signal from the image data using the clock signal, and transmits the clock signal to the control circuit 320A. The RX I/F 310A also transmits the dedicated clock signal CLK to the control circuit 320A.

During the write operation, control circuit 320A writes the recovered data to picture buffer 325 using the clock signal and the write control signal. During the read operation period The control circuit 320A reads the data (e.g., recovered data) from the picture buffer 325 using the dedicated clock signal CLK and the read control signal and transmits the read data to the image processing circuit 344. The read control signal can be generated using the dedicated clock signal CLK.

The timing control signal generator 342 of the timing controller 340A generates a material transmission timing control signal TE using the dedicated clock signal CLK, and transmits the material transmission timing control signal TE to the host 200A. The TX I/F 270A transmits the image data to the DDI 300A based on the data transmission timing control signal TE.

The image processing circuit 344 of the timing controller 340A processes the material output from the control circuit 320A using the dedicated clock signal CLK, and transmits the display material corresponding to the processing result to the driving circuit block 350. As described above, the DDI 300A processes the image data transmitted from the host 200A by using the dedicated clock signal CLK transmitted from the host 200A via the dedicated transmission line 11a as an operation clock signal.

FIG. 14 is a block diagram of a system 100B in accordance with yet another exemplary embodiment. The system 100B includes a host 200A, a DDI 300B, a display panel 400, an external memory 500, and a camera 600. In addition to the frequency calculation circuit 250, the structure and operation of the host 200A illustrated in FIG. 14 may be substantially the same or similar to the structure and operation of the host 200 illustrated in FIG.

During operation of system 100B, host 200A continuously (eg, always) transmits clock signal HCLK to DDI 300B. The DDI 300B uses the clock signal CLK associated with the clock signal HCLK as the operational clock signal, and the DDI 300B does not include the oscillator. At this time, the frequency of the clock signal HCLK is higher than the clock signal CLK. Frequency of. The clock signal HCLK can be a MIPI clock signal. When system 100B operates in the MIPI command mode, host 200A continually provides a clock signal to DDI 300B.

The clock signal HCLK does not care about program changes, voltage variations, and/or temperature variations of the DDI 300B. The RX I/F 310B of the DDI 300B recovers the data, the data enable signal, and the sync signal from the image data using the clock signal HCLK, and transmits the clock signal HCLK to the control circuit 320B.

During the write operation, the control circuit 320B writes the recovered data to the picture buffer 325 using the clock signal HCLK and the write control signal. During a read operation, control circuit 320B reads data (eg, recovered data) from picture buffer 325 using clock signal CLK and read control signals and transmits the read data to image processing circuit 344. The read control signal can be generated using the clock signal CLK.

The timing control signal generator 342 of the timing controller 340A generates the data transfer timing control signal TE using the clock signal CLK, and transmits the material transfer timing control signal TE to the host 200A. The TX I/F 270 transmits the image data to the DDI 300B based on the data transmission timing control signal TE.

The image processing circuit 344 of the timing controller 340A processes the material output from the control circuit 320B using the clock signal CLK, and transmits the display material corresponding to the processing result to the drive circuit block 350.

FIG. 15 is a block diagram of a system 100C in accordance with yet another exemplary embodiment. The system 100C includes a host 200B, a DDI 300, a display panel 400, and an external memory. 500, camera 600 and frequency calculation integrated circuit (frequency calculation IC) 700. Except for the interface 290, the structure and operation of the host 200B illustrated in FIG. 15 may be substantially the same, substantially the same as or similar to the structure and operation of the host 200 illustrated in FIG. Host 200B and frequency calculation IC 700 can communicate with one another via interface 290. The frequency calculation IC 700 can include any of the frequency calculation circuits 250, 250A, 250B, 250C, 250D, 250E, 250F described above.

The frequency calculation IC 700 calculates the frequency fcnt of the data transmission timing control signal TE and/or counts the period of the data transmission timing control signal TE using the reference clock signal fref or frefd to generate a count value CNT corresponding to the count result.

The count value CNT or frequency fcnt calculated by the frequency calculation circuit 250 of the frequency calculation IC 700 is transmitted to the CPU 210 via the interface 290 in the host 200B and the bus bar 201. The CPU 210 generates a first frequency control signal using the count value CNT (for example, by determining the frequency fcnt based on the count value CNT) or the frequency fcnt, and transmits the first frequency control signal to the TX I/F 270 and the interface 12 via the TX I/F 270 and the interface 12 DDI 300. The DDI 300 adjusts the frequency of the operational clock signal of the DDI 300 based on the first frequency control signal.

The interface 12 includes a transmission line for controlling transmission of signals and a transmission line for transmission of image data. Interface 12 can be implemented as an MIPI, eDP interface, or high speed serial interface.

The structure and operation of the DDI 300 illustrated in FIG. 15 may be substantially the same or similar to the structure and operation of the DDI 300 illustrated in FIG. As shown in FIG. 15, the system 100C adjusts the DDI 300 using the frequency calculation IC 700 and the host 200B. The frequency at which the clock signal (eg, internal clock signal ifc) is operated.

As described above, according to an exemplary embodiment, a host (eg, IC, SoC, processor, AP, mobile AP, etc.) receives a data transmission timing control signal from the DDI, and calculates a frequency of the data transmission timing control signal using the reference clock signal, A frequency control signal for adjusting a frequency of the data transmission timing control signal is generated based on the calculated frequency, and the frequency control signal is transmitted to the DDI. The host corrects for frequency deviations in the DDI's operational clock signal, thereby preventing erroneous operations of devices used in systems including the host and DDI, such as touching a screen or a stylus. In other words, DDI reduces or eliminates EMI due to frequency deviations, thereby preventing abnormal operation of other devices used in the system, such as touching the screen and the stylus.

In addition, because the host corrects the frequency offset in the DDI's operational clock signal, the host does not need to provide an independent reference clock signal to the DDI. Therefore, the circuit structure of the system is simplified. In addition, DDI does not require an additional crystal oscillator because the host corrects the frequency offset in the DDI's operating clock signal.

While the exemplifying embodiments have been particularly shown and described in the foregoing, it will be understood by those skilled in the art that, without departing from the spirit and scope of the inventive concept as defined by the appended claims Various changes in form and detail are made to the illustrative embodiments.

Claims (17)

An application processor of a display system of a portable device for displaying image data on a display panel, the application processor comprising: a controller configured to obtain a frequency of a data transmission timing control signal received from a display driver integrated circuit Generating a frequency control signal for adjusting a frequency associated with an operational clock signal of the display driver integrated circuit based on the obtained frequency; a transmitter configured to generate the frequency control signal Transmitting to the display driver integrated circuit; and frequency calculation circuit, comprising: a detector configured to receive the data transmission timing control signal from the display driver integrated circuit; and a frequency calculator configured The frequency of the received data transmission timing control signal is calculated, wherein the frequency calculator is configured to output the calculated frequency to the controller. The application processor of claim 1, wherein the frequency calculation circuit further comprises: a frequency comparator configured to determine whether the calculated frequency is in a predetermined operation of the display driver integrated circuit Within the frequency range, a control signal is generated in accordance with the determination, and the generated control signal is output to the controller. The application processor of claim 2, wherein: the frequency comparator is responsive to the calculated frequency being lower than the predetermined operation Generating a first control signal in response to the calculated frequency being within the predetermined operating frequency range to generate a second control signal, and responsive to the calculated frequency being higher than the predetermined operating frequency range A third control signal is generated as the control signal. The application processor of claim 1, wherein the frequency calculation circuit further comprises: a frequency counter configured to determine a period of the received period of the data transmission timing control signal based on the reference clock signal a value, wherein the frequency calculator is configured to calculate the received frequency of the data transmission timing control signal based on the determined count value. The application processor of claim 4, wherein the detector comprises: an edge detector configured to detect based on a rising edge or a falling edge of the received data transmission timing control signal The period of the received data transmission timing control signal is measured. The application processor of claim 4, wherein the frequency calculation circuit further comprises: a frequency divider configured to divide the reference clock signal by a predetermined factor, wherein the frequency counter The configuration is configured to determine the count value based on the divided reference clock signal. A display system for displaying image data, the display system comprising: an application processor, comprising: a first controller configured to obtain a frequency of a signal provided by the display driver integrated circuit from the frequency calculation circuit, and generate an operation clock for adjusting the integrated circuit with the display driver based on the obtained frequency a first frequency control signal of a signal-related frequency, and a transmitter configured to transmit the generated first frequency control signal to the display driver integrated circuit; the frequency calculation circuit configured to Receiving the signal from the display driver integrated circuit, calculating the frequency of the received signal based on a reference clock signal, and providing the calculated frequency to the first controller; a display driver integrated circuit configured to drive display of the image material on a display panel, the display driver integrated circuit comprising: a control signal generator configured to generate the based on the operational clock signal Signaling and providing the generated signal to the application processor and the frequency calculation circuit; the receiver is configured to respond to the provided Receiving, by the application processor, the first frequency control signal; and a second controller configured to output a second frequency control signal based on the received first frequency control signal to adjust The frequency associated with the operational clock signal; wherein the display system is a portable device and the application processor is a host. The display system of claim 7, wherein the signal is Tearing effect signal. The display system of claim 7, wherein the display driver integrated circuit further comprises: an oscillator configured to output the operational clock signal, wherein the display driver integrated circuit is configured to The frequency of the operational clock signal is adjusted in accordance with the second frequency control signal. The display system of claim 7, wherein the display driver integrated circuit is configured to adjust a frequency of the generated signal based on the second frequency control signal and the operational clock signal. The display system of claim 10, wherein the display driver integrated circuit is configured to be between a frequency of deviation of the operational clock signal and the frequency of the generated signal The frequency of the generated signal is adjusted by the ratio. An application processor of a display system of a portable device for displaying image data on a display panel, the application processor comprising: a controller configured to obtain a frequency of a signal received from a display driver integrated circuit, and based on Obtaining the frequency to generate a frequency control signal for adjusting a frequency associated with an operational clock signal of the display driver integrated circuit, wherein the controller is configured to be responsive to the obtained frequency being The frequency control signal is generated outside of a predetermined operating frequency range of the display driver integrated circuit; and a transmitter configured to transmit the generated frequency control signal to the display driver integrated circuit. The application processor of claim 12, wherein: The received signal is a tearing effect signal; and the controller is configured to control the transmitter to transmit the image data to the display driver product in response to the received tearing effect signal Body circuit. The application processor of claim 12, further comprising: a frequency calculation circuit configured to receive the signal from the display driver integrated circuit and calculate the received reference based on a reference clock signal The frequency of the signal, wherein the controller is configured to generate the frequency control signal based on the calculated frequency. The application processor of claim 14, wherein the frequency calculation circuit comprises: a frequency counter configured to determine a count value of a period of the received signal based on the reference clock signal; A frequency calculator configured to calculate the frequency of the received signal based on the determined count value. The application processor of claim 12, wherein the controller is a central processing unit. The application processor of claim 12, wherein the controller is an image processing circuit.