CN109412565B - Multi-channel signal selection control circuit - Google Patents
Multi-channel signal selection control circuit Download PDFInfo
- Publication number
- CN109412565B CN109412565B CN201710711638.XA CN201710711638A CN109412565B CN 109412565 B CN109412565 B CN 109412565B CN 201710711638 A CN201710711638 A CN 201710711638A CN 109412565 B CN109412565 B CN 109412565B
- Authority
- CN
- China
- Prior art keywords
- subunit
- input
- input end
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
- H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Landscapes
- Electronic Switches (AREA)
Abstract
The invention relates to the technical field of signal detection, and discloses a multi-path signal selection control circuit which comprises input following modules, output following modules and a preset number of gating control modules, wherein a control signal output end of the input following module is connected with a control signal input end of a first gating control module, a control signal output end of each gating control module is connected with a control signal input end of a last gating control module, a clock signal output end of the input following module is respectively connected with a clock signal input end of each gating control module, a reset signal output end of the input following module is respectively connected with a reset signal input end of each gating control module, and an output end of each gating control module is commonly connected with an input end of the output following module. The invention realizes the function of multi-input and single-output of signals, and the parallel multi-channel input signals are successively selected and output, thereby having simple structure and low cost.
Description
Technical Field
The invention relates to the technical field of signal detection, in particular to a multi-channel signal selection control circuit.
Background
At present, when a plurality of signals are detected by signal detection equipment, each signal needs to correspond to one path of signal detection circuit, so that the circuit in the signal detection equipment is complex, the number of devices is large, the occupied space is large, and the cost is high.
Disclosure of Invention
The embodiment of the invention provides a multi-channel signal selection control circuit, and aims to solve the problems of complex circuit, large number of devices, large occupied space and high cost in the prior art.
The embodiment of the invention provides a multi-channel signal selection control circuit which comprises an input following module, an output following module and a preset number of gating control modules.
The control signal input end, the clock signal input end and the reset signal input end of the input following module are respectively a control signal input end, a clock signal input end and a reset signal input end of the multi-path signal selection control circuit, the control signal output end of the input following module is connected with the control signal input end of the first gating control module, the control signal output end of the gating control module is connected with the control signal input end of the last gating control module, the clock signal output end of the input following module is respectively connected with the clock signal input end of each gating control module, the reset signal output end of the input following module is respectively connected with the reset signal input end of each gating control module, the source signal input end of the gating control module is the source signal input end of the multi-path signal selection control circuit, and the output end of each gating control module is connected with the input end of the output following module, the output end of the output following module is the output end of the multi-path signal selection control circuit.
The input following module receives an external control signal, a clock signal and a reset signal and sends the signals to the gating control module, a source signal input end of the gating control module is connected with the source signal, and the gating control module controls the output of the source signal according to the control signal, the clock signal and the reset signal.
In one embodiment, the gate control module includes a triggering unit and a switch control unit.
The input end of the trigger unit is the control signal input end of the gating control module, the clock end of the trigger unit is the clock signal input end of the gating control module, the reset end of the trigger unit is the reset signal input end of the gating control module, the output end of the trigger unit and the controlled end of the switch control unit are connected together to form the control signal output end of the gating control module, the input end of the switch control unit is the source signal input end of the gating control module, and the output end of the switch control unit is the output end of the gating control module.
In one embodiment, the trigger unit comprises a first analog switch subunit, a first latch subunit, a second analog switch subunit, a second latch subunit and a logic conversion subunit.
The first input end of the first analog switch subunit is the input end of the trigger unit, the input end of the logic conversion subunit is the clock end of the trigger unit, the second input end and the third input end of the first analog switch subunit are respectively connected with the first output end and the second output end of the logic conversion subunit in a one-to-one correspondence manner, the output end of the first analog switch subunit is connected with the input end of the first latch subunit, the output end of the first latch subunit is connected with the first input end of the second analog switch subunit, the second input end and the third input end of the second analog switch subunit are respectively connected with the second output end and the first output end of the logic conversion subunit in a one-to-one correspondence manner, the fourth input end of the second analog switch subunit is the reset end of the trigger unit, the output end of the second analog switch subunit is connected with the input end of the second latch subunit, and the output end of the second latch subunit is the output end of the trigger unit.
In one embodiment, the first analog switch subunit includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube.
The grid electrode of the first switch tube and the grid electrode of the fourth switch tube are connected in common to form a first input end of the first analog switch subunit, the grid electrode of the second switch tube is a second input end of the first analog switch subunit, the grid electrode of the third switch tube is a third input end of the first analog switch subunit, the source electrode of the second switch tube and the drain electrode of the third switch tube are connected in common to form an output end of the first analog switch subunit, the drain electrode and the well potential of the first switch tube and the well potential of the second switch tube are connected in common to form direct current, the source electrode of the first switch tube is connected with the drain electrode of the second switch tube, the source electrode of the third switch tube is connected with the drain electrode of the fourth switch tube, and the source electrode and the well potential of the fourth switch tube and the well potential of the third switch tube are connected in common to the ground.
In one embodiment, the first latch subunit includes a first not gate and a second not gate.
The output end of the first NOT gate and the input end of the second NOT gate are connected in common to form the input end of the first latch subunit, and the input end of the first NOT gate and the output end of the second NOT gate are connected in common to form the output end of the first latch subunit.
In one embodiment, the second analog switch subunit includes a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and a ninth switch tube.
The grid of the fifth switch tube and the grid of the eighth switch tube are connected together to form the first input end of the second analog switch subunit, the grid of the sixth switch tube is the second input end of the second analog switch subunit, the grid of the seventh switch tube is the third input end of the second analog switch subunit, the grid of the ninth switch tube is the fourth input end of the second analog switch subunit, the source of the sixth switch tube, the drain of the seventh switch tube and the source of the ninth switch tube are connected together to form the output end of the second analog switch subunit, the drain of the fifth switch tube, the trap potential and the trap potential of the sixth switching tube are connected with direct current in common, the drain electrode and the trap potential of the ninth switching tube are connected with direct current in common, the source electrode of the fifth switching tube is connected with the drain electrode of the sixth switching tube, the source electrode of the seventh switching tube is connected with the drain electrode of the eighth switching tube, and the source electrode and the trap potential of the eighth switching tube and the trap potential of the seventh switching tube are connected with the ground in common.
In one embodiment, the second latch subunit includes a third not gate and a fourth not gate.
And the output end of the third NOT gate and the input end of the fourth NOT gate are connected in common to form the input end of the second latch subunit, and the input end of the third NOT gate and the output end of the fourth NOT gate are connected in common to form the output end of the second latch subunit.
In one embodiment, the logic conversion subunit includes a fifth not gate and a sixth not gate.
The input end of the fifth not gate is the input end of the logic conversion subunit, the output end of the fifth not gate and the input end of the sixth not gate are connected in common to form a first output end of the logic conversion subunit, and the output end of the sixth not gate is the second output end of the logic conversion subunit.
In one embodiment, the input follower module includes a first follower, a second follower, and a third follower.
The input end of the first follower is a control signal input end of the input following module, the output end of the first follower is a control signal output end of the input following module, the input end of the second follower is a clock signal input end of the input following module, the output end of the second follower is a clock signal output end of the input following module, the input end of the third follower is a reset signal input end of the input following module, and the output end of the third follower is a reset signal output end of the input following module.
In one embodiment, the output follower module includes a fourth follower.
The input end and the output end of the fourth follower are respectively the input end and the output end of the output follower module.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the control signal output end of the input following module is connected with the control signal input end of the first gating control module, the control signal output end of the gating control module is connected with the control signal input end of the last gating control module, the clock signal output end of the input following module is respectively connected with the clock signal input end of each gating control module, the reset signal output end of the input following module is respectively connected with the reset signal input end of each gating control module, and the output end of each gating control module is commonly connected with the input end of the output following module. The embodiment of the invention realizes the function of multi-input and single-output of signals, and the parallel multi-path input signals are successively selected and output, thereby having simple structure and low cost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a multi-channel signal selection control circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit structure diagram of a multi-channel signal selection control circuit in a specific application scenario according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of the trigger unit in fig. 2 according to an embodiment of the present invention;
FIG. 4 is a timing diagram of signals provided by one embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The terms "first," "second," and "third," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order.
The following detailed description of implementations of the invention refers to the accompanying drawings in which:
fig. 1 shows a structure of a multi-channel signal selection control circuit according to an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment of the present invention are shown, and detailed descriptions are as follows:
as shown in fig. 1, the multi-channel signal selection control circuit according to the embodiment of the present invention includes an input follower module 100, an output follower module 200, and a predetermined number of gate control modules 300.
The control signal input terminal, the clock signal input terminal and the reset signal input terminal of the input follower module 100 are respectively the control signal input terminal, the clock signal input terminal and the reset signal input terminal of the multi-path signal selection control circuit, the control signal output terminal of the input follower module 100 is connected with the control signal input terminal of the first gating control module 300, the control signal output terminal of the gating control module 300 is connected with the control signal input terminal of the next gating control module 300, the clock signal output terminal of the input follower module 100 is connected with the clock signal input terminal of each gating control module 300, the reset signal output terminal of the input follower module 100 is connected with the reset signal input terminal of each gating control module 300, the source signal input terminal of the gating control module 300 is the source signal input terminal of the multi-path signal selection control circuit, the output terminal of each gating control module 300 is connected with the input terminal of the output follower module 200, the output end of the output following module 200 is the output end of the multi-path signal selection control circuit.
The input following module 100 receives an external control signal Din, a clock signal CLK and a reset signal RST and transmits the signals to the gating control module 300, a source signal input end of the gating control module 300 is connected with a source signal, and the gating control module 300 controls output of the source signal according to the control signal Din, the clock signal CLK and the reset signal RST.
In this embodiment, the control signal input terminal, the clock signal input terminal and the reset signal input terminal of the input follower module 100 are respectively connected to the control signal Din, the clock signal CLK and the reset signal RST, the source signal input terminal of the first gate control module 300 is connected to the first source signal I1, the source signal input terminal of the second gate control module 300 is connected to the second source signal I2, and so on, the source signal input terminal of the nth gate control module 300 is connected to the nth source signal In, and the output terminal of the output follower module 200 outputs the driving signal OUT.
In one embodiment, the gate control module 300 controls the source signal input terminal and the source signal output terminal to be turned on and off according to the control signal Din, the clock signal CLK, and the reset signal RST.
When the source signal input terminal and the output terminal of one gating control module 300 are turned on, the source signal input terminals and the output terminals of the other gating control modules 300 are turned off. For example, if the source signal input terminal and the output terminal of the mth gate control module 300 are turned on, the driving signal OUT output by the output follower module 200 is the mth source signal Im input by the mth gate control module 300.
In this embodiment, under the control of the control signal Din, the clock signal CLK, and the reset signal RST, a preset number of the gating control modules 300 sequentially gate and output corresponding source signals, so that a plurality of parallel source signals can be output one by one, and only one of the source signals can be output.
As shown in fig. 2, the following description is given by taking a specific application scenario that the multi-channel signal selection control circuit includes 8 gating control modules 300, and it should be noted that the multi-channel signal selection control circuit may further include any number of gating control modules 300.
As shown in fig. 2, in one embodiment of the present invention, the gate control module 300 of fig. 1 includes a trigger unit 310 and a switch control unit 320.
The input end of the trigger unit 310 is a control signal input end of the gating control module 300, the clock end of the trigger unit 310 is a clock signal input end of the gating control module 300, the reset end of the trigger unit 310 is a reset signal input end of the gating control module 300, the output end of the trigger unit 310 and the controlled end of the switch control unit 320 are connected together to form a control signal output end of the gating control module 300, the input end of the switch control unit 320 is a source signal input end of the gating control module 300, and the output end of the switch control unit 320 is an output end of the gating control module 300.
In this embodiment, the input terminal I, the clock terminal CK, and the reset terminal R of the trigger unit 310 respectively access the control signal Din, the clock signal CLK, and the reset signal RST through the input follower module 100, the output terminal O of the trigger unit 310 outputs the switch control signal to the controlled terminal S of the switch control unit 320, the input terminal I of the switch control unit 320 accesses the source signal, the output terminal O of the first trigger unit 310 outputs the first switch control signal S1 to the controlled terminal S of the first switch control unit 320, the input terminal I of the first switch control unit 320 accesses the first source signal I1, and so on, the output terminal O of the nth trigger unit 310 outputs the nth switch control signal Sn to the controlled terminal S of the nth switch control unit 320, and the input terminal I of the nth switch control unit 320 accesses the nth source signal In.
In one embodiment, referring to fig. 2, the switch control unit 320 includes controlled switches, and a first terminal, a second terminal and a controlled terminal of the controlled switches are an input terminal i, an output terminal o and a controlled terminal s of the switch control unit 320, respectively.
In one embodiment, referring to fig. 2, the input follower module 100 includes a first follower U1, a second follower U2, and a third follower U3.
The input end of the first follower U1 is a control signal input end of the input following module 100, the output end of the first follower U1 is a control signal output end of the input following module 100, the input end of the second follower U2 is a clock signal input end of the input following module 100, the output end of the second follower U2 is a clock signal output end of the input following module 100, the input end of the third follower U3 is a reset signal input end of the input following module 100, and the output end of the third follower U3 is a reset signal output end of the input following module 100.
In this embodiment, the input terminal of the first follower U1 is connected to the control signal Din, the input terminal of the second follower U2 is connected to the clock signal CLK, and the input terminal of the third follower U3 is connected to the reset signal RST. The follower is used to enhance the driving capability of the output.
In one embodiment, referring to fig. 2, the output follower module 200 includes a fourth follower U4.
The input and output of the fourth follower U4 are the input and output, respectively, of the output follower module 200.
In this embodiment, the output terminal of the fourth follower U4 outputs the driving signal OUT.
As shown in fig. 3, in an embodiment of the present invention, the trigger unit 310 in fig. 2 includes a first analog switch subunit 311, a first latch subunit 312, a second analog switch subunit 313, a second latch subunit 314, and a logic conversion subunit 315.
The first input end of the first analog switch subunit 311 is the input end of the trigger unit 310, the input end of the logic conversion subunit 315 is the clock end of the trigger unit 310, the second input end and the third input end of the first analog switch subunit 311 are respectively connected with the first output end and the second output end of the logic conversion subunit 315 in a one-to-one correspondence manner, the output end of the first analog switch subunit 311 is connected with the input end of the first latch subunit 312, the output end of the first latch subunit 312 is connected with the first input end of the second analog switch subunit 313, the second input end and the third input end of the second analog switch subunit 313 are respectively connected with the second output end and the first output end of the logic conversion subunit 315 in a one-to-one correspondence manner, the fourth input end of the second analog switch subunit 313 is the reset end of the trigger unit 310, the output end of the second analog switch subunit 313 is connected with the input end of the second latch subunit 314, the output terminal of the second latch subunit 314 is the output terminal of the trigger unit 310.
In one embodiment, referring to fig. 3, the first analog switch subunit 311 includes a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a fourth switch tube Q4.
The grid electrode of the first switching tube Q1 and the grid electrode of the fourth switching tube Q4 are connected in common to form a first input end of the first analog switch subunit 311, the grid electrode of the second switching tube Q2 is a second input end of the first analog switch subunit 311, the grid electrode of the third switching tube Q3 is a third input end of the first analog switch subunit 311, the source electrode of the second switching tube Q2 and the drain electrode of the third switching tube Q3 are connected in common to form an output end of the first analog switch subunit 311, the drain electrode, the well potential of the first switching tube Q1 and the well potential of the second switching tube Q2 are connected in common to form direct current, the source electrode of the first switching tube Q1 is connected to the drain electrode of the second switching tube Q2, the source electrode of the third switching tube Q3 is connected to the drain electrode of the fourth switching tube Q4, and the source electrode, well potential of the fourth switching tube Q4 and well potential of the third switching tube Q3 are connected in common to ground.
In one embodiment, referring to fig. 3, the first switch transistor Q1 and the second switch transistor Q2 are both P-channel MOS transistors (metal oxide semiconductor transistors), and the third switch transistor Q3 and the fourth switch transistor Q4 are both N-channel MOS transistors.
In one embodiment, referring to fig. 3, the first latch subunit 312 includes a first not gate Inv1 and a second not gate Inv 2.
An output terminal of the first not gate Inv1 and an input terminal of the second not gate Inv2 are commonly connected to form an input terminal of the first latch subunit 312, and an input terminal of the first not gate Inv1 and an output terminal of the second not gate Inv2 are commonly connected to form an output terminal of the first latch subunit 312.
In one embodiment, referring to fig. 3, the second analog switch subunit 313 includes a fifth switch tube Q5, a sixth switch tube Q6, a seventh switch tube Q7, an eighth switch tube Q8, and a ninth switch tube Q9.
The grid of the fifth switching tube Q5 and the grid of the eighth switching tube Q8 are connected in common to form a first input end of the second analog switch subunit 313, the grid of the sixth switching tube Q6 is a second input end of the second analog switch subunit 313, the grid of the seventh switching tube Q7 is a third input end of the second analog switch subunit 313, the grid of the ninth switching tube Q9 is a fourth input end of the second analog switch subunit 313, the source of the sixth switching tube Q6, the drain of the seventh switching tube Q7 and the source of the ninth switching tube Q9 are connected in common to form an output end of the second analog switch subunit 313, the drain and the well potential of the fifth switching tube Q5 and the well potential of the sixth switching tube Q6 are connected in common to direct current, the drain and the well potential of the ninth switching tube Q9 are connected in common to direct current, the source of the fifth switching tube Q5 is connected to the drain of the sixth switching tube Q6, the source of the seventh switching tube Q7 is connected to the eighth switching tube 8, the source and the well potential of the eighth switch tube Q8 and the well potential of the seventh switch tube Q7 are connected to the ground in common.
In one embodiment, referring to fig. 3, the fifth switching transistor Q5, the sixth switching transistor Q6, and the ninth switching transistor Q9 are all P-channel MOS transistors, and the seventh switching transistor Q7 and the eighth switching transistor Q8 are all N-channel MOS transistors.
In one embodiment, referring to fig. 3, the second latch subunit 314 includes a third not gate Inv3 and a fourth not gate Inv 4.
An output terminal of the third not gate Inv3 and an input terminal of the fourth not gate Inv4 are commonly connected to form an input terminal of the second latch subunit 314, and an input terminal of the third not gate Inv3 and an output terminal of the fourth not gate Inv4 are commonly connected to form an output terminal of the second latch subunit 314.
In one embodiment, referring to fig. 3, the logic transforming subunit 315 includes a fifth not gate Inv5 and a sixth not gate Inv 6.
An input terminal of the fifth not gate Inv5 is an input terminal of the logic transforming subunit 315, an output terminal of the fifth not gate Inv5 and an input terminal of the sixth not gate Inv6 are commonly connected to form a first output terminal of the logic transforming subunit 315, and an output terminal of the sixth not gate Inv6 is a second output terminal of the logic transforming subunit 315.
As shown in fig. 4, in the specific application scenario shown in fig. 2, the timing of each signal will be described.
First, reset mode
When the reset signal RST is equal to 0, the flip-flop unit 310 operates in the reset state, so that the outputs of the first to eighth switch control signals S1 to S8 are all 0, i.e., none of the first to eighth source signals I1 to I8 is selected. When the reset signal RST is equal to 1, the flip-flop unit 310 operates in the normal mode.
Second, normal mode
1. After the reset signal RST is reset, the control signal Din is switched from low level to high level for one clock cycle in the 1 st clock cycle of the clock signal CLK, and the sequential selection is controlled to start at the timing shown in fig. 4. In the high level half period of the 1 st clock cycle, the first trigger unit 310 collects and receives the high level signal of the control signal Din, and latches and outputs 1 to the collected high level signal in the low level half period of the 1 st clock cycle, and the first switch control signal S1 is changed into high level; in the 7 flip-flop cells 310 connected behind the first flip-flop cell 310, since the signals at the input terminals are all 0, 0 is latched and output at a low level in a 1 st clock cycle, that is, in the 1 st clock cycle, the second switch control signal S2 to the eighth switch control signal S8 are all 0. The driving signal OUT selectively outputs the first source signal I1 in the second half of the 1 st clock period.
2. In the 2 nd clock cycle of the normal operation, the control signal Din becomes 0, and in the high-level half period of the 2 nd clock cycle, the control signal Din input by the first flip-flop unit 310 becomes 0, and the second to eighth flip-flop units 310 later receive the latch output of the previous flip-flop unit 310 in sequence. In the second half of the 2 nd clock cycle, the first trigger unit 310 latches and outputs the collected control signal Din with low level, so that the first switch control signal S1 changes from 1 to 0, and the second switch control signal S2 output by the second trigger unit 310 changes from 0 to 1. The third to eighth switch control signals S3 to S8 are output as they are, and remain at 0. Thus, the high level signal of the control signal Din is transferred from the output of the first flip-flop unit 310 to the output of the second flip-flop unit 310 in the 2 nd clock cycle. In the 2 nd clock cycle, the driving signal OUT selectively outputs the first source signal I1 in the first half cycle and the second source signal I2 in the second half cycle.
Analogizing according to the principle.
3. In the second half low period of the 3 rd clock period, the control signal Din high level signal is transferred to the third flip-flop 310, and the third switch control signal S3 outputs 1 in the second half period, and the rest of S1, S2, and S4 to S8 output 0.
In the 3 rd clock cycle, the driving signal OUT selectively outputs the second source signal I2 in the first half cycle and the third source signal I3 in the second half cycle.
4. In the second half low level period of the 4 th clock period, the control signal Din high level signal is transferred to the fourth flip-flop 310, and the fourth switch control signal S4 outputs 1 in the second half period, and the rest S1 to S3 and S5 to S8 output 0.
In the 4 th clock cycle, the driving signal OUT selects to output the third source signal I3 in the first half cycle and the fourth source signal I4 in the second half cycle.
5. In the second half low level period of the 5 th clock period, the control signal Din high level signal is transferred to the fifth flip-flop 310, and the fifth switch control signal S5 outputs 1 in the second half period, and the rest S1 to S4 and S6 to S8 output 0.
In the 5 th clock cycle, the driving signal OUT selectively outputs the fourth source signal I4 in the first half period and the fifth source signal I5 in the second half period.
6. In the second half low period of the 6 th clock period, the control signal Din high signal is transferred to the sixth flip-flop 310, and the sixth switching control signal S6 outputs 1 in the second half period, and the rest of S1 to S5 and S7 and S8 output 0.
In the 6 th clock cycle, the driving signal OUT selectively outputs the fifth source signal I5 in the first half period and the sixth source signal I6 in the second half period.
7. In the second half low period of the 7 th clock period, the control signal Din high signal is transferred to the seventh flip-flop 310, and the seventh switching control signal S7 outputs 1 in the second half period, and the remaining S1 to S6 and S8 output 0.
In the 7 th clock cycle, the driving signal OUT selectively outputs the sixth source signal I6 in the first half cycle and the seventh source signal I7 in the second half cycle.
8. In the second half low period of the 8 th clock period, the control signal Din high signal is transferred to the eighth flip-flop 310, and the eighth switch control signal S8 outputs 1 in the second half period, and the rest of S1 to S7 output 0.
In the 8 th clock cycle, the driving signal OUT selectively outputs the seventh source signal I7 in the first half cycle and the eighth source signal I8 in the second half cycle.
9. In the second half low period of the 9 th clock period, the control signal Din changes from 0 to 1 for one clock period, the control signal Din high signal is input to the first flip-flop 310, the first switch control signal S1 outputs 1 in the second half period, and the rest S2 to S8 output 0.
In the 9 th clock cycle, the driving signal OUT selectively outputs the eighth source signal I8 in the first half cycle and the first source signal I1 in the second half cycle.
And thirdly, the cycle with the period of 8 clock signal CLK periods can be realized according to the sequence.
According to the embodiment of the invention, the number of signal gating paths can be adjusted by increasing or decreasing the number of the gating control modules 300, and when the number of the control modules 300 is k, the duty ratio of the control signal Din is set to 1/k, so that each path can be gated successively.
It should be noted that the ports or pins with the same numbers in the description of the present invention and the drawings are connected.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A multi-channel signal selection control circuit is characterized by comprising an input following module, an output following module and a preset number of gating control modules;
The control signal input end, the clock signal input end and the reset signal input end of the input following module are respectively a control signal input end, a clock signal input end and a reset signal input end of the multi-path signal selection control circuit, the control signal output end of the input following module is connected with the control signal input end of the first gating control module, the control signal output end of the gating control module is connected with the control signal input end of the last gating control module, the clock signal output end of the input following module is respectively connected with the clock signal input end of each gating control module, the reset signal output end of the input following module is respectively connected with the reset signal input end of each gating control module, and the source signal input end of the gating control module is the source signal input end of the multi-path signal selection control circuit, the output end of each gating control module is connected with the input end of the output following module in common, and the output end of the output following module is the output end of the multi-channel signal selection control circuit;
the input following module receives an external control signal, a clock signal and a reset signal and sends the signals to the gating control module, a source signal input end of the gating control module is connected with a source signal, and the gating control module controls the output of the source signal according to the control signal, the clock signal and the reset signal so as to output a plurality of parallel source signals one by one.
2. The multi-channel signal selection control circuit as claimed in claim 1, wherein the gate control module includes a trigger unit and a switch control unit;
the input end of the trigger unit is the control signal input end of the gating control module, the clock end of the trigger unit is the clock signal input end of the gating control module, the reset end of the trigger unit is the reset signal input end of the gating control module, the output end of the trigger unit and the controlled end of the switch control unit are connected together to form the control signal output end of the gating control module, the input end of the switch control unit is the source signal input end of the gating control module, and the output end of the switch control unit is the output end of the gating control module.
3. The multi-channel signal selection control circuit of claim 2, wherein the trigger unit comprises a first analog switch subunit, a first latch subunit, a second analog switch subunit, a second latch subunit, and a logic conversion subunit;
the first input end of the first analog switch subunit is the input end of the trigger unit, the input end of the logic conversion subunit is the clock end of the trigger unit, the second input end and the third input end of the first analog switch subunit are respectively connected with the first output end and the second output end of the logic conversion subunit in a one-to-one correspondence manner, the output end of the first analog switch subunit is connected with the input end of the first latch subunit, the output end of the first latch subunit is connected with the first input end of the second analog switch subunit, the second input end and the third input end of the second analog switch subunit are respectively connected with the second output end and the first output end of the logic conversion subunit in a one-to-one correspondence manner, the fourth input end of the second analog switch subunit is the reset end of the trigger unit, and the output end of the second analog switch subunit is connected with the input end of the second latch subunit, and the output end of the second latch subunit is the output end of the trigger unit.
4. The multi-signal selection control circuit of claim 3, wherein the first analog switch subunit comprises a first switch tube, a second switch tube, a third switch tube and a fourth switch tube;
the grid of first switch tube and the grid of fourth switch tube connect jointly and form the first input of first simulation switch subunit, the grid of second switch tube does the second input of first simulation switch subunit, the grid of third switch tube does the third input of first simulation switch subunit, the source of second switch tube and the drain electrode of third switch tube connect jointly and form the output of first simulation switch subunit, the drain electrode of first switch tube, well electric potential and the well electric potential of second switch tube connect the direct current jointly, the source of first switch tube connects the drain electrode of second switch tube, the source of third switch tube connects the drain electrode of fourth switch tube, the source of fourth switch tube, well electric potential and the well electric potential of third switch tube connect jointly and ground.
5. The multi-signal selection control circuit of claim 3 wherein the first latch subunit comprises a first not gate and a second not gate;
The output end of the first NOT gate and the input end of the second NOT gate are connected in common to form the input end of the first latch subunit, and the input end of the first NOT gate and the output end of the second NOT gate are connected in common to form the output end of the first latch subunit.
6. The multi-signal selection control circuit of claim 3, wherein the second analog switch subunit comprises a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and a ninth switch tube;
the grid electrode of the fifth switching tube and the grid electrode of the eighth switching tube are connected in common to form a first input end of the second analog switch subunit, the grid electrode of the sixth switching tube is a second input end of the second analog switch subunit, the grid electrode of the seventh switching tube is a third input end of the second analog switch subunit, the grid electrode of the ninth switching tube is a fourth input end of the second analog switch subunit, the source electrode of the sixth switching tube, the drain electrode of the seventh switching tube and the source electrode of the ninth switching tube are connected in common to form an output end of the second analog switch subunit, the drain electrode of the fifth switching tube, the well potential and the well potential of the sixth switching tube are connected in common to direct current, the drain electrode of the ninth switching tube and the well potential are connected in common to direct current, the source electrode of the fifth switching tube is connected to the drain electrode of the sixth switching tube, and the source electrode of the seventh switching tube is connected to the drain electrode of the eighth switching tube, the source electrode and the well potential of the eighth switching tube and the well potential of the seventh switching tube are connected to the ground in common.
7. The multi-signal selection control circuit of claim 3, wherein the second latch subunit comprises a third not gate and a fourth not gate;
and the output end of the third NOT gate and the input end of the fourth NOT gate are connected in common to form the input end of the second latch subunit, and the input end of the third NOT gate and the output end of the fourth NOT gate are connected in common to form the output end of the second latch subunit.
8. The multi-signal selection control circuit of claim 3, wherein the logic conversion subunit comprises a fifth not gate and a sixth not gate;
the input end of the fifth not gate is the input end of the logic conversion subunit, the output end of the fifth not gate and the input end of the sixth not gate are connected in common to form a first output end of the logic conversion subunit, and the output end of the sixth not gate is the second output end of the logic conversion subunit.
9. The multi-signal selection control circuit of claim 1, wherein the input follower module comprises a first follower, a second follower, and a third follower;
the input of first follower does the control signal input of module is followed to the input, the output of first follower does the control signal output of module is followed to the input, the input of second follower does the clock signal input of module is followed to the input, the output of second follower does the clock signal output of module is followed to the input, the input of third follower does the reset signal input of module is followed to the input, the output of third follower does the reset signal output of module is followed to the input.
10. The multiple signal selection control circuit of claim 1, wherein the output follower module comprises a fourth follower;
and the input end and the output end of the fourth follower are respectively the input end and the output end of the output following module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710711638.XA CN109412565B (en) | 2017-08-18 | 2017-08-18 | Multi-channel signal selection control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710711638.XA CN109412565B (en) | 2017-08-18 | 2017-08-18 | Multi-channel signal selection control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109412565A CN109412565A (en) | 2019-03-01 |
| CN109412565B true CN109412565B (en) | 2022-07-15 |
Family
ID=65462807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710711638.XA Active CN109412565B (en) | 2017-08-18 | 2017-08-18 | Multi-channel signal selection control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109412565B (en) |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4745127B2 (en) * | 2006-05-23 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | Clock switching circuit |
| CN101262218B (en) * | 2008-03-11 | 2012-02-22 | 东南大学 | Data multi-channel and clockwise/anticlockwise output control circuit |
| KR20090131010A (en) * | 2008-06-17 | 2009-12-28 | 주식회사 동부하이텍 | Dual mode edge triggered flip-flop |
| US8306481B2 (en) * | 2009-10-30 | 2012-11-06 | Infineon Technologies Ag | Single pole multi throw switch |
| CN101777907A (en) * | 2009-12-31 | 2010-07-14 | 宁波大学 | Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop |
| CN102355012B (en) * | 2011-08-11 | 2013-11-27 | 深圳市天微电子有限公司 | Numerical-control constant current driving circuit |
| US20140002161A1 (en) * | 2012-07-02 | 2014-01-02 | Klaus Von Arnim | Circuit arrangement, a retention flip-flop, and methods for operating a circuit arrangement and a retention flip-flop |
| CN103236272B (en) * | 2013-03-29 | 2016-03-16 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate drive apparatus and display device |
| CN104360781B (en) * | 2014-11-12 | 2017-10-03 | 京东方科技集团股份有限公司 | Driver element, drive circuit, contact panel and the driving method of touch control electrode |
| CN104503931A (en) * | 2014-11-28 | 2015-04-08 | 上海富山精密机械科技有限公司 | Multi-channel analog signal acquisition method |
| CN106877868B (en) * | 2017-01-16 | 2020-02-14 | 电子科技大学 | High-speed successive approximation type analog-to-digital converter |
| CN106941345B (en) * | 2017-03-17 | 2020-03-10 | 中国电子科技集团公司第二十四研究所 | D trigger and asynchronous successive approximation type analog-to-digital converter |
-
2017
- 2017-08-18 CN CN201710711638.XA patent/CN109412565B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109412565A (en) | 2019-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107113003B (en) | Analog-digital converter based on successive approximation register | |
| CN102708816B (en) | Shift register, grid driving device and display device | |
| CN107437945B (en) | Parallel-serial conversion circuit | |
| CN113271097B (en) | Latch circuit, double data rate ring counter and related devices | |
| US20030115401A1 (en) | Scalable self-routing superconductor switch | |
| CN106486047B (en) | shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN102708777A (en) | Shift register unit and gate drive device | |
| JPH06140882A (en) | Reset-controllable bistable flip-flop circuit | |
| CN109412565B (en) | Multi-channel signal selection control circuit | |
| CN103208980A (en) | Window voltage comparison device | |
| US9240785B2 (en) | Analog signal compatible CMOS switch as an integrated peripheral to a standard microcontroller | |
| US8866466B2 (en) | Power generating circuit and switching circuit | |
| RU2366080C2 (en) | Self-synchronising two-cycle d flip-flop with low active control signal level | |
| CN106330169B (en) | A kind of timing sequence conversion and data-latching circuit suitable for asynchronous SAR ADC | |
| CN109412580B (en) | Selection circuit | |
| CN112799465A (en) | Control signal generator and driving method thereof | |
| US6496039B1 (en) | Clocked half-rail differential logic | |
| US2864075A (en) | Switching network | |
| SU1290567A1 (en) | Switching device | |
| SU1117628A1 (en) | Information input device | |
| RU2487393C1 (en) | Device for inputting command matrix signals | |
| SU752489A1 (en) | Shift register | |
| CN115296667A (en) | Digital signal driving circuit with multi-channel input and single-channel output and driving method | |
| RU16208U1 (en) | BATTERY CONTROL DEVICE | |
| CN110855916A (en) | Analog signal reading circuit array with variable output channel number and reading method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 336000 No.133, Yishang Avenue, Yichun economic and Technological Development Zone, Jiangxi Province Patentee after: Jiangxi Zhixin Intelligent Technology Co.,Ltd. Address before: 518000 room 1007, scientific research building, Tsinghua information port, North District, high tech Industrial Park, Nanshan District, Shenzhen, Guangdong Patentee before: SHENZHEN FINGERCHIP INTELLIGENT TECHNOLOGY Co.,Ltd. |
|
| CP03 | Change of name, title or address |