CN115296667A

CN115296667A - Digital signal driving circuit with multi-channel input and single-channel output and driving method

Info

Publication number: CN115296667A
Application number: CN202211017733.7A
Authority: CN
Inventors: 刘戈扬; 李明; 吕玉冰; 王小东; 任思伟
Original assignee: CETC 44 Research Institute
Current assignee: CETC 44 Research Institute
Priority date: 2022-08-23
Filing date: 2022-08-23
Publication date: 2022-11-04

Abstract

The invention belongs to a signal reading part in a circuit system, and relates to a digital signal driving circuit with multi-channel input and single-channel output and a driving method; the driving circuit comprises an enabling pulse generating circuit, a time sequence generating circuit and m signal transmission circuits; the enabling pulse generating circuit is provided with 1 clock signal input end, 1 enabling pulse signal input end and n column level circuit output switch control signal output ends; the time sequence generating circuit is provided with k column level circuit output switch control signal input ends and k signal transmission control time sequence output ends; each signal transmission circuit is provided with n column-level circuit signal input ends, n column-level circuit output switch control signal input ends, k signal transmission control time sequence input ends and 1 single tap data output end; in a signal transmission circuit, n columns of signals are divided into k sections to be respectively driven, and each section is provided with j columns of reading circuits, so that multi-channel input and single-channel output from a column-level circuit to single-tap signal transmission are realized.

Description

Digital signal driving circuit with multi-channel input and single-channel output and driving method

Technical Field

The invention relates to a signal reading part in a circuit system, in particular to a digital signal driving circuit with multi-channel input and single-channel output and a driving method.

Background

For a column-level signal readout circuit system which is used for reading out signals of a focal plane sensing array and takes a readout circuit with a physical size within one or a few pixel column widths as a basic unit, a subsystem which concentrates output signals of a plurality of columns of readout circuits into a single tap circuit and then unifies the output signals from the tap circuit to the outside of the readout circuit is generally needed. In this sub-system, a plurality of column-level circuits corresponding to one tap sequentially output signals to the tap in the order of, for example, column 0, column 1 to column (n-1); when a certain column-level circuit outputs a signal, other column-level circuits are disconnected from the tap; the tap receives the signal and outputs the data content of the 0 th column, the 1 st column to the (n-1) th column in sequence. The reading mode sharply reduces the requirements of the circuit system on input and output ports (physical contacts) of related data from originally thousands to dozens of times, and greatly improves the system integration level.

In order to reduce the number of taps of the circuit system and improve the system integration, it is desirable that one tap can correspond to as many column-level circuits as the tap processing speed allows. Generally, a method for directly establishing physical connection between an output terminal of a certain column-level circuit and an input terminal of a certain tap circuit, and between output terminals (switching mechanisms) of the other column-level circuits corresponding to the tap circuit, to the same net is used, and at this time, parasitic load caused by the wire itself and the output terminals of each column-level circuit needs to be considered at the same time: the more the number of the column-level circuits corresponding to the taps is, the larger the wire load and the loads brought by the rest column-level circuits are, and the higher the requirement on the output driving capability of the column-level circuits outputting signals is; considering the theory related to the RC network, the output driving capability of the column-level circuit has an objective upper limit, and the column-level circuit cannot be driven by a tap connection wire network, which is a large-scale array readout circuit, and thus the signal speed and integrity cannot be considered at the same time.

Controlling the amount of load driven by the output of each column stage circuit is one way to solve the above problem. In order to reduce the number of the taps corresponding to the column-level circuits, under the condition that the total number of the column-level circuits in a readout circuit system is fixed, the method is not beneficial to controlling the number of the taps in the system, so that the integration level of the system is influenced. A more suitable method is to add multi-stage drive on the basis of a 'direct physical connection method' lead network, and control the load quantity of the output end of a column stage circuit by adjusting the load quantity of each stage drive in a multi-stage drive circuit, but a part of a digital signal which needs to be transmitted in two directions exists in the original 'direct physical connection method' lead network, and the digital signal drive circuit required by the method usually only supports one-way signal transmission, and if the design is improper, signals in a system conflict with each other, the framework and the time sequence need to be designed elaborately to ensure that the signals are transmitted in the correct direction.

Disclosure of Invention

The invention provides a digital signal driving circuit with multi-channel input and single-channel output, which is particularly suitable for application of a column-level readout circuit to signal transmission of a single-channel tap.

In a first aspect of the present invention, the present invention provides a digital signal driving circuit with multi-channel input and single-channel output, comprising an enable pulse generating circuit, a timing sequence generating circuit and m signal transmission circuits; the enabling pulse generating circuit is provided with a clock signal input end, an enabling pulse signal input end and n column-level circuit output switch control signal output ends; the time sequence generating circuit is provided with k column level circuit output switch control signal input ends and k signal transmission control time sequence output ends; each signal transmission circuit is provided with n column-level circuit signal input ends, n column-level circuit output switch control signal input ends, k signal transmission control time sequence input ends and a single tap data output end; n/k = j; n, k, j and m are positive integers, and n and k are even numbers;

the n column-level circuit signal input ends of each signal transmission circuit correspond to the n column-level circuit signal input end buses of the digital signal driving circuit one by one; the single tap data output ends of the m signal transmission circuits are used as m single tap data output ends of the digital signal driving circuit one by one; the k signal transmission control time sequence output ends of the time sequence generating circuit are connected with the k signal transmission control time sequence input ends of each signal transmission circuit in a one-to-one correspondence manner; a clock signal input end and an enable pulse signal input end of the enable pulse generating circuit are respectively used as a clock signal input end and an enable pulse signal input end of the digital signal driving circuit; the output switch control signal output ends of the n column-level circuits of the enabling pulse generating circuit are connected with the output switch control signal input ends of the n column-level circuits of the m signal transmission circuits in a one-to-one correspondence manner; and the output switch control signal output ends of the k column-level circuits of the enabling pulse generating circuit are connected to the output switch control signal input ends of the k column-level circuits of the time sequence generating circuit in a one-to-one correspondence manner.

In a second aspect of the present invention, the present invention further provides a multi-channel input single-channel output digital signal driving method, which is used for implementing the multi-channel input single-channel output digital signal driving circuit according to the first aspect of the present invention, and the method includes:

a clock is input at a clock signal input end of an enabling pulse generating circuit, and a pulse which has a high level length of one clock cycle and can be identified by a clock trigger edge is input at the enabling pulse signal input end;

sequentially outputting pulses with the high level length of one clock period at the output end of a column-level circuit output switch control signal of the enabling pulse generating circuit according to the sequence of 0 th to (n-1) th ports;

the n column-level circuit output switch control signals are used for sequentially closing and opening all column-level circuit output switches in the m signal transmission circuits, so that signals on the data input end buses of all the column-level circuits sequentially enter all the signal transmission circuits for transmission;

k column-level circuit output switch control signals are output to the time sequence generating circuit and are used for generating time sequences for controlling the opening and closing of k driver related switches in each signal transmission circuit, and the generated time sequences are output to the signal transmission control time sequence input end of each signal transmission circuit from k signal transmission control time sequence output ends of the time sequence generating circuit;

sequentially outputting the signals of the corresponding column-level circuits collected by the signal transmission circuits through the single-tap data output end of each signal transmission circuit;

when one clock period is over, keeping the input clock of the enabling pulse generating circuit unchanged, sending a pulse with the high level length of one clock period and capable of being identified by a clock triggering edge to the enabling pulse signal input end of the enabling pulse generating circuit again, namely repeating the process; the pulse width of each column stage circuit data is one clock cycle, and a large cycle, namely n clock cycles, is needed for finishing the data output of all columns.

The invention has the beneficial effects that:

1. the invention realizes the multi-stage driving of digital signal wires by arranging a plurality of driving circuits controlled by time sequence on a signal transmission path on the traditional multi-channel input and single-channel output digital signal driving circuit which is particularly suitable for the transmission from a column-level circuit to a single tap signal, and effectively overcomes the problem of large parasitic load caused by large-area and long-distance wires in the circuit.

2. Compared with the traditional drive circuit, the time sequence required by the newly added circuit is completely generated in the circuit, the normal operation can be realized only by using the time sequence (clock and enabling pulse) used by the traditional drive circuit, the new time sequence does not need to be added, and the use is simple and convenient.

3. The invention has little change to the main signal transmission circuit part in the traditional drive circuit, except the drive circuit which takes the buffer as the main part, no other devices are added, and the added time sequence generating circuit supports the provision of time sequences for a plurality of signal transmission circuits (for merging bus output), thereby being beneficial to controlling the layout area size of the circuit and being convenient for physical realization.

Drawings

FIG. 1 is a schematic diagram of a multi-channel input, single-channel output digital signal driver circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an enable pulse generation circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a timing generation circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a timing generation sub-circuit that may be used in accordance with an embodiment of the present invention;

FIG. 5 is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a digital signal driver circuit used in a preferred embodiment of the present invention;

FIG. 7 is a diagram illustrating input and output timing signals in accordance with an embodiment of the present invention;

in the figure: wherein:

101: enable pulse generation circuit, 102: timing generation circuits, 103 to 105: signal transmission circuit, 106 to 108: column-level circuit signal input terminal bus, 109 to 111: single tap data output, 112: clock signal input terminal, 113: an enable pulse signal input;

201 to 205: d flip-flop, 206-210: column stage circuit output switch control signal output terminal, 211: enable pulse signal input terminal, 212: a clock signal input terminal;

301 to 305: timing generation sub-circuit, 306 to 311: signal transmission control timing output terminal, 312 to 317: the column stage circuit outputs a switch control signal input end;

401: initial switching pulse input, 402: end switch pulse input, 403: switched pulse delivery output, 404: switching pulse delivery inverting output, 405: inverter 1, 411: inverter 2, 406: or gate 1, 408: or gate, 2, 410: or gate 3, 407: 1 st and gate, 409: a 1 st latch;

501 to 507: tri-state gate driver, 508 to 527: column-stage circuit signal input terminals, 528 to 534: signal transmission control timing input terminal, 535-554: column level circuit output switch, 555: a single tap data output;

601 to 603: pulse counter, 604: enable pulse generation circuit, 605: timing generation circuit, 606 to 609: signal transmission circuit, 610 to 612: count pulse input terminal of digital signal drive circuit, 613: pulse counter reset signal input terminal of digital signal drive circuit, 614 to 617: single tap data output of digital signal drive circuit, 618: clock signal input terminal of digital signal drive circuit, 619: and an enable pulse signal input end of the digital signal driving circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention provides a digital signal driving circuit with multi-channel input and single-channel output.A top layer circuit (circuit 1 for short) of the driving circuit system comprises an enable pulse generating circuit 101 (circuit 2 for short), a time sequence generating circuit 102 (circuit 3 for short) and m signal transmission circuits 103, 104 and 105 (circuit 4 for short) in total of 0 th, 1 th, … … and (m-1) as shown in figure 1.

The enable pulse generating circuit 101 has a clock signal input terminal 112 (clk), an enable pulse signal input terminal 113 (en _ pulse), and n column stage circuit output switch control

signal output terminals

109, 110, 111 (col _ sw _ en <0:n-1 >);

the timing generation circuit 102 has k column stage circuit output switch control signal input terminals (col _ sw _ en <0,j-1,2j-1, …, n-j-1 >) and k signal transmission control timing output terminals (int _ sw _ ctrl <0:k-1 >);

each of the signal transmission circuits 103, 104, 105 has n column-stage circuit signal input terminals (col _ data _ in <0:n-1 >), n column-stage circuit output switch control signal input terminals (col _ sw _ en <0:n-1 >), k signal transmission control timing input terminals (int _ sw _ ctrl <0:k-1 >) and one single tap

data output terminal

109, 110, 111 (col _ data _ out);

in the circuit ports, n, j and k follow the relation of n/k = j; n, j, k and m are all positive integers, n and k are even numbers, and j is not less than 2,k and not less than 4.

Wherein, n column level circuit signal input terminals col _ data _ in <0:n-1> of each signal transmission circuit are used as n column level circuit signal

input terminal buses

106, 107, 108 of the digital signal driving circuit in a one-to-one correspondence; that is, all the column-stage circuit signal input terminals col _ data _ in <0:n-1> of the 0 th circuit 4 are served as the 0 th group of column-stage circuit signal input terminal bus col _ data _ in _0 of the circuit 1 by n-1>, all the column-stage circuit signal input terminals col _ data _ in <0:n-1> of the 1 st circuit 4 are served as the 1 st group of column-stage circuit signal input terminal bus col _ data _ in _1 of the circuit 1 by n-1>, and so on until all the column-stage circuit signal input terminals col _ data _ in <0:n-1> of the (m-1) th circuit 4 are served as the (m-1) th group of column-stage circuit signal input terminal buses 106, 107, 108 (col _ data _ in _ (m-1) <0:n >) of the circuit 1.

The single tap data output ends of the m signal transmission circuits are used as m single tap data output ends of the digital signal driving circuit one by one; that is, in order, the 0 th, 1 st, … …, (m-1) the one-tap data output port col _ data _ out of the circuit 4 is taken as the 0 th, 1 st, … …, (m-1) the one-tap

data output port

109, 110, 111 (col _ data _ out <0:m-1 >) of the circuit 1.

K signal transmission control time sequence output ends int _ sw _ ctrl <0:k-1> of the time sequence generating circuit are connected with k signal transmission control time sequence input ends int _ sw _ ctrl <0:k-1> of the m signal transmission circuits in a one-to-one correspondence mode according to names;

a clock signal input end 112 and an enable pulse signal input end 113 of the enable pulse generating circuit are respectively used as the clock signal input end 112 and the enable pulse signal input end 113 of the digital signal driving circuit;

n column stage circuit output switch control signal output ends col _ sw _ en <0:n-1> of the enable pulse generating circuit are connected with n column stage circuit output switch control signal input ends col _ sw _ en <0:n-1> of the m signal transmission circuits in a one-to-one correspondence mode according to names;

k column stage circuit output switch control signal output ends col _ sw _ en <0,j-1,2j-1, …, n-j-1> of the enable pulse generation circuit are connected to k column stage circuit output switch control signal input ends col _ sw _ en <0,j-1,2j-1, …, n-j-1> of the timing generation circuit in a one-to-one correspondence mode.

In an embodiment of the present invention, a driving method corresponding to the digital signal driving circuit includes:

sequentially outputting pulses with the high level length of one clock period at the output end col _ sw _ en <0:n-1> of the output switch control signal of the column-level circuit of the enabling pulse generating circuit according to the sequence of 0 to (n-1) th ports;

k column stage circuit output switch control signals col _ sw _ en <0,j-1,2j-1, …, n-j-1> are output to the timing sequence generating circuit 102, and are used for generating a timing sequence for controlling the opening and closing of k driver related switches in each signal transmission circuit, and the generated timing sequence is output to a signal transmission control timing input end int _ sw _ ctrl <0:k-1> of each signal transmission circuit from k signal transmission control timing sequence output ends int _ sw _ ctrl <0:k-1> of the timing sequence generating circuit;

when one clock period is over, keeping the input clock of the enabling pulse generating circuit unchanged, sending a pulse with the high level length of one clock period and capable of being identified by a clock triggering edge to the enabling pulse signal input end of the enabling pulse generating circuit again, namely repeating the process; the pulse width of each part of column-level circuit data is one clock cycle, and one large cycle, namely n clock cycles, is needed for finishing the data output of all columns.

In the process, the circuit 1 serves as a single-tap output system, collected signals corresponding to the column-level circuits are sequentially output by the single-tap data output ends of the circuits 4, the pulse width of each column-level circuit data is one clock cycle, and n clock cycles are needed for completing data output of all columns. After the above process is finished, the input clock of the holding circuit 2 is unchanged, and the signal with the above characteristic is sent to the enable pulse signal input end again, so that the process can be repeated.

The digital signal driving circuit and the corresponding driving method can be understood as follows: for a total of n columns of readout circuits corresponding to a single tap, some combined output signal conductor of the columns is divided into k sections in a signal transmission circuit to be driven respectively, each section comprises an output structure of j columns of readout circuits, and the system can support n columns of m-bit bus outputs. Therefore, in the circuit ports, n, j, k, and m are all positive integers, n and k are even numbers, j is not less than 2,k and not less than 4,n, j, and k follow the relationship of n/k = j.

An enable pulse generating circuit (circuit 2) is shown in fig. 2, the enable pulse generating circuit comprises n cascaded D flip-

flops

201, 202, 203, 204 and 205, which are sequenced according to 0,1, … … and (n-1), and the Q output end of the previous D flip-flop is connected with the D input end of the next D flip-flop; the clock input ends of the n D triggers are connected to the same clock signal input end, wherein the D input end of the foremost D trigger is connected with the enabling pulse signal input end, and the Q output ends of the n D triggers are respectively used as output switch control signal output ends of the n column-level circuits.

Specifically, the D input terminal of the 0 th flip-flop is used as the enable pulse signal input terminal 211 of the circuit 2, and the clock input terminal CK thereof is used as the clock signal input terminal 212 of the circuit 2; the Q output end of the 0 th trigger is connected with the D input end of the 1 st trigger, the Q output end of the 1 st trigger is connected with the D input end of the 2 nd trigger, and so on until the Q output end of the (n-2) th trigger is connected with the D input end of the (n-1) th trigger, meanwhile, the connection of the Q output end and the adjacent D input end is respectively used as (n-1) output switch control signal output ends 206, 207, 208 and 209 (col _ sw _ en <0:n-2 >) of the circuit 2, the Q output end of the (n-1) th trigger is used as a column circuit output switch control signal output end 210 (col _ sw _ en < n-1 >) of the circuit 2, and the clock input ends of the 1 st and 2 th to (n-1) th triggers are all connected with a clock signal input end 212 of the circuit 2.

In an embodiment of the present invention, under the enable pulse generating circuit, a driving method corresponding to the digital signal driving circuit includes:

a clock is input at a clock signal input end of an enabling pulse generating circuit, and a pulse which has a high level length of one clock cycle and can be identified by a clock trigger edge is input at the enabling pulse signal input end; after a certain time delay occurs after the time of a clock triggering edge, a 0 th trigger of the enabling pulse generating circuit outputs a pulse with a high level length of one clock period at the Q output end, the pulse is used as a signal of an output switch control signal output end of the column level circuit to be output outwards, and simultaneously the pulse is input at the D input end of a 1 st trigger, and the clock triggering process is repeated; the pulse is transmitted through a trigger in the enabling pulse generating circuit until the output end of the output switch control signal of the last column stage circuit outputs the pulse outwards in the nth clock cycle, and the operation process of a large cycle is finished.

Specifically, a clock is input to a clock signal input end, a pulse which has a high level length of one clock cycle and can be identified by a clock trigger edge is input to an enable pulse signal input end (for example, a certain clock trigger edge is located at the middle time of the high level of an enable pulse signal), a 0 th trigger outputs a pulse which has a high level length of one clock cycle at a Q output end after a certain time delay after the occurrence time of the clock trigger edge, the pulse is output outwards as a signal of a column-level circuit output switch control signal output end col _ sw _ en <0>, and the pulse is input to a D input end of a 1 st trigger, the clock trigger process is repeated, a pulse which has a high level length of one clock cycle is output at a Q output end in the next second clock cycle, the pulse is output outwards as a signal of a column-level circuit output switch control signal output end col _ sw _ en <1>, and so on, the pulse is subjected to a "transfer" process "through a trigger in a circuit 2 until a large pulse output process of a last column-level circuit output switch control signal output end col _ sw _ en < n-1> in the first clock cycle, and the process is ended; and keeping the clock signal input, and inputting a pulse with the high level length of one clock cycle and capable of being identified by the clock trigger edge again at the input end of the enable pulse signal, so that the process can be repeated.

As shown in fig. 3, the timing generation circuit (circuit 3) includes (k-1) timing generation sub-circuits 301, 302, 303, 304, 305 (hereinafter referred to as circuit 5) in total of 0 th, 1 th, 2 th, … and (k-2); the circuit 5 is provided with a starting switch pulse input end pulse _ start _ prev, an ending switch pulse input end pulse _ end, a switch pulse transmission output end level _ next and a switch pulse transmission inverted output end level _ next _ b; the switch pulse transmission output end of the previous time sequence generation sub-circuit is connected to the initial switch pulse input end of the next time sequence generation sub-circuit to form a cascade circuit; wherein, the switch pulse transmission output ends of the 0 th to (k/2-1) th time sequence generation sub-circuits are sequentially connected with the first k/2 signal transmission control time sequence output ends 306, 307 and 308, and the switch pulse transmission inverted output ends of the (k/2-1) th to (k-2) th time sequence generation sub-circuits are sequentially connected with the rear k/2 signal transmission control time sequence output ends 309, 310 and 311; the start switch pulse input terminal of the 0 th timing generation sub-circuit and the end switch pulse input terminals of the 0 th to (k-2) th timing generation sub-circuits are sequentially connected to k column-level circuit output switch control signal input terminals 312, 313, 314, 315, 316, 317 (middle part ports are omitted).

Specifically, the initial switching pulse input terminal of the (k/2-1) th circuit 5 in the circuit 3 is connected to the switching pulse transmission output terminal of the (k/2-2) th circuit 5, and the connection line is used as the signal transmission control timing output terminal int _ sw _ ctrl < k/2-2> of the circuit 3; the ending switch pulse input end of the (k/2-1) th circuit 5 is used as the output switch control signal input end col _ sw _ en < n/2-1> of the column circuit of the circuit 3; the switch pulse transmission output end of the (k/2-1) th circuit 5 is connected with the initial switch pulse input end of the (k/2) th circuit 5 and is used as a signal transmission control timing output end int _ sw _ ctrl < k/2-1> of the circuit 3; the switching pulse transmission inverting output terminal of the (k/2-1) th circuit 5 serves as a signal transmission control timing output terminal int _ sw _ ctrl < k/2> of the circuit 3; the starting switch pulse input end of the (k/2-2) th circuit 5 is connected with the switch pulse transmission output end of the (k/2-3) th circuit 5 and serves as a signal transmission control timing output end int _ sw _ ctrl < k/2-3> of the circuit 3, the starting switch pulse input end of the (k/2-3) th circuit 5 is connected with the switch pulse transmission output end of the (k/2-4) th circuit 5 and serves as a signal transmission control timing output end int _ sw _ ctrl < k/2-4> of the circuit 3, and so on until the starting switch pulse input end of the 1 st circuit 5 is connected with the switch pulse transmission output end of the 0 th circuit 5 and serves as a signal transmission control timing output end int _ sw _ ctrl <0> of the circuit 3; the switch pulse transmission inverted output ends of the 0 th, 1 th, … … (k/2-3) and (k/2-2) th circuits 5 are not externally connected, and the ending switch pulse input ends of the two are respectively used as the output switch control signal input ends col _ sw _ en < j-1,2j-1, … and n/2-2j-1,n/2-j-1> of the column level circuit of the circuit 3; the initial switch pulse input end of the 0 th circuit 5 is used as the output switch control signal input end col _ sw _ en <0> of the column level circuit of the circuit 3; the switching pulse transmission output end of the k/2 th circuit 5 is connected with the initial switching pulse input end of the (k/2+1) th circuit 5, the switching pulse transmission output end of the (k/2+1) th circuit 5 is connected with the initial switching pulse input end of the (k/2+2) th circuit 5, and the like, until the switching pulse transmission output end of the (k-3) th circuit 5 is connected with the initial switching pulse input end of the (k-2) th circuit 5; the switching pulse transmission inverting output ends of the k/2, (k/2+1), … …, (k-3) and (k-2) circuits 5 are respectively used as signal transmission control timing output ends int _ sw _ ctrl < k/2+1, k/2+2, … and k-2,k-1> of the circuits 5, and the ending switching pulse input ends of the switching pulse transmission inverting output ends are respectively used as column stage circuit output switching control signal input ends col _ sw _ en < n/2+j-1,n/2+2j-1, … and n-2j-1,n-j-1> of the circuits 3; the switching pulse transfer output terminal of the (k-2) th circuit 5 is not externally connected.

In an embodiment of the present invention, under the timing generation circuit, a driving method corresponding to the digital signal driving circuit includes:

the method comprises the steps that pulses with high level duration being one clock cycle are respectively input into a 0 th column level circuit output switch control signal input end and a (j-1) th column level circuit output switch control signal input end of a time sequence generating circuit, the pulses are processed by a 0 th time sequence generating sub-circuit, a pulse with rising edge coinciding with the rising edge of an input pulse of the 0 th column level circuit output switch control signal input end, falling edge coinciding with the falling edge of an input pulse of a (j-1) th column level circuit output switch control signal input end and high level width being j clock cycles is generated at a switch pulse transmission output end of the 0 th time sequence generating sub-circuit, the pulses are output from a signal transmission control time sequence output end of the time sequence generating circuit, are used for controlling corresponding switches in the signal transmission circuit and are simultaneously input into a starting switch pulse input end of the 1 st time sequence generating sub-circuit; repeating the above process, sequentially inputting a pulse with a high level duration of one clock cycle at the ending switch pulse input end of the 1 st to (k/2-1) time sequence generating sub-circuits, wherein the switch pulse transmission output end of the 1 st to (k/2-1) time sequence generating sub-circuits in the time sequence generating circuit is used as the 1 st to (k/2-1) signal transmission control time sequence output end of the time sequence generating circuit, and respectively outputting a rising edge which is coincident with the rising edge of the input pulse at the output switch control signal input end of the 0 th column level circuit, a falling edge which is coincident with the (2 j-1), (3 j-1), and (…, and (n/2-1) pulses with high level widths of 2j, 3j, … … and n/2 clock cycles at the output switch control signal input end of the column level circuit;

outputting a signal which is in the opposite phase with the switch pulse transmission output end of the (k/2-1) th time sequence generation sub-circuit at the switch pulse transmission output end, wherein the rising edge of the signal coincides with the falling edge of the (k/2-1) th transmission control time sequence output end of the time sequence generation circuit, the falling edge of the signal coincides with the rising edge of the pulse received by the output switch control signal input end of the column-level circuit in the next large period, the high level width of the signal is at least n/2 clock periods, and the signal is output as the (k/2) th signal transmission control time sequence output end of the time sequence generation circuit; repeating the above process, inputting pulses with high level duration of one clock cycle into the output switch control signal input ends of the kth/2 to (k-2) column stage circuits of the time sequence generating circuit in sequence, after the pulses are processed by the kth/2 to (k-2) time sequence generating sub-circuits, respectively, outputting rising edges from the switch pulse transmission inverting output ends of the output switch control signal input ends of the column stage circuits of the time sequence generating circuit, overlapping the falling edges of the pulses received by the output switch control signal input ends of the column stage circuits, and overlapping the falling edges of the pulses received by the output switch control signal input ends of the 0 th column stage circuit of the next large cycle, wherein the high level widths are at least (n/2-j), (n/2-2 j), … … and j clock cycles, and ending the operation process of one large cycle.

Specifically, firstly, pulses with a high level duration of one clock cycle are respectively input to the column-level circuit output switch control signal input terminals col _ sw _ en <0> and col _ sw _ en < j-1> of the circuit 3, and considering the working principle of the circuit 2 generating the two pulses, the time when col _ sw _ en < j-1> receives the pulses is (j-1) clock cycles later than the time when col _ sw _ en <0> receives the pulses, and through the processing of the 0 th circuit 5, a pulse with a high level duration of j clock cycles is generated at the switch pulse transmission output terminal of the circuit 5, wherein the pulse is output from the signal transmission control timing output terminal int _ sw _ ctrl <0> of the circuit 3, and is used for controlling the corresponding switches in the circuit 4 and simultaneously input to the input terminal of the 1 st switch 5 in the circuit 3; a pulse with a high level duration of one cycle is input to an ending switch pulse input terminal of a 1 st circuit 5 (i.e., a column-level circuit output switch control signal input terminal col _ sw _ en <2j-1> of a circuit 3), and considering the operating principle of the circuit 2 generating the pulse, the moment when col _ sw _ en <2j-1> receives the pulse will be (2 j-1) clock cycles later than the moment when col _ sw _ en <0> receives the pulse, and a pulse with a rising edge coinciding with the rising edge of a col _ sw _ en <0> input pulse, a falling edge coinciding with the falling edge of a col _ sw _ en <2j-1> input pulse and a high level width of 2j clock cycles is generated at a switch pulse transmission output terminal of the circuit 5 through the processing of the 1 st circuit 5, and the pulse is output from a signal transmission control timing output terminal int _ sw _ ctrl <1> of the circuit 3 and is simultaneously input to the initial switch pulse input terminal of the 1 st circuit 5 in the circuit 3; by analogy, according to the above process, the switching pulse transmission output terminals of the 2 nd, 3 rd, … …, (k/2-1) circuits 5 in the circuit 3 will be used as signal transmission control timing output terminals int _ sw _ ctrl <2,3, …, k/2-1 of the circuit 3, and respectively output pulses with rising edges coinciding with the rising edges of col _ sw _ en <0> input pulses, falling edges coinciding with the falling edges of col _ sw _ en <3j-1,4j-1, …, n/2-1> input pulses, and high level widths of 3j, 4j, … …, and n/2 clock cycles; the switching pulse transmission inverted output end of the (k/2-1) th circuit 5 in the circuit 3 outputs a signal inverted to the switching pulse transmission output end thereof, the rising edge thereof coincides with the falling edge of the transmission control timing output end int _ sw _ ctrl < k/2-1> of the circuit 3, the falling edge thereof coincides with the rising edge of the pulse received by the column-level circuit output switching control signal input end col _ sw _ en <0> of the next large period, and the high level width thereof is at least n/2 clock periods, and the signal is output as the signal transmission control timing output end int _ sw _ ctrl < k/2> of the circuit 3; then pulses with high level duration of one clock cycle are respectively input into the ending switch pulse input ends of k/2, (k/2+1), … … and (k-2) circuits 5 (namely, the column stage circuit output switch control signal input end col _ sw _ en < n/2+j-1,n/2+2j-1, …, n-j-1> of the circuit 3) in the circuit 3, the time when the input ends receive the pulses is respectively later than the time when col _ sw _ en <0> receives the pulses by (n/2+j-1), (n/2 zxft 2j-1), … … and (n-j-1) clock cycles, and after the processing by the circuit 5, transmitting the output rising edges from the inverting output ends (namely the output switch control signal input ends int _ sw _ ctrl < k/2+1, k/2+2, …, k-1 >) of the column stage circuits from the switching pulse transmission inverting output ends (namely, the output switch control signal input ends int _ sw _ ctrl < k/2+1, k/2+2, …, k-1 >) of the circuits are respectively overlapped with the falling edges of the pulses received by the output switch control signal input ends col _ sw _ en < n/2+j-1,n/2 j-1, …, n-j-1> of the column stage circuits, the falling edges of the pulses are overlapped with the rising edges of the pulses received by the output switch control signal input ends col _ sw _ en <0> of the next large period, and the pulses with high level widths of at least (n/2-j), (n/2-2 j), 4924 zxft 49j clock periods respectively end the operation process of one large period; the operation circuit 2 inputs pulses to the input end of the column-level circuit output switch control signal of the circuit 3 again, and the process can be repeated.

One useful circuit 5 is shown in fig. 4, which includes 2 inverters 1,2, 3 or gates 1,2, 3, 1 and gate 407 and 1 latch 409 (which latches data when the latch pulse level is high), the input terminal of the 1 inverter 405 is connected to the ending switch pulse input terminal 402 of the circuit 5, and the output terminal thereof is connected to the 1 st input terminal of the 1 st and gate; the 2 nd input terminal of the 1 st AND gate is connected to the data output terminal (Q terminal) of the 1 st latch, and the output terminal thereof is connected to the 2 nd input terminal of the 2 nd OR gate 408; the 1 st input terminal of the 2 nd or gate 408 is connected to the initial switching pulse input terminal 401 of the circuit 5, and the output terminal thereof is connected to the data input terminal (terminal D) of the 1 st latch; the latch pulse input end (L end) of the 1 st latch is connected with the output end of the 1 st OR gate 406; the 1 st input end of the 1 st OR gate 406 is connected with the initial switch pulse input end of the circuit 5, and the 2 nd input end thereof is connected with the ending switch pulse input end of the circuit 5; the 1 st input terminal of the 3 rd or gate 410 is connected to the ending switch pulse input terminal of the circuit 5, the 2 nd input terminal thereof is connected to the data output terminal of the 1 st latch, and the output terminal thereof is connected to the switch pulse transmission output terminal 403 of the circuit 5 and the input terminal of the 2 nd inverter 411; the output of the 2 nd inverter 411 is connected to the switching pulse transfer inverting output 404 of circuit 5.

In an embodiment of the present invention, under the timing generation sub-circuit, a driving method corresponding to the digital signal driving circuit includes:

the use method of the circuit 5 is as follows: firstly, pulses with certain high level duration are respectively input at the input end of a starting switch pulse and the input end of an ending switch pulse, the high level parts of the two pulses are not overlapped, and the pulse input to the input end of the ending switch pulse reaches a circuit 5 later than the pulse input to the input end of the starting switch pulse; then, generating two front and back pulses at the No. 1 or gate, wherein the two front and back pulses are respectively used for the related data latch of the No. 1 latch; the 1 st phase inverter, the 1 st AND gate, the 2 nd OR gate and the 1 st register form a sample hold device, when starting to input pulses to the initial switch pulse input end, the 1 st register samples, the data output end of the 1 st register starts to output high level, after finishing inputting high level pulses to the initial switch pulse input end, the 1 st latch is changed into a latch state from the sampling state, the data output end of the 1 st latch can still keep the high level unchanged until the finishing switch pulse input end receives the high level, the 1 st latch enters the sampling state again, samples the low level received at the 1 st input end of the 1 st AND gate, the data output end of the 1 st latch outputs the low level, after finishing inputting high level pulses to the finishing switch pulse input end, the 1 st latch is changed into the latch state again, and the data output end keeps outputting the low level; and then, splicing the high-level pulse output by the data output end of the 1 st register and the pulse output by the end switch pulse input end in a time domain by using a 3 rd OR gate, finally obtaining a long pulse with a rising edge superposed with the rising edge of the pulse input to the start switch pulse input end, a falling edge superposed with the falling edge of the pulse input to the end switch pulse input end and a high-level time length equal to the sum of the mutual delay time of the rising edges of the two input pulses and the high-level time length of the pulse input to the end switch pulse input end at the output end of the OR gate (namely, the switch pulse transmission output end of the circuit 3), and obtaining an inverted signal of the long pulse at the switch pulse transmission inverted output end.

As shown in fig. 5, the signal transmission circuit (circuit 4) includes 0,1, … …, (k-1) k digital signal drivers 501, 502, 503, 504, 505, 506, 507 with tri-state gates and n column-level circuit output switches 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, wherein in the 0 th to (k/2-1) th drivers, the output terminal of the previous driver is connected to the input terminal of the next driver, in the (k/2-1) th to (k-1) th drivers, the input terminal of the previous driver is connected to the output terminal of the next driver, the input terminal of each driver is connected to the output terminals of the j column-level circuit output switches, and the status control terminals of the 0 to (k-1) th drivers are connected to the k signal transmission control timing input terminals 528, 529, 533, 534, 532, 534 of the signal transmission circuit; the signal input ends 508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526 and 527 of the 0 th to (n-1) th column-level circuits of the signal transmission circuit are sequentially connected with the input ends of the output switches of the 0 th to (n-1) th column-level circuits, wherein the output end of the (k/2-1) th driver is connected with the single-tap data output end 555 of the signal transmission circuit.

Specifically, the output end of the (k/2-1) th driver is connected with the output end of the (k/2) th driver and is connected with the single-tap data output end col _ data _ out of the circuit 4; the input end of the (k/2-1) th driver is connected with the output end of the (n/2-j), (n/2-j + 1), … …, (n/2-2), (n/2-1) column stage circuit output switch of the circuit 4 and is connected with the output end of the (k/2-2) th driver, the input end of the (k/2-2) th driver is connected with the output end of the (n/2-2 j), (n/2-2j 1), … …, (n/2-j-2), (n/2-j-1) column stage circuit output switch of the circuit 4 and is connected with the output end of the (k/2-3) th driver, and so on until the input end of the 0 th driver is connected with the output end of the 0 th, 1, … …, (j-2), (j-1) column stage circuit output switch of the circuit 4; the input terminal of the k/2 th driver is connected to the output terminal of the (n/2), (n/2+1), … …, (n/2+j-2), (n/2+j-1) th column stage circuit output switch of circuit 4, and is connected to the output terminal of the (k/2+1) th driver, the input terminal of the (k/2+1) th driver is connected to the output terminal of the (n/2+j), (n/2 j + 1), … …, (n/2 + 2j-2), (n/2 + 2j-1) column stage circuit output switch of circuit 4, and is connected to the output terminal of the (k/2+2) th driver, and so on until the input terminal of the (k-1) th driver is connected to the output terminal of the (n-j + 321), (n-j + 1), … … -1) column stage circuit output terminal of circuit 4, and so on; the input ends of the output switches of 0,1, … … and (n-1) column level circuits are respectively connected with 0,1, … … and (n-1) column level circuit signal input end col _ data _ in <0:n-1> of the circuit 4 in sequence; the state control ends of the 0 th, 1 st, … … and (k-1) th drivers are sequentially connected with the signal transmission control timing input end int _ sw _ ctrl <0:k-1> of the circuit 4 respectively.

In an embodiment of the present invention, under the signal transmission circuit, a driving method corresponding to the digital signal driving circuit includes:

the state control end of the used tri-state gate is set to keep normal buffer output when receiving high level, and the output end is in high impedance state when receiving low level;

pulses with certain high level duration are respectively input at a starting switch pulse input end and an ending switch pulse input end of the time sequence generating sub-circuit, the high level parts of the two pulses are not overlapped, and the pulse input to the ending switch pulse input end reaches the time sequence generating sub-circuit later than the pulse input to the starting switch pulse input end; then, generating two front and back pulses at the No. 1 or gate, wherein the two front and back pulses are respectively used for the related data latch of the No. 1 latch; the 1 st phase inverter, the 1 st AND gate, the 2 nd OR gate and the 1 st register form a sampling hold device, when starting to input pulses to the initial switch pulse input end, the 1 st register samples, the data output end of the 1 st register starts to output high level, after finishing inputting high level pulses to the initial switch pulse input end, the 1 st latch is changed from the sampling state to the latch state, the data output end of the 1 st latch can still keep the high level unchanged until the finishing switch pulse input end receives the high level, the 1 st latch enters the sampling state again, samples the low level received at the 1 st input end of the 1 st AND gate, the data output end of the 1 st latch outputs the low level, after finishing inputting high level pulses to the finishing switch pulse input end, the 1 st latch is changed to the latch state again, and the data output end keeps outputting the low level; and then, splicing the high level pulse output by the data output end of the 1 st register and the pulse output by the end switch pulse input end on a time domain by utilizing a 3 rd OR gate, and finally obtaining a long pulse with a rising edge superposed with the rising edge of the pulse input to the start switch pulse input end, a falling edge superposed with the falling edge of the pulse input to the end switch pulse input end and a high level time length equal to the sum of the mutual delay time of the rising edges of the two input pulses and the high level time length of the pulse input to the end switch pulse input end at the output end of the OR gate, namely the switch pulse transmission output end of the circuit 3, and obtaining an inverted signal of the long pulse at the switch pulse transmission inverted output end.

Specifically, firstly, a high level is input to a signal transmission control timing input end int _ sw _ ctrl <0:k/2-1> of a circuit 4 through a control circuit 2, and a low level is input to int _ sw _ ctrl < k/2:k-1>, at this time, 0-0 (k/2-1) driver keeps normal buffer output, and k/2-k-1 drivers enter a high-impedance state, it can be considered that an output end of the k/2 driver is disconnected from a single-tap data output end of the circuit 4, meanwhile, under the control of the circuit 2, 0-1, … …, and (j-1) column stage circuit output switches are sequentially closed and then disconnected, and the closing processes are not overlapped with each other, the 0-th, 1, … …, and (j-1) column stage circuit signal input end col _ in _ 0:j in the circuit 4 sequentially enter a single-tap data output end chain of the circuit 4, and finally, the data of the single-tap data chain (k-1, 3236, and the data chain is finally completed through the driver; then the control circuit 2 makes the signal transmission control timing input end int _ sw _ ctrl <0> of the circuit 4 become low level, int _ sw _ ctrl <1:k/2-1> keeps high level, int _ sw _ ctrl < k/2:k-1> keeps low level, at this time, the 0 th driver is in high impedance state, which can be seen that the output end is cut off, the 1 st to (k/2-1) drivers keep normal buffer output, the k/2 nd to (k-1) th drivers keep high impedance state, meanwhile, under the control of the circuit 2, the data input to the j (j + 1), … …, (2 j-1) column stage circuit signal input end col _ data _ in < j, j +1, …,2j-1> in the circuit 4 sequentially enter the gate driver chain of the circuit 4, and finally the three-state tap data output is completed through the 1 st to (k/2-1) driver output end; then the control circuit 2 makes the signal transmission control time input end int _ sw _ ctrl <1> of the circuit 4 become low level, int _ sw _ ctrl <0> keeps low level, int _ sw _ ctrl <2:k/2-1> keeps high level, int _ sw _ ctrl < k/2:k-1> keeps low level … … and so on until the control circuit 2 makes the signal transmission control time input end int _ sw _ ctrl < k/2-2> of the circuit 4 become low level, int _ sw _ ctrl <0,1, …, k/2-2> keeps low level, int _ sw _ ctrl < k/2-1> keeps high level, int _ sw _ ctrl < k/3924 xzft 1> keeps low level, int _ sw _ ctrl < k/3924-1 > keeps low level, int _ sw _ ctrl < k/35j < 2-1> completes the process of single-stage data output from the circuit 4, int _ sw _ ctrl < k/35j-1- > output, and the data input end of the circuit 4 + j-3-n-3, and the data output process of the single stage of the circuit 1-3-1; then, int _ sw _ ctrl <0:k/2-1> is kept at a low level, int _ sw _ ctrl < k/2> becomes a high level, int _ sw _ ctrl < k/2+1 is kept at a low level, at this time, it can be regarded that the output end of the (k/2-1) th driver is disconnected from the single-tap data output end, the output end of the k/2 th driver restores the connection to the single-tap data output end, and the output end of the (k/2+1) driver is disconnected from the external connection, at this time, the process that the data of the signal input end col _ data _ in < n/2,n/2+1, … and n/2+j-1> of the circuit 4 columns of circuits are sequentially output from the single-tap data output end is completed; then int _ sw _ ctrl <0:k/2-1> is kept at a low level, int _ sw _ ctrl < k/2> is kept at a high level, int _ sw _ ctrl < k/2+1> is changed into a high level, int _ sw _ ctrl < k/2+ k/1 > is kept at a low level, and the process that data of signal input ends col _ data _ in < n/2+ j, n/2+ j +1, …, n/2+2j-1> of the 4-column stage circuit of the circuit are sequentially output from the single-tap data output end is completed; and so on, until int _ sw _ ctrl <0:k/2-1> is kept at low level, int _ sw _ ctrl < k/2:k-2> is kept at high level, int _ sw _ ctrl < k-1> becomes high level, the process that the data of the column stage circuit signal input terminals col _ data _ in < n-j, n-j +1, …, n-1> of the circuit 4 are sequentially output from the single tap data output terminal is completed, thereby the process that all the column stage circuit signal input terminals data in the circuit 4 are output from the single tap data output terminal thereof is completed, and the relevant time sequence is input to the circuit 2 again to repeat the process.

In a preferred embodiment of the present invention, this embodiment is intended to illustrate the operation of the circuit 1 in conjunction with an actual operating scenario, where, assuming that m =4, n =32, k =8, then j =4, meaning that the circuit 1 in this embodiment supports a 4-bit wide output, including 4 circuits 4; each circuit 4 is provided with 32 column circuit signal input ends, one driver is arranged at every 4 column circuit signal input ends, and the total number of the drivers is 8; there are 32 flip-flops in

circuit

2 and 7 in circuit 3.

The circuit diagram used in the preferred embodiment is shown in fig. 6, and the timing diagram used by the circuit 6 is shown in fig. 7. The circuit 6 includes 32 4-bit pulse counters 601, 602, 603, which are 0,1, … …,31, in addition to the various circuits included in the circuit 1, and count the number of pulses of the input clock pulse signal and output the count result, which is usually the last step of the operation of some types of analog-to-digital converters. The pulse counter comprises a counting pulse input end count _ in, a reset signal input end count _ rst and a counting result output end bus count _ out <3:0>, in the circuit 6, the counting pulse input ends of the 0 th to the 31 th pulse counters are respectively connected with the 0 th to the 31 th counting pulse input ends 610, 611 and 612 of the circuit 6, and the reset signal input ends of all the counters are connected with the pulse counter reset signal input end 613 of the circuit 6; the count result output terminals count _ out <0> of the 0 th to 31 th pulse counters count 32 nets in total, are connected to the column circuit signal input terminal col _ data _ in <0> of the 0 th signal transmission circuit 606 as a bus in a one-to-one correspondence, the count result output terminals count _ out <1> of the 0 th to 31 th pulse counters count 32 nets in total, are connected to the column circuit signal input terminal col _ data _ in <0> of the 1 st signal transmission circuit 607 as a bus in a one-to-one correspondence, and are … …, and so on, so as to complete the connection of the count result output terminals of the pulse counters to the respective circuits 4. The single-tap data output terminals of the 0 th to 3 rd signal transmission circuits 606, 607, 608, 609 serve as the 0 th to 3 rd single-tap

data output terminals

614, 615, 616, 617 of the circuit 6, the clock signal input terminal of the enable pulse generation circuit 604, i.e., the circuit 2, serves as the clock signal input terminal 618 of the circuit 6, the enable pulse signal input terminal of the enable pulse generation circuit 604, i.e., the circuit 2, serves as the enable pulse signal input terminal 619 of the circuit 6, and the timing generation circuit 605 serves as a bridge between the enable pulse generation circuit 604 and the signal transmission circuits 606, 607, 608, 609.

Based on the digital driving circuit of the preferred embodiment, the corresponding driving method includes the following steps:

firstly, inputting reset low-level pulses to a reset signal input end of a counter in a circuit 6 to clear the output of the counter, then inputting clock pulse signals with the same or unequal pulse numbers to a counting pulse input end of each counter, wherein the pulse numbers are instantly reflected on a counting result output end bus of each counter, and when the pulses are not input any more, the final counting result is kept on the counting result output end bus of each counter; signals shown as waveforms in fig. 7 are input to a clock signal input end and an enable pulse signal input end of the circuit 6, that is, waveforms of a column stage circuit output switch control signal col _ sw _ en and a signal transmission control timing signal int _ sw _ ctrl shown in fig. 7 are obtained sequentially according to the principle described above, where col _ sw _ en controls the column stage circuit output switches in each circuit 4, data at the signal input end of each column stage circuit is sequentially released to a signal transmission driver chain in the circuit 4, and int _ sw _ ctrl ensures that signal transmission does not conflict if the output state of each tri-state gate driver in the synchronous control circuit 4 is a high-resistance state or no; the data of the bus at the output end of each counter counting result can be obtained sequentially by the bus col _ data _ out <3:0> at the single-tap data end of the circuit 6, and each data is maintained for one clock cycle. As shown in fig. 7, assuming that the numbers finally obtained by counting by the 0 th, 1 th and 31 th counters are 6 (binary 0110), 9 (binary 1001) and 12 (binary 1100), respectively, when col _ sw _ en <0> is at a high level, binary data 0110 is obtained in col _ data _ out <3:0>, and when col _swu _ sw _ en < -1> is at a high level, binary data 1001 is obtained in col _ data _ out <3:0>, and when col _swu _ sw < -31 > is at a high level, binary data 1100 is obtained in col _ data _ out <3:0 >.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A digital signal drive circuit with multi-channel input and single-channel output comprises an enable pulse generation circuit, a time sequence generation circuit and m signal transmission circuits; the enabling pulse generating circuit is characterized by comprising a clock signal input end, an enabling pulse signal input end and n column-level circuit output switch control signal output ends; the time sequence generating circuit is provided with k column level circuit output switch control signal input ends and k signal transmission control time sequence output ends; each signal transmission circuit is provided with n column-level circuit signal input ends, n column-level circuit output switch control signal input ends, k signal transmission control time sequence input ends and a single tap data output end; n/k = j; n, k, j and m are positive integers, and n and k are even numbers;

the n column level circuit signal input ends of each signal transmission circuit are in one-to-one correspondence to serve as n column level circuit signal input end buses of the digital signal driving circuit; the single tap data output ends of the m signal transmission circuits are used as m single tap data output ends of the digital signal driving circuit one by one; the k signal transmission control time sequence output ends of the time sequence generating circuit are connected with the k signal transmission control time sequence input ends of each signal transmission circuit in a one-to-one correspondence manner; a clock signal input end and an enable pulse signal input end of the enable pulse generating circuit are respectively used as a clock signal input end and an enable pulse signal input end of the digital signal driving circuit; the output switch control signal output ends of the n column-level circuits of the enabling pulse generating circuit are connected with the output switch control signal input ends of the n column-level circuits of the m signal transmission circuits in a one-to-one correspondence manner; and the output switch control signal output ends of the k column stage circuits of the enabling pulse generating circuit are connected to the output switch control signal input ends of the k column stage circuits of the time sequence generating circuit in a one-to-one correspondence mode.

2. The multi-channel input single-channel output digital signal driving circuit according to claim 1, wherein the enable pulse generating circuit comprises n cascaded D flip-flops, and the Q output terminal of the previous D flip-flop is connected to the D input terminal of the next D flip-flop; the clock input ends of the n D triggers are connected to the same clock signal input end, wherein the D input end of the foremost D trigger is connected with the enabling pulse signal input end, and the Q output ends of the n D triggers are respectively used as output switch control signal output ends of the n column-level circuits.

3. A multi-channel input single-channel output digital signal driving circuit according to claim 1, wherein the timing generation circuit comprises (k-1) cascaded timing generation sub-circuits; each timing sub-circuit has a start switch pulse input, an end switch pulse input, a switch pulse transfer output, and a switch pulse transfer inverted output; the switching pulse transmission output end of the previous time sequence generation sub-circuit is connected to the initial switching pulse input end of the next time sequence generation sub-circuit to form a cascade circuit; the switching pulse transmission output ends of the 0 th to (k/2-1) th time sequence generation sub-circuits are sequentially connected with the first k/2 signal transmission control time sequence output ends, and the switching pulse transmission inverted output ends of the (k/2-1) th to (k-2) th time sequence generation sub-circuits are sequentially connected with the last k/2 signal transmission control time sequence output end; the starting switch pulse input end of the 0 th time sequence generation sub-circuit and the ending switch pulse input end of the 0 th to (k-2) th time sequence generation sub-circuits are sequentially connected with the output switch control signal input ends of the k column level circuits.

4. The multi-channel input single-channel output digital signal driving circuit according to claim 3, wherein the timing generation sub-circuit comprises two inverters, three OR gates, an AND gate and a latch; the input end of the 1 st inverter is connected with the ending switch pulse input end of the timing sequence generation sub-circuit, and the output end of the 1 st inverter is connected with the 1 st input end of the 1 st AND gate; the 2 nd input end of the 1 st AND gate is connected with the data output end of the 1 st latch, and the output end of the 1 st AND gate is connected with the 2 nd input end of the 2 nd OR gate; the 1 st input end of the 2 nd OR gate is connected with the initial switch pulse input end of the timing sequence generation sub-circuit, and the output end of the 2 nd OR gate is connected with the data input end of the 1 st latch; the latch pulse input end of the 1 st latch is connected with the output end of the 1 st OR gate; the 1 st input end of the 1 st OR gate is connected with the initial switch pulse input end of the time sequence generation sub-circuit, and the 2 nd input end of the 1 st OR gate is connected with the ending switch pulse input end of the time sequence generation sub-circuit; the 1 st input end of the 3 rd OR gate is connected with the ending switch pulse input end of the time sequence generating sub-circuit, the 2 nd input end of the 3 rd OR gate is connected with the data output end of the 1 st latch, and the output end of the 2 nd OR gate is connected with the switch pulse transmission output end of the time sequence generating sub-circuit and the input end of the 2 nd inverter; and the output end of the 2 nd inverter is connected with the switching pulse transmission inverting output end of the timing generation sub-circuit.

5. A multi-channel input single-channel output digital signal driving circuit according to claim 1, wherein the signal transmission circuit includes k digital signal drivers with tri-state gates and n column stage circuit output switches, in the 0 th to (k/2-1) th drivers, the output terminal of the previous driver is connected to the input terminal of the next driver, in the (k/2-1) th to (k-1) th drivers, the input terminal of the previous driver is connected to the output terminal of the next driver, the input terminal of each driver is connected to the output terminals of the j column stage circuit output switches, and the state control terminal of the 0 th to (k-1) th drivers is connected to the k signal transmission control timing input terminals of the signal transmission circuit; the signal input ends of 0 th to (n-1) th column-level circuits of the signal transmission circuit are sequentially connected with the input ends of 0 th to (n-1) th column-level circuit output switches, wherein the output end of the (k/2-1) th driver is connected with the single-tap data output end of the signal transmission circuit.

6. A multi-channel input single-channel output digital signal driving method for implementing a multi-channel input single-channel output digital signal driving circuit according to any one of claims 1 to 5, the method comprising:

the k column-level circuit output switch control signals are output to the time sequence generating circuit and are used for generating time sequences for controlling the opening and closing of the k driver related switches in each signal transmission circuit, and the generated time sequences are output to the signal transmission control time sequence input end of each signal transmission circuit from the k signal transmission control time sequence output ends of the time sequence generating circuit;

when a clock cycle is finished, keeping the input clock of the enabling pulse generating circuit unchanged, sending a pulse with the high level length of one clock cycle and capable of being identified by a clock trigger edge to the enabling pulse signal input end of the enabling pulse generating circuit again, namely repeating the process; the pulse width of each column stage circuit data is one clock cycle, and a large cycle, namely n clock cycles, is needed for finishing the data output of all columns.

7. The method of claim 6, wherein the enabling pulse generating circuit is operated by:

a clock is input at a clock signal input end of an enabling pulse generating circuit, and a pulse which has a high level length of one clock cycle and can be identified by a clock trigger edge is input at the enabling pulse signal input end; after a certain time delay occurs after the time of a clock triggering edge, a 0 th trigger of the enabling pulse generating circuit outputs a pulse with a high level length of one clock period at the Q output end, the pulse is used as a signal of an output switch control signal output end of the column level circuit to be output outwards, and simultaneously the pulse is input at the D input end of a 1 st trigger, and the clock triggering process is repeated; the pulse is transmitted through a trigger in the enabling pulse generating circuit until the output end of the output switch control signal of the last column stage circuit outputs a pulse at the nth clock cycle, and the operation process of a large cycle is finished.

8. The method of claim 6, wherein the operation of the timing generation circuit comprises:

the method comprises the steps that pulses with high level duration being one clock cycle are respectively input into a 0 th column level circuit output switch control signal input end and a (j-1) th column level circuit output switch control signal input end of a time sequence generating circuit, the pulses are processed by a 0 th time sequence generating sub-circuit, a pulse with rising edge coinciding with the rising edge of an input pulse of the 0 th column level circuit output switch control signal input end, falling edge coinciding with the falling edge of an input pulse of a (j-1) th column level circuit output switch control signal input end and high level width being j clock cycles is generated at a switch pulse transmission output end of the 0 th time sequence generating sub-circuit, the pulses are output from a signal transmission control time sequence output end of the time sequence generating circuit, are used for controlling corresponding switches in the signal transmission circuit and are simultaneously input into a starting switch pulse input end of the 1 st time sequence generating sub-circuit; repeating the above processes, inputting a pulse with a high level duration of one clock cycle at the ending switch pulse input end of the 1 st to (k/2-1) th time sequence generating sub-circuits in sequence, and using the switch pulse transmission output end of the 1 st to (k/2-1) th time sequence generating sub-circuits in the time sequence generating circuit as the 1 st to (k/2-1) th signal transmission control time sequence output end of the time sequence generating circuit to respectively output a pulse with a rising edge coinciding with the rising edge of the input pulse at the output switch control signal input end of the 0 th column level circuit, a falling edge coinciding with the rising edge of the input pulse at the output switch control signal input end of the (2 j-1), (3 j-1), …, and (n/2-1) column level circuit to output pulses with falling edges coinciding with high level widths of 2j, 3j, … … and n/2 clock cycles;

outputting a signal which is in the opposite phase with the switch pulse transmission output end of the (k/2-1) th time sequence generation sub-circuit at the switch pulse transmission output end, wherein the rising edge of the signal coincides with the falling edge of the (k/2-1) th transmission control time sequence output end of the time sequence generation circuit, the falling edge of the signal coincides with the rising edge of the pulse received by the output switch control signal input end of the column-level circuit in the next large period, the high level width of the signal is at least n/2 clock periods, and the signal is output as the (k/2) th signal transmission control time sequence output end of the time sequence generation circuit; repeating the above process, inputting pulses with high level duration of one clock cycle into the output switch control signal input ends of the kth/2 to (k-2) column level circuits of the time sequence generating circuit in sequence, after the pulses are processed by the kth/2 to (k-2) time sequence generating sub-circuits, respectively, outputting rising edges from the switch pulse transmission inverting output ends of the input switches, namely the output switch control signal input ends of the column level circuits of the time sequence generating circuit, overlapping the falling edges of the pulses received by the output switch control signal input ends of the column level circuits, and overlapping the rising edges of the pulses received by the output switch control signal input ends of the 0 th column level circuit of the next large cycle, wherein the high level widths are at least (n/2-j), (n/2-2 j), … … and j clock cycles, and ending the operation process of one large cycle.

9. The method of claim 8, wherein the operation of the timing generation sub-circuit comprises:

pulses with certain high level duration are respectively input at a starting switch pulse input end and an ending switch pulse input end of the time sequence generating sub-circuit, the high level parts of the two pulses are not overlapped, and the pulse input to the ending switch pulse input end reaches the time sequence generating sub-circuit later than the pulse input to the starting switch pulse input end; then, generating two front and back pulses at the 1 st OR gate, wherein the two front and back pulses are respectively used for the relevant data latch of the 1 st latch; the 1 st phase inverter, the 1 st AND gate, the 2 nd OR gate and the 1 st register form a sample hold device, when starting to input pulses to the initial switch pulse input end, the 1 st register samples, the data output end of the 1 st register starts to output high level, after finishing inputting high level pulses to the initial switch pulse input end, the 1 st latch is changed into a latch state from the sampling state, the data output end of the 1 st latch can still keep the high level unchanged until the finishing switch pulse input end receives the high level, the 1 st latch enters the sampling state again, samples the low level received at the 1 st input end of the 1 st AND gate, the data output end of the 1 st latch outputs the low level, after finishing inputting high level pulses to the finishing switch pulse input end, the 1 st latch is changed into the latch state again, and the data output end keeps outputting the low level; and then, splicing the high-level pulse output by the data output end of the 1 st register and the pulse output by the end switch pulse input end on a time domain by utilizing a 3 rd OR gate, finally obtaining a long pulse with a rising edge superposed with the rising edge of the pulse input to the start switch pulse input end, a falling edge superposed with the falling edge of the pulse input to the end switch pulse input end and a high-level time length equal to the sum of the mutual delay time of the rising edges of the two input pulses and the high-level time length of the pulse input to the end switch pulse input end at the output end of the OR gate, namely the switch pulse transmission output end of the time sequence generation circuit, and obtaining an inverted signal of the long pulse at the switch pulse transmission inverted output end.

10. The method of claim 6, wherein the signal transmission circuit operates according to a process comprising:

the state control end of a tri-state gate of the signal transmission circuit keeps normal buffer output when receiving high level, and the output end is in a high-impedance state when receiving low level;

controlling the time sequence generating circuit to input high level to a 0 th to a (k/2-1) th signal transmission control time sequence input end of the signal transmission circuit through controlling the enabling pulse generating circuit, and inputting low level to a k/2 th to a (k-1) th drivers, wherein the 0 th to the (k/2-1) th drivers keep normal buffer output, and the k/2 th to the (k-1) th drivers enter a high-impedance state, and the output end of the k/2 th driver is considered to be disconnected with a single-tap data output end of the signal transmission circuit; meanwhile, under the control of an enabling pulse generating circuit, 0 to (j-1) th column level circuit output switches in the signal transmission circuit are sequentially closed and then are opened, the closing processes are not overlapped, data input to the 0 to (j-1) th column level circuit signal input ends in the signal transmission circuit sequentially enter a digital signal driver of a three-state gate of the signal transmission circuit, and finally reach a single-tap data output end through the 0 to (k/2-1) th drivers to complete data output;

the process that the data of the signal input end of all the column level circuits in the signal transmission circuit is output from the single-tap data output end of the signal input end is finished by sequentially controlling the enable pulse generation circuit to enable the 0 th to the (k-1) th signal transmission control time sequence input end of the signal transmission circuit to input high level or low level.