CN109411461A - The spuious balanced substrate of gate pole and its power semiconductor modular - Google Patents
The spuious balanced substrate of gate pole and its power semiconductor modular Download PDFInfo
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- CN109411461A CN109411461A CN201711322063.9A CN201711322063A CN109411461A CN 109411461 A CN109411461 A CN 109411461A CN 201711322063 A CN201711322063 A CN 201711322063A CN 109411461 A CN109411461 A CN 109411461A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
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- 230000005611 electricity Effects 0.000 claims description 6
- 238000009434 installation Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 19
- 230000008878 coupling Effects 0.000 description 9
- 238000010168 coupling process Methods 0.000 description 9
- 238000005859 coupling reaction Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 230000000875 corresponding effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 238000007323 disproportionation reaction Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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Abstract
The invention discloses a kind of spuious balanced substrate of gate pole and its power semiconductor modulars.Including four power potential regions and three auxiliary potential regions, multiple power switch are housed on first, third power potential region, each power switch is made of multiple power semiconductor chips, and multiple power semiconductor chips are in parallel and are connected on adjacent power potential region；The second auxiliary potential region is equipped between first, second power potential region between third, the 4th power potential region, the first auxiliary potential region is equipped between upper first auxiliary potential region and first or third power potential region in a second direction, it is equipped with third between the second, first power potential region and between third, the first power potential region and assists potential region, is electrically connected between second, third auxiliary potential region.Compared with prior art, the advantage of power semiconductor modular provided by the invention is that the control loop stray parameter of each chip of power switch can be made uniform.
Description
Technical field
The present invention relates to a kind of substrate and power semiconductor modulars, are especially equipped with multiple power more particularly to one kind
The substrate of semiconductor chip and power semiconductor modular including such substrate and power semiconductor chip.
Background technique
The through-current capability of single power semiconductor chip is limited, is the power handling capability of extended power semiconductor module,
The arrangement composition bridge arm switch of multi-chip parallel connection is generallyd use inside the power semiconductor modular of large capacity.Parallel arrangement
The switch of chip is usually controlled by a control terminal, switching circuit can be indicated by following model.
Cgs1 in Fig. 1, Cgs2, Cgs3 respectively represent the grid capacitance of three pieces of power semiconductor chips in parallel, power half
Voltage in the through-current capability and grid capacitance of conductor chip is positively correlated.Tg and Ts is respectively power semiconductor modular and external drive
The port of dynamic circuit connection, for receiving driving signal.Rg0 and Lg0 is respectively the driving circuit common portion of every piece of chip
Stray resistance and stray inductance.Rg1, Lg1, Rg2, Lg2 and Rg2, Lg3 are respectively three pieces of power semiconductor chips because of position distribution
Caused individual stray resistance and stray inductance.In power semiconductor modular opening process, the driving that is added on Tg and Ts
Voltage becomes positive value by specific negative value, and due to the effect of driving circuit stray parameter, the voltage at grid capacitance both ends rises, from
And make to rise by the power current of power semiconductor chip；In turn off process, the driving voltage on Tg and Ts is added in by specific
Positive value become negative value, the voltage decline at grid capacitance both ends, to make to decline by the power current of power semiconductor chip.
If the individual stray parameter of parallel chip is inconsistent, it will lead to gate capacitance charges or the velocity of discharge be inconsistent, so as to cause
Pass through the unevenness of the power current of chip in switching process.Since the foundation of the voltage at semiconductor chip both ends in switching process is logical
It is often before curent change, it is inconsistent that non-uniform transient current will lead to the loss generated on power semiconductor chip, most
Be reflected in eventually chip chamber temperature it is inconsistent on.In the case where power semiconductor modular full power operation, because of chip current point
The excessively mild overcurrent that cloth unevenness causes may cause the failure of semiconductor element, influence the normal operation of module.
It can be seen that from described above, influencing the inconsistent reason of parallel chip switching speed is mainly internal stray parameter
Inconsistent, stray parameter mainly considers the influence of stray inductance and equivalent resistance.Wherein, the stray resistance of every piece of chip includes public affairs
The stray resistance of the stray resistance of part and itself driving path altogether.Stray inductance then includes the self-induction of common portion and itself drives
The self-induction and loop of power circuit in dynamic path are coupled to the mutual inductance of driving circuit.Therefore, it needs to minimize because of core when module design
The difference of piece itself the driving inconsistent bring stray parameter in path.
If power semiconductor chip fails, gate capacitance may be caused short-circuit, and because coupling device of power welds
The chip failing that burns at place shows as open circuit to module.Due to driving power power limited, short-circuit gate capacitance can be dragged down
The grid voltage of the chip in parallel with failure chip.If the voltage is lower than the threshold voltage that power semiconductor is opened, can
Cause to turn off with the mistake of these devices, to influence the normal work of module.
Summary of the invention
Consider above-mentioned technical essential, the present invention provides a kind of spuious balanced substrate of gate pole and its power semiconductor modular,
The difference of driving circuit stray parameter caused by reducing because of chip space position distribution avoids the mistake shutdown of normal chip,
Improve the reliability of power semiconductor modular.
The technical solution adopted by the present invention is that:
The present invention protects a kind of substrate, and specific structure is as follows:
Including four power potential regions and three auxiliary potential regions, four power potential regions are successively arranged for interval
The second power potential region, the first power potential region, third power potential region, the 4th power potential region；
Multiple power switch are mounted on the first power potential region and third power potential region, each power is opened
Pass is made of multiple power semiconductor chips, and multiple power semiconductor chips are parallel with one another and connected by coupling device of power
Onto the power potential region adjacent with power potential region where itself；
Between first power potential region and the second power potential region and third power potential region and the 4th power
The second auxiliary potential region is equipped between potential region, in a second direction upper first auxiliary potential region and the first power potential area
The first auxiliary potential region being correspondingly connected with each power switch is equipped between domain or third power potential region, first is auxiliary
Potential region is helped to be connected to the second auxiliary potential region；
Between the second power potential region corner and the first power potential region and the corner of third power potential region
And first be equipped with third between power potential region and assist potential region, the second auxiliary potential region and third assist potential region
Between be electrically connected by second, third auxiliary connecting device, the coordination electrode of each power switch it is corresponding first auxiliary
Potential region is electrically connected by the first auxiliary connecting device.
The mounting arrangements direction of the second direction is consistent.
First auxiliary potential region be arranged in corresponding power switch or second direction it is reversed be aligned place, and make
Obtain the first power potential region of the first auxiliary potential region and power semiconductor chip bottom, third power potential region is insulated
In the case where as close as possible to.
Second auxiliary connecting device and third auxiliary connecting device all have two junctions, and the first junction is located at
On second auxiliary potential region, the second junction is located on third auxiliary potential region.
For passive element, a kind of passive element is arranged in parallel along first direction, first direction and power switch
Mounting arrangements direction it is perpendicular.In this case, passive element and the link position of the second auxiliary potential region are auxiliary by second
The position of the first junction of attachment device is helped to determine, specifically: the first junction of the second auxiliary connecting device of distance is nearest
Two passive elements be connected to the second auxiliary potential region along away from the first junction direction, remaining passive element is along close to the
One junction direction is connected to the second auxiliary potential region.
For passive element, passive element described in another kind is arranged along perpendicular to first direction, first direction and power
The mounting arrangements direction of switch is perpendicular.In this case, passive element both ends be connected respectively to the second auxiliary potential region and
Between third power potential region, in the first auxiliary potential area between the first auxiliary connecting device and passive element
Middle position setting recess notch.
The second power potential region and the 4th power potential region are equipped with indent engraved structure, the second auxiliary electricity
Being equipped with for gesture region extends into the extended segment among indent engraved structure, and the first junction is arranged in extended segment end.
First junction is located at all power switch along the middle position for being parallel to second direction.
The passive element is resistance, capacitor, inductance, and the element with fuse function.
The auxiliary connecting device is the element with linkage function such as metal material connecting line, resistance or inductance.
The power semiconductor chip is Metal Oxide Semiconductor Field Effect Transistor, has reverse parallel connection afterflow two
The insulated gate bipolar transistor of pole pipe, high electron mobility transistor, with the metal oxygen for having reverse parallel connection freewheeling diode
Compound semiconductor field effect transistor and junction field effect transistor,
The chip material can be silicon, silicon carbide, gallium nitride etc..
The present invention also protects a kind of power semiconductor modular comprising the substrat structure.
The present invention is using beneficial effect:
The present invention increases the accounting of common portion stray parameter by using attachment device, arranges additional resistance or inductance
Element and setting member placing direction, the difference of driving circuit stray parameter caused by reducing because of chip space position distribution.
While it is of the invention because resistance or inductance element have fuse function, it can be kept away in the case where one single chip fails
The mistake shutdown for exempting from normal chip, improves the reliability of module.
Detailed description of the invention
Fig. 1 is the switching circuit figure of existing power semiconductor chip.
Fig. 2 is the top view of the single substrate of power semiconductor modular described in the embodiment of the present invention 1.
Fig. 3 is the local top view of driving circuit on power semiconductor modular substrate described in embodiment 1.
Fig. 4 is the equivalent circuit of driving circuit described in embodiment 1.
Fig. 5 is the top view of the single substrate of power semiconductor modular described in embodiment 2.
Table 1 shows the simulation result of every piece of chip drives loop stray inductance under a design example.
In figure: power potential region 10,11,12,13, power switch 20, coupling device of power 30, power terminal element
41,42,43, direction 51,52, auxiliary potential region 60,61,62, auxiliary connecting device 70,71,72, control terminal element 81,
82。
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.
As shown in Figures 2 and 3, the substrate 1 of the specific embodiment of the invention 1 include four power potential regions 10,11,12,
13 and three auxiliary potential regions 60,61,62, four power potential regions 10,11,12,13 are successively spaced apart second
Power potential region 11, the first power potential region 10, third power potential region 12, the 4th power potential region 13；Power
Potential region 10,11,12,13 and auxiliary potential region 60,61,62 are actually one layer of metal layer.
Multiple power switch 20 are mounted on the first power potential region 10 and third power potential region 12, each
Power switch 20 is made of multiple power semiconductor chips, and multiple power semiconductor chips are parallel with one another and connected by power
Device 30 is connected on the power potential region adjacent with power potential region where itself.
Between first power potential region 10 and the second power potential region 11 and third power potential region 12 and
The second auxiliary potential region 61 is equipped between four power potential regions 13, in a second direction the first auxiliary 60 He of potential region on 52
The be correspondingly connected with each power switch 20 is equipped between first power potential region 10 or third power potential region 12
One auxiliary potential region 60, the first auxiliary potential region 60 are connected to the second auxiliary potential region 61 through passive element 80, and first
Mutual be electrically connected is realized by passive element 80 with the second auxiliary potential region 61 in auxiliary potential region 60.
Between 11 corner of the second power potential region and the first power potential region 10 and third power potential region
It is equipped with third between 12 corners and the first power potential region 10 and assists potential region 62, the second auxiliary potential region 61 and third
It assists being electrically connected between potential region 62 by second, third auxiliary connecting device 71,72, the control electricity of each power switch 20
The first extremely corresponding auxiliary potential region 60 is electrically connected by the first auxiliary connecting device 70.
Multiple power potential regions 10~13 and the multiple power switch 20 installed thereon in the present invention, in the following ways
Arrangement:
First power potential region 10, power switch 20 are mounted on first power potential region by its bottom
10；It is disposed with multiple power switch 20 in specific implementation on the first power potential region 10, multiple power switch 20 are along parallel
It is arranged in a linear arrangement in first direction 51.
Second power potential region 11 is arranged in by the first power potential region 10, second direction 52 it is reversed it is upper with
First power potential region 10 is adjacent, and passes through the power switch on coupling device of power 30 and the first power potential region 10
The power electrode at 20 tops is connected.
Third power potential region 12 is arranged in by the first power potential region 10, in second direction 52 with the first function
Rate potential region 10 is adjacent, and passes through 20 top of power switch on coupling device of power 30 and the first power potential region 10
Power electrode be connected.
Third power potential region 12, power switch 20 are mounted on third power potential region 12 by its bottom
On；It is disposed with multiple power switch 20 in specific implementation on third power potential region 12, multiple power switch 20 are along parallel
It is arranged in a linear arrangement in first direction 51.
4th power potential region 13 is arranged in by the first power potential region 10, in second direction 52 with third function
Rate potential region 12 is adjacent, and passes through coupling device of power 30 and the power switch 20 on third power potential region 12
The power electrode at top is connected.
The present invention reduces commutation circuit area by the configuration of above-mentioned commutation circuit, to reduce whole stray inductance.
First power potential region 10 in a first direction 51 and first direction 51 it is reversed on protrude from third power electricity
First extended structure in gesture region 12 and the 4th power potential region 13, extended structure make the first power potential region 10 first
Direction 51 and first direction 51 it is reversed on protrude from third power potential region 12 and the 4th power potential region 13, and
One extended structure protrude from the part of third power potential region 12 and the 4th power potential region 13 again in a second direction 52 to
Third power potential region 12 and the 4th power potential region 13 extend to form the second extended structure, and development length at least makes to extend
Part is more than third power potential region 12；Also, extended structure protrudes from third power potential region 12 and the 4th power electricity
Second direction 52 extends to the second power potential region 11 again for the part in gesture region 13.
By the setting of above-mentioned extended structure, so that the current direction flowed through on extended structure and its inside flow through the first gold medal
Belong to the contrary of the cut-off current of coating 10, third metal backing 12 and the 4th metal backing 13, the magnetic field of generation can be mutual
It offsets, further decreases the stray inductance of commutation circuit entirety.The extended structure of 52 arrangements in a second direction of two sides provides
Two symmetrical commutation circuits can help to reduce each core for the power semiconductor chip along 51 lateral arrangement of first direction
The difference in change of current path caused by piece is distributed due to spatial position, to reduce the difference of each chip stray inductance.
As shown in Figure 2, the present invention is equivalent to half-bridge topology, and upper and lower bridge arm is respectively by two rows of power mounted thereto
Semiconductor chip 20 forms, and each row's chip is parallel with one another.
For forming the power semiconductor chip 20 of upper bridge arm, the power electrode of bottom is directly welded at positive electrode potential area
Metal backing 10 on, top power electrode by coupling device of power 30 be connected to exchange potential area 11 He of metal backing
12, coordination electrode is located at the top of chip.The control terminal 81,82 of bridge arm is set to 11 right side of metal backing, control terminal in module
Son 82 is set up directly on metal backing 11, provides reference potential for control terminal 81.
For forming the power semiconductor chip 20 of lower bridge arm, the power electrode of bottom is directly welded at exchange potential area
Metal backing 12 on, top power electrode is connected to the metal backing 13 in negative potential area by coupling device of power 30, control
Electrode processed is located at chip bottom.The control terminal 81,82 of module lower bridge arm is set to 13 left side of metal backing, and control terminal 82 is straight
It connects and is arranged on metal backing 13, provide reference potential for control terminal 81.Since control terminal 81,82 is away from power semiconductor chip
The distance of piece coordination electrode is inconsistent, and therefore the stray parameter of the control loop of every piece of chip will necessarily generate difference, to lead
The switching speed of parallel chip is inconsistent when module being caused to work, and generated electric current and temperature distributing disproportionation problem may will affect
The reliability service of module.Therefore need to be by particular arrangement, balanced every piece of chip under the premise of not changing control terminal position
Driving circuit stray parameter.
The present invention is with following configuration principle to realize technical goal.
By taking Fig. 3 as an example.Firstly, in the underface of every piece of power semiconductor chip 20 setting auxiliary potential area 60, and be every
Block power semiconductor chip configured length and the consistent auxiliary connecting device 700,701,702,703,704 of diameter, auxiliary connection
Device 700,701,702,703,704 is for connecting auxiliary potential area 600,601,602,603,604 and power semiconductor chip
Coordination electrode, the stray parameter to guarantee this section of path is consistent.Meanwhile auxiliary connecting device 70 with 30 groups of coupling device of power
At plane it is parallel with modular power current direction, therefore the power current that module can be reduced generated on the partial circuit it is mutual
Sense avoids changing the normal switch of the mutual inductance influence of electric potential module generated on driving circuit because of power current.
Secondly, configuration auxiliary connecting device 71 and 72.In specific implementation, the second auxiliary potential region 61 of lower bridge arm and the
Three auxiliary potential regions 62 between by the second auxiliary connecting device 71 be electrically connected, upper bridge arm second auxiliary potential region 61 with
Third assists being electrically connected between potential region 62 by third auxiliary connecting device 72.Second auxiliary connecting device 71 and third are auxiliary
Attachment device 72 is helped to all have two junctions 910, the 911, first junction 910 is located on the second auxiliary potential region 61, and
It is located at the middle position of power semiconductor chip on 51 in a first direction, the second junction 911 is located at 81 place of control terminal
It assists in potential area 62.The setting of first junction 910 is reduced to the difference of every piece of chip drives electrode distance, is conducive to subtract
The unevenness of small stray parameter.
Secondly, arranging the consistent passive element 80 of impedance, passive member on the driving circuit of every piece of power semiconductor chip
Part can be resistance or inductance, and resistance value or inductance value are greater than the stray parameter value in circuit, to reduce unbalanced stray parameter whole
Accounting in a loop stray parameter.
So as to form equivalent circuit structure as shown in Figure 4.
As shown in figure 3, passive element 80 is arranged in parallel along first direction 51, the installation of first direction 51 and power switch 20
Arranged direction is perpendicular；Also, passive element 80 and the link position of the second auxiliary potential region 61 are by the second auxiliary connection dress
The position decision of 71 the first junction 910 is set, specially；First junction 910 of the second auxiliary connecting device of distance 71 is most
Close two passive elements 801,802 are connected to the second auxiliary potential region 61 along away from 910 direction of the first junction, i.e., so that
Two passive elements 801,802 are passive compared with to the first junction 910 with the contact position of the second auxiliary potential region 61
Element 801,802 itself is to the first junction 910 apart from farther；Remaining passive element 800,803,804 is along close to the first connection
Locate 910 directions and be connected to the second auxiliary potential region 61, i.e., so that remaining passive element 800,803,804 and the second assists potential
The contact position in region 61 is to the first junction 910 apart from compared to passive element 800,803,804 itself to the first junction 910
Apart from closer.This configuration can minimize the closer chip in the first junction of distance 910 and distance the first junction 910 is farther away
The difference in length in the driving path of chip, so that the first junction 910 is most to the stray parameter between each chip passive element
Amount is consistent.
In addition, passive element 80 is configured to fuse function, it is short can to there is failure in the gate pole of power semiconductor chip
The driving circuit of the failure chip can be disconnected after the phenomenon of road.Under this kind of failure conditions, because chip failing power electrode with connect
Device weld is burnt, which shows as open circuit to module, thus such configuration can guarantee to failure chip every
From without influencing coordination electrode to the control of normal chip and continuing working for module.
According to the configuration of embodiment, the present invention is implemented to every piece of chip drives loop stray inductance using Ansys software
Q3D software package is emulated, and simulation result is as shown in table 1 below, and along first direction 51, chip number changes from small to big.It can from result
Find out, to the chip for belonging to same bridge arm, the stray inductance difference of driving circuit is no more than 3nH.
Table 1
| Chip position | Stray electrical inductance value (nH) | Chip position | Stray electrical inductance value (nH) |
| Upper bridge arm chip 1 | 15.495 | Lower bridge arm chip 1 | 16.46 |
| Upper bridge arm chip 2 | 15.812 | Lower bridge arm chip 2 | 15.769 |
| Upper bridge arm chip 3 | 16.208 | Lower bridge arm chip 3 | 14.504 |
| Upper bridge arm chip 4 | 16.705 | Lower bridge arm chip 4 | 14.337 |
| Upper bridge arm chip 5 | 18.209 | Lower bridge arm chip 5 | 14.161 |
In upper table, upper bridge arm chip refers to that the power semiconductor chip 20 of bridge arm, lower bridge arm chip are the function of lower bridge arm
Rate semiconductor chip 20.
Embodiment 2
The difference of the present embodiment and embodiment 1 is: auxiliary 60 area of potential area increases, and is provided with sunk structure, nothing
Source element 80 52 is arranged in parallel in a second direction, as shown in Figure 5.The coordination electrode of every piece of chip passes through respective attachment device
700,701,702,703,704 are connected with auxiliary potential area 600,601,602,603,604.Passive element 800,801,802,
803,804 placement directions are parallel with second direction 52.Passive element 80, which is placed in, is correspondingly connected with device 70 along first direction 51
Left or right side.For the equilibrium for guaranteeing every piece of chip controls loop stray inductance, the placement location of passive element 80 is auxiliary by second
The position of the first junction 910 of attachment device 71 is helped to determine, three close passive elements 801 of the first junction of distance 910,
802,803, placement position is far from the first junction 910, two remote passive elements 800,804 of the first junction of distance 910
Its placement position is close to the first junction 910.
It is the most important failure mode of metal backing on substrate 10 because metal backing falls off caused by temperature change, passes through
The mode for increasing potential area single metal blanket area can increase the bond strength of metal backing and underlying substrate, to reduce mistake
Efficiency.
The metal backing for assisting potential area 60 is the smallest metal backing of area on entire substrate 10, and away from fever source chip
80 distances are close, and the temperature change of experience is maximum, it can thus be assumed that the structure is the highest part of crash rate on entire substrate 10.And
The present embodiment increases the face that can arrange auxiliary potential area 60 by way of by passive element 80 in a second direction 52 arrangements
Product, so that auxiliary potential area 60 increases area in arrangement, while in 70 He of auxiliary connecting device in auxiliary potential area 60
Sunk structure is arranged in 80 middle position of passive element, further increases the reliability of metal backing.
To maintain control loop stray inductance equal by optimizing the placement position of passive element 80 for the set-up mode of embodiment 2
Even advantage, while improving the reliability of substrate 10.
It can be seen that the advantage of power semiconductor modular provided by the invention is that the control of each chip of power switch can be made
Loop stray parameter is uniform, and there is it to protrude significant technical effect.
Claims (9)
1. a kind of spuious balanced substrate of gate pole, it is characterised in that:
Including four power potential regions (10,11,12,13) and three auxiliary potential regions (60,61,62), four power electricity
Gesture region (10,11,12,13) be successively spaced apart second power potential region (11), the first power potential region (10),
Third power potential region (12), the 4th power potential region (13)；
Multiple power switch (20) are mounted on the first power potential region (10) and third power potential region (12), often
A power switch (20) is made of multiple power semiconductor chips, and multiple power semiconductor chips are parallel with one another and pass through power
Attachment device (30) is connected on the power potential region adjacent with power potential region where itself；
Between first power potential region (10) and the second power potential region (11) and third power potential region (12) and
The second auxiliary potential region (61) is equipped between 4th power potential region (13), in a second direction the first auxiliary potential on (52)
It is equipped with and each power switch between region (60) and the first power potential region (10) or third power potential region (12)
(20) the first auxiliary potential region (60) being correspondingly connected with, the first auxiliary potential region (60) are connected to the through passive element (80)
Two auxiliary potential region (61)；
Between the second power potential region (11) corner and the first power potential region (10) and third power potential region
(12) third auxiliary potential region (62), the second auxiliary potential region are equipped between corner and the first power potential region (10)
(61) it is electrically connected between third auxiliary potential region (62) by second, third auxiliary connecting device (71,72), each power
The first corresponding auxiliary potential region (60) of the coordination electrode of switch (20) is electrically connected by the first auxiliary connecting device (70)
It connects.
2. a kind of spuious balanced substrate of gate pole according to claim 1, it is characterised in that:
The second direction (52) is consistent with the mounting arrangements direction of power switch (20).
3. a kind of spuious balanced substrate of gate pole according to claim 1, it is characterised in that:
First auxiliary potential region (60) is arranged in and corresponding power switch (20) (52) or second party in a second direction
At the alignment reversed to (52), and make the first power of the first auxiliary potential region (60) and power semiconductor chip bottom electricity
It is close in the case where gesture region (10), third power potential region (12) insulation.
4. a kind of spuious balanced substrate of gate pole according to claim 1, it is characterised in that:
Second auxiliary connecting device (71) and third auxiliary connecting device (72) all have two junctions (910,911),
First junction (910) is located in the second auxiliary potential region (61), and the second junction (911) are located at third auxiliary potential region
(62) on；
The passive element (80) is arranged in parallel along first direction (51), the installation of first direction (51) and power switch (20)
Arranged direction is perpendicular；Also, passive element (80) and the link position of the second auxiliary potential region (61) are connected by the second auxiliary
The position decision of the first junction (910) of connection device (71), specifically:
Three close passive element (801,802,803) edges of the first junction (910) of the second auxiliary connecting device of distance (71)
It is connected to the second auxiliary potential region (61) away from the first junction (910) direction, remaining passive element (800,804) is along close
First junction (910) direction is connected to the second auxiliary potential region (61).
5. a kind of spuious balanced substrate of gate pole according to claim 1, it is characterised in that:
Second auxiliary connecting device (71) and third auxiliary connecting device (72) all have two junctions (910,911),
First junction (910) is located in the second auxiliary potential region (61), and the second junction (911) are located at third auxiliary potential region
(62) on.
6. a kind of spuious balanced substrate of gate pole according to claim 1, it is characterised in that:
The passive element (80) is along perpendicular to second direction (52) arrangement, the peace of second direction (52) and power switch (20)
It is parallel consistent to fill arranged direction；Passive element (80) both ends are connected respectively to the second auxiliary potential region (61) and third power
Between potential region (12), in the first auxiliary connecting device (70) and passive element in first auxiliary potential area (60)
(80) the middle position setting recess notch between.
7. a kind of spuious balanced substrate of gate pole according to claim 1, it is characterised in that:
The second power potential region (11) and the 4th power potential region (13) are equipped with indent engraved structure, and second is auxiliary
Being equipped with for potential region (61) is helped to extend into the extended segment among indent engraved structure, the first junction is arranged in extended segment end
(910)。
8. a kind of spuious balanced substrate of gate pole according to claim 1, it is characterised in that:
First junction (910) is located at all power switch (20) along the middle position for being parallel to second direction (52).
9. a kind of power semiconductor modular, the substrate comprising at least one as described in the claims 1-6 is any.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2017106963904 | 2017-08-15 | ||
| CN201710696390.4A CN107342313A (en) | 2017-08-15 | 2017-08-15 | The spuious balanced substrate of gate pole and its power semiconductor modular |
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| Publication Number | Publication Date |
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| CN109411461A true CN109411461A (en) | 2019-03-01 |
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| CN201710696390.4A Pending CN107342313A (en) | 2017-08-15 | 2017-08-15 | The spuious balanced substrate of gate pole and its power semiconductor modular |
| CN201721723460.2U Active CN207868198U (en) | 2017-08-15 | 2017-12-12 | A kind of spuious balanced substrate of gate pole and its power semiconductor modular |
| CN201711322063.9A Pending CN109411461A (en) | 2017-08-15 | 2017-12-12 | The spuious balanced substrate of gate pole and its power semiconductor modular |
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| CN201721723460.2U Active CN207868198U (en) | 2017-08-15 | 2017-12-12 | A kind of spuious balanced substrate of gate pole and its power semiconductor modular |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023083338A1 (en) * | 2021-11-12 | 2023-05-19 | 比亚迪半导体股份有限公司 | Semiconductor power module, motor controller, and vehicle |
| WO2024045990A1 (en) * | 2022-08-31 | 2024-03-07 | 比亚迪半导体股份有限公司 | Semiconductor power module, motor controller, and vehicle |
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| CN107342313A (en) * | 2017-08-15 | 2017-11-10 | 杭州浙阳电气有限公司 | The spuious balanced substrate of gate pole and its power semiconductor modular |
| CN107958905A (en) * | 2017-12-11 | 2018-04-24 | 臻驱科技（上海）有限公司 | Power semiconductor modular substrate |
| CN108447845A (en) * | 2018-05-21 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN108447847A (en) * | 2018-06-06 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN108447846A (en) * | 2018-06-06 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN108807336A (en) * | 2018-06-06 | 2018-11-13 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN110867438A (en) * | 2019-09-30 | 2020-03-06 | 臻驱科技（上海）有限公司 | Power semiconductor module substrate |
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| CN207868198U (en) | 2018-09-14 |
| CN107342313A (en) | 2017-11-10 |
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