CN109410820B - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
- Publication number
- CN109410820B CN109410820B CN201811537694.7A CN201811537694A CN109410820B CN 109410820 B CN109410820 B CN 109410820B CN 201811537694 A CN201811537694 A CN 201811537694A CN 109410820 B CN109410820 B CN 109410820B
- Authority
- CN
- China
- Prior art keywords
- transistor
- electrically connected
- signal
- node
- pull
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
According to the GOA circuit and the display panel provided by the embodiment of the application, the cascade control module is added in each grade of GOA unit, when the display panel is in a normal working state, the cascade control module outputs a previous scanning signal to the pull-up control module, and the GOA circuit grade is normally started; when the display panel is in an abnormal pause state, the cascade control module outputs a low level signal to the pull-up control module, and the GOA circuit level transmission is paused, so that the pause and the start of the GOA circuit level transmission are realized, the control function of the GOA circuit is enriched, and the reliability of the display panel is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a GOA circuit and a display panel.
Background
The GOA (Gate Driver on Array, chinese) technology integrates a Gate driving circuit on an Array substrate of a display panel, so that the Gate driving integrated circuit part can be omitted to reduce the product cost from both the material cost and the manufacturing process. Such a gate switching circuit integrated on an array substrate by using the GOA technology is also referred to as a GOA circuit or a shift register circuit, where each shift register in the gate switching circuit is also referred to as a GOA unit.
The stage transmission structure of the existing GOA circuit is complete and continuous, namely, each stage of GOA unit is sequentially turned on and off according to the stage transmission sequence, and the GOA circuit cannot realize the pause and the turn-on of the stage transmission.
Disclosure of Invention
An object of the embodiments of the present application is to provide a GOA circuit and a display panel, which can implement pause and start of level transmission.
The embodiment of the application provides a GOA circuit, includes: the multistage GOA unit that cascades, each grade GOA unit all includes: the device comprises a cascade control module, an upper pulling control module, a lower transmitting module, an upper pulling module, a lower pulling maintaining module and an energy storage module;
the cascade control module is accessed to a first control signal, a second control signal, a previous scanning signal and a low level signal, is electrically connected to the pull-up control module, and is used for outputting the previous scanning signal or the low level signal to the pull-up control module under the control of the first control signal and the second control signal;
the pull-up control module is connected to a previous-level transmission signal, is electrically connected to a first node, and is used for outputting the previous-level scanning signal or the low-level signal to the first node under the control of the previous-level transmission signal;
the down-transmission module is accessed to a first clock signal, is electrically connected to the first node and is used for outputting a current-level transmission signal under the potential control of the first node;
the pull-up module is connected to the first clock signal, electrically connected to the first node, and used for outputting a scanning signal of the current stage under the control of the potential of the first node;
the pull-down module is connected to a next-stage scanning signal and the low-level signal, electrically connected to the first node and the current-stage scanning signal, and used for pulling down the potential of the first node and the potential of the current-stage scanning signal according to the next-stage scanning signal;
the pull-down maintaining module is connected to the low level signal, electrically connected to the first node and the current-level scanning signal, and configured to maintain the potential of the first node and the potential of the current-level scanning signal at the potential of the low level signal after the pull-down module pulls down the potential of the first node and the potential of the current-level scanning signal;
the energy storage module is electrically connected to the first node and the current-stage scanning signal, and is configured to store a potential of the first node and enable an equipotential jump between the potential of the first node and a potential of the current-stage scanning signal.
In the GOA circuit described in this application, the cascade control module includes: a first transistor and a second transistor;
the source electrode of the first transistor is electrically connected to the upper-stage scanning signal, and the grid electrode of the first transistor is electrically connected to the first control signal; the source of the second transistor is electrically connected to the low-level signal, and the gate of the second transistor is electrically connected to the second control signal; the drain electrode of the first transistor and the drain electrode of the second transistor are electrically connected to the pull-up control module.
In the GOA circuit described in this application, when the first transistor and the second transistor are both N-type transistors or P-type transistors, the polarity of the first control signal is opposite to the polarity of the second control signal.
In the GOA circuit of the present application, when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the polarity of the first control signal is the same as the polarity of the second control signal;
or, when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the polarity of the first control signal is the same as the polarity of the second control signal.
In the GOA circuit described in this application, the pull-up control module includes: a third transistor;
the source of the third transistor is electrically connected to the cascade control module, the gate of the third transistor is electrically connected to the previous-stage transmission signal, and the drain of the third transistor is electrically connected to the first node.
In the GOA circuit described in this application, the download module includes: a fourth transistor;
the source of the fourth transistor is electrically connected to the first clock signal, the gate of the fourth transistor is electrically connected to the first node, and the drain of the fourth transistor is electrically connected to the present-stage transmission signal.
In the GOA circuit described in this application, the pull-up module includes: a fifth transistor;
the source of the fifth transistor is electrically connected to the first clock signal, the gate of the fifth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the present-stage scanning signal.
In the GOA circuit described in this application, the pull-down module includes: a sixth transistor and a seventh transistor;
the source electrode of the sixth transistor and the source electrode of the seventh transistor are both electrically connected with the low-level signal; the grid electrode of the sixth transistor and the grid electrode of the seventh transistor are both electrically connected to the next-stage scanning signal; the drain of the sixth transistor is electrically connected to the first node, and the drain of the seventh transistor is electrically connected to the present-stage scanning signal.
In the GOA circuit of the present application, the pull-down maintaining module includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
the source and the gate of the eighth transistor and the source of the ninth transistor are electrically connected to a second clock signal; a drain of the eighth transistor is electrically connected to a gate of the ninth transistor and a source of the twelfth transistor; a drain of the ninth transistor is electrically connected to a gate of the tenth transistor, a gate of the eleventh transistor, and a source of the thirteenth transistor; a drain of the tenth transistor, a drain of the eleventh transistor, a source of the twelfth transistor, and a source of the thirteenth transistor are all electrically connected to the low level signal; a drain of the tenth transistor is electrically connected to the present-stage scan signal, and a drain of the eleventh transistor, a gate of the twelfth transistor, and a gate of the thirteenth transistor are electrically connected to the first node.
In the GOA circuit described in this application, the energy storage module includes: a capacitor;
one end of the capacitor is electrically connected to the first node, and the other end of the capacitor is electrically connected to the current-level scanning signal.
The embodiment of the present application further provides a display panel, which includes the above-mentioned GOA circuit; when the display panel is in a normal working state, the cascade control module outputs the previous scanning signal to the pull-up control module; when the display panel is in an abnormal pause state, the cascade control module outputs the low level signal to the pull-up control module.
According to the GOA circuit and the display panel provided by the embodiment of the application, the cascade control module is added in each grade of GOA unit, when the display panel is in a normal working state, the cascade control module outputs a previous scanning signal to the pull-up control module, and the GOA circuit grade is normally started; when the display panel is in an abnormal pause state, the cascade control module outputs a low level signal to the pull-up control module, and the GOA circuit level transmission is paused, so that the pause and the start of the GOA circuit level transmission are realized, the control function of the GOA circuit is enriched, and the reliability of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a GOA unit provided in an embodiment of the present application;
fig. 2 is a first circuit diagram of a GOA unit according to an embodiment of the present disclosure;
fig. 3 is a second circuit diagram of a GOA unit according to an embodiment of the present disclosure;
fig. 4 is a third circuit diagram of a GOA unit according to an embodiment of the present disclosure;
fig. 5 is a fourth circuit diagram of a GOA unit according to an embodiment of the present disclosure;
fig. 6 is a timing diagram illustrating the GOA unit shown in fig. 2 in a pause state.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a drain, and the output end is a source. In addition, the transistors used in the embodiments of the present application may include a P-type transistor and/or an N-type transistor, where the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
In addition, it should be noted that the GOA circuit of the embodiment of the present application includes multiple cascaded GOA units. Each grade of GOA unit in the GOA circuit can be sequentially turned on and turned off according to the grade transmission sequence; in addition, the GOA circuit of the embodiment of the application can also realize pause and start of stage transmission, so that the control function of the GOA circuit is enriched.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA unit according to an embodiment of the present disclosure. As shown in fig. 1, a GOA unit provided in this embodiment of the present application includes: the system comprises a cascade control module 101, a pull-up control module 102, a pull-down module 103, a pull-up module 104, a pull-down module 105, a pull-down maintenance module 106 and an energy storage module 107.
The cascade control module 101 is connected to the first control signal C12, the second control signal C13, the previous-stage scan signal G (N-1), and the low-level signal VSS, and is electrically connected to the pull-up control module 102, and configured to output the previous-stage scan signal G (N-1) or the low-level signal VSS to the pull-up control module 102 under the control of the first control signal C12 and the second control signal C13.
The pull-up control module 102 is connected to the previous-level transmission signal ST (N-1), and is electrically connected to the first node q (N), and configured to output the previous-level scanning signal G (N-1) or the low-level signal VSS to the first node q (N) under the control of the previous-level transmission signal ST (N-1).
The downloading module 103 is connected to the first clock signal CK, electrically connected to the first node q (n), and configured to output the current-stage transmission signal st (n) under the control of the potential of the first node q (n).
The pull-up module 104 is connected to the first clock signal CK, and is electrically connected to the first node q (n) for outputting the current-stage scanning signal g (n) under the control of the potential of the first node q (n).
The pull-down module 105 is connected to the next-level scanning signal and the low-level signal VSS, and is electrically connected to the first node q (n) and the current-level scanning signal g (n), and is configured to pull down the potential of the first node q (n) and the potential of the current-level scanning signal g (n) according to the next-level scanning signal.
The pull-down maintaining module 106 is connected to the low level signal VSS, and is electrically connected to the first node q (n) and the current-stage scanning signal g (n), and configured to maintain the potential of the first node q (n) and the potential of the current-stage scanning signal g (n) at the potential of the low level signal VSS after the pull-down module 105 pulls down the potential of the first node q (n) and the potential of the current-stage scanning signal g (n);
the energy storage module 107 is electrically connected to the first node q (n) and the current-stage scanning signal g (n), and is configured to store the potential of the first node q (n) and make the potential of the first node q (n) and the potential of the current-stage scanning signal g (n) generate an equal potential jump.
The GOA unit that this application embodiment provided includes: the GOA circuit comprises a cascade control module 101, a pull-up control module 102, a pull-down module 103, a pull-up module 104, a pull-down module 105, a pull-down maintaining module 106, and an energy storage module 107, wherein the cascade control module 101 is capable of outputting a previous scan signal G (N-1) or a low level signal VSS to the pull-up control module 102 under the control of a first control signal C12 and a second control signal C13, so that the cascade control module 101 can enable the GOA circuit to be in a working state or a suspended state. When the GOA circuit is in a working state, the cascade control module 101 may output a previous scanning signal G (N-1) to the pull-up control module 102; when the GOA circuit is in the pause state, the cascade control module 101 may output the low level signal VSS to the pull-up control module 102, so as to pause the operation of the GOA circuit.
Referring to fig. 2, fig. 3, fig. 4 or fig. 5, fig. 2 is a first circuit diagram of a GOA unit according to an embodiment of the present disclosure; fig. 3 is a second circuit diagram of a GOA unit according to an embodiment of the present disclosure; fig. 4 is a third circuit diagram of a GOA unit according to an embodiment of the present disclosure; fig. 5 is a fourth circuit diagram of a GOA unit according to an embodiment of the present disclosure. As shown in fig. 2, 3, 4 or 5, the cascade control module 101 includes: a first transistor T12 and a second transistor T13; the source of the first transistor T12 is electrically connected to the previous-stage scan signal G (N-1), and the gate of the first transistor T12 is electrically connected to the first control signal C12; the source of the second transistor T13 is electrically connected to the low level signal VSS, and the gate of the second transistor T13 is electrically connected to the second control signal C13; the drain of the first transistor T12 and the drain of the second transistor T13 are electrically connected to the pull-up control module 102.
In some embodiments, as shown in fig. 2, the first transistor T12 and the second transistor T13 are both N-type transistors, and the polarity of the first control signal C12 is opposite to the polarity of the second control signal C13. That is, when the GOA circuit is in an operating state, the first control signal C12 is at a high level, the second control signal C13 is at a low level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the previous stage scan signal G (N-1) is output to the pull-up control module 102 through the first transistor T12; when the GOA circuit is in the pause state, the first control signal C12 is at a low level, the second control signal C13 is at a high level, the first transistor T12 is turned off, and the second transistor T13 is turned on, so that the low level signal VSS is output to the pull-up control module 102 through the second transistor T13.
In some embodiments, as shown in fig. 3, the first transistor T12 and the second transistor T13 are both P-type transistors, and the polarity of the first control signal C12 is opposite to the polarity of the second control signal C13. That is, when the GOA circuit is in the working state, the first control signal C12 is at a low level, the second control signal C13 is at a high level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the previous stage scan signal G (N-1) is output to the pull-up control module 102 through the first transistor T12; when the GOA circuit is in the pause state, the first control signal C12 is at a high level, the second control signal C13 is at a low level, the first transistor T12 is turned off, and the second transistor T13 is turned on, so that the low level signal VSS is output to the pull-up control module 102 through the second transistor T13.
In some embodiments, as shown in fig. 4, the first transistor T12 is an N-type transistor, the second transistor T13 is a P-type transistor, and the polarity of the first control signal C12 is the same as the polarity of the second control signal C13. That is, when the GOA circuit is in an operating state, the first control signal C12 is at a high level, the second control signal C13 is at a high level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the previous stage scan signal G (N-1) is output to the pull-up control module 102 through the first transistor T12; when the GOA circuit is in the pause state, the first control signal C12 is at a low level, the second control signal C13 is at a low level, the first transistor T12 is turned off, and the second transistor T13 is turned on, so that the low level signal VSS is output to the pull-up control module 102 through the second transistor T13.
In some embodiments, as shown in fig. 5, the first transistor T12 is a P-type transistor, the second transistor T13 is an N-type transistor, and the polarity of the first control signal C12 is the same as the polarity of the second control signal C13. That is, when the GOA circuit is in the working state, the first control signal C12 is at a low level, the second control signal C13 is at a low level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the previous stage scan signal G (N-1) is output to the pull-up control module 102 through the first transistor T12; when the GOA circuit is in the pause state, the first control signal C12 is at a high level, the second control signal C13 is at a high level, the first transistor T12 is turned off, and the second transistor T13 is turned on, so that the low level signal VSS is output to the pull-up control module 102 through the second transistor T13.
Referring to fig. 2, fig. 3, fig. 4 or fig. 5, the pull-up control module 102 includes: a third transistor T11; the source of the third transistor T11 is electrically connected to the cascade control module 101, the gate of the third transistor T11 is electrically connected to the previous-stage transmission signal ST (N-1), and the drain of the third transistor T11 is electrically connected to the first node q (N).
The download module 103 includes: a fourth transistor T22; the source of the fourth transistor T22 is electrically connected to the first clock signal CK, the gate of the fourth transistor T22 is electrically connected to the first node q (n), and the drain of the fourth transistor T22 is electrically connected to the current-stage transmission signal st (n).
The pull-up module 104 includes: a fifth transistor T21; the source of the fifth transistor T21 is electrically connected to the first clock signal CK, the gate of the fifth transistor T21 is electrically connected to the first node q (n), and the drain of the fifth transistor T21 is electrically connected to the present-stage scan signal g (n).
The pull-down module 105 includes: a sixth transistor T41 and a seventh transistor T31; the source of the sixth transistor T41 and the source of the seventh transistor T31 are both electrically connected to the low level signal VSS; the gate of the sixth transistor T41 and the gate of the seventh transistor T31 are both electrically connected to the next-stage scan signal; the drain of the sixth transistor T41 is electrically connected to the first node q (n), and the drain of the seventh transistor T31 is electrically connected to the present-stage scan signal g (n).
The pull-down maintenance module 106 includes: an eighth transistor T51, a ninth transistor T53, a tenth transistor T32, an eleventh transistor T42, a twelfth transistor T52, and a thirteenth transistor T54; the source and the gate of the eighth transistor T51 and the source of the ninth transistor T53 are electrically connected to the second clock signal LC; a drain of the eighth transistor T51 is electrically connected to the gate of the ninth transistor T53 and the source of the twelfth transistor T52; a drain of the ninth transistor T53 is electrically connected to the gate of the tenth transistor T32, the gate of the eleventh transistor T42 and the source of the thirteenth transistor T54; the drain of the tenth transistor T32, the drain of the eleventh transistor T42, the source of the twelfth transistor T52, and the source of the thirteenth transistor T54 are all electrically connected to the low level signal VSS; the drain of the tenth transistor T32 is electrically connected to the present-level scan signal g (n), the drain of the eleventh transistor T42, the gate of the twelfth transistor T52, and the gate of the thirteenth transistor T54 are all electrically connected to the first node q (n).
The energy storage module 107 includes: a capacitance Cbt; one end of the capacitor Cbt is electrically connected to the first node q (n), and the other end of the capacitor Cbt is electrically connected to the present-stage scanning signal g (n).
In some embodiments, the third transistor T11, the fourth transistor T22, the fifth transistor T21, the sixth transistor T41, the seventh transistor T31, the eighth transistor T51, the ninth transistor T53, the tenth transistor T32, the eleventh transistor T42, the twelfth transistor T52, and the thirteenth transistor T54 are all N-type transistors. Of course, those skilled in the art may set the third transistor T11, the fourth transistor T22, the fifth transistor T21, the sixth transistor T41, the seventh transistor T31, the eighth transistor T51, the ninth transistor T53, the tenth transistor T32, the eleventh transistor T42, the twelfth transistor T52, and the thirteenth transistor T54 as P-type transistors as needed, which is not limited herein.
Referring to fig. 6, fig. 6 is a timing diagram illustrating the GOA unit shown in fig. 2 in a pause state. Referring to fig. 2 and 6, when the GOA unit is in the pause state, the first control signal C12 is at a low level, the second control signal C13 is at a high level, the first transistor T12 is turned off, the second transistor T13 is turned on, so that the low level signal VSS is output to the first node q (n) through the second transistor T13, and further the fourth transistor T22, the fifth transistor T21, the twelfth transistor T52, and the thirteenth transistor T54 are turned off, the present-stage scan signal g (n) is output at a low level, and the GOA unit stops operating.
When the GOA unit is in an operating state, the first control signal C12 is at a high level, the second control signal C13 is at a high level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the previous stage scanning signal G (N-1) is output to the first node q (N) through the first transistor T12, and the GOA unit operates normally. It should be noted that each process corresponding to the working state of the GOA unit is consistent with the prior art, and is not described herein again.
In the GOA circuit provided in the embodiment of the present application, by adding a cascade control module 101 in each level of GOA unit, when the display panel is in a normal working state, the cascade control module 101 outputs a previous level scanning signal G (N-1) to the pull-up control module 102, and the GOA circuit level is normally turned on; when the display panel is in an abnormal pause state, the cascade control module 101 outputs the low level signal VSS to the pull-up control module 102, and the GOA circuit level transmission is paused, so that the GOA circuit level transmission is paused and started, the control function of the GOA circuit is enriched, and the reliability of the display panel is improved.
The embodiment of the present application further provides a display panel, which includes the above GOA circuit, which is not described herein again. When the display panel is in a working state, the cascade control module 101 outputs a previous scanning signal G (N-1) to the pull-up control module 102; when the display panel is in the pause state, the cascade control module 101 outputs the low level signal VSS to the pull-up control module 102.
The GOA circuit and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to illustrate the principles and implementations of the present application, and the above description of the embodiments is only used to help understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application. The GOA circuit and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to illustrate the principles and implementations of the present application, and the above description of the embodiments is only used to help understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (8)
1. A GOA circuit, comprising: the multistage GOA unit that cascades, each grade GOA unit all includes: the device comprises a cascade control module, an upper pulling control module, a lower transmitting module, an upper pulling module, a lower pulling maintaining module and an energy storage module;
the cascade control module is accessed to a first control signal, a second control signal, a previous scanning signal and a low level signal, is electrically connected to the pull-up control module, and is used for outputting the previous scanning signal or the low level signal to the pull-up control module under the control of the first control signal and the second control signal;
the pull-up control module is connected to a previous-level transmission signal, is electrically connected to a first node, and is used for outputting the previous-level scanning signal or the low-level signal to the first node under the control of the previous-level transmission signal;
the down-transmission module is accessed to a first clock signal, is electrically connected to the first node and is used for outputting a current-level transmission signal under the potential control of the first node;
the pull-up module is connected to the first clock signal, electrically connected to the first node, and used for outputting a scanning signal of the current stage under the control of the potential of the first node;
the pull-down module is connected to a next-stage scanning signal and the low-level signal, electrically connected to the first node and the current-stage scanning signal, and used for pulling down the potential of the first node and the potential of the current-stage scanning signal according to the next-stage scanning signal;
the pull-down maintaining module is connected to the low level signal, electrically connected to the first node and the current-level scanning signal, and configured to maintain the potential of the first node and the potential of the current-level scanning signal at the potential of the low level signal after the pull-down module pulls down the potential of the first node and the potential of the current-level scanning signal;
the energy storage module is electrically connected to the first node and the current-stage scanning signal, and is configured to store a potential of the first node and enable an equipotential jump between the potential of the first node and the potential of the current-stage scanning signal;
the cascade control module includes: a first transistor and a second transistor;
the source electrode of the first transistor is electrically connected to the upper-stage scanning signal, and the grid electrode of the first transistor is electrically connected to the first control signal; the source of the second transistor is electrically connected to the low-level signal, and the gate of the second transistor is electrically connected to the second control signal; the drain electrode of the first transistor and the drain electrode of the second transistor are electrically connected to the pull-up control module;
when the first transistor and the second transistor are both N-type transistors or P-type transistors, the polarity of the first control signal is opposite to the polarity of the second control signal.
2. The GOA circuit of claim 1, wherein the pull-up control module comprises: a third transistor;
the source of the third transistor is electrically connected to the cascade control module, the gate of the third transistor is electrically connected to the previous-stage transmission signal, and the drain of the third transistor is electrically connected to the first node.
3. The GOA circuit of claim 1, wherein the downloading module comprises: a fourth transistor;
the source of the fourth transistor is electrically connected to the first clock signal, the gate of the fourth transistor is electrically connected to the first node, and the drain of the fourth transistor is electrically connected to the present-stage transmission signal.
4. The GOA circuit of claim 1, wherein the pull-up module comprises: a fifth transistor;
the source of the fifth transistor is electrically connected to the first clock signal, the gate of the fifth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the present-stage scanning signal.
5. The GOA circuit of claim 1, wherein the pull-down module comprises: a sixth transistor and a seventh transistor;
the source electrode of the sixth transistor and the source electrode of the seventh transistor are both electrically connected with the low-level signal; the grid electrode of the sixth transistor and the grid electrode of the seventh transistor are both electrically connected to the next-stage scanning signal; the drain of the sixth transistor is electrically connected to the first node, and the drain of the seventh transistor is electrically connected to the present-stage scanning signal.
6. The GOA circuit of claim 1, wherein the pull-down maintenance module comprises: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
the source and the gate of the eighth transistor and the source of the ninth transistor are electrically connected to a second clock signal; a drain of the eighth transistor is electrically connected to a gate of the ninth transistor and a source of the twelfth transistor; a drain of the ninth transistor is electrically connected to a gate of the tenth transistor, a gate of the eleventh transistor, and a source of the thirteenth transistor; a drain of the tenth transistor, a drain of the eleventh transistor, a source of the twelfth transistor, and a source of the thirteenth transistor are all electrically connected to the low level signal; a drain of the tenth transistor is electrically connected to the present-stage scan signal, and a drain of the eleventh transistor, a gate of the twelfth transistor, and a gate of the thirteenth transistor are electrically connected to the first node.
7. The GOA circuit of claim 1, wherein the energy storage module comprises: a capacitor;
one end of the capacitor is electrically connected to the first node, and the other end of the capacitor is electrically connected to the current-level scanning signal.
8. A display panel comprising the GOA circuit of any one of claims 1-7; when the display panel is in a working state, the cascade control module outputs the previous scanning signal to the pull-up control module; when the display panel is in a pause state, the cascade control module outputs the low level signal to the pull-up control module.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811537694.7A CN109410820B (en) | 2018-12-15 | 2018-12-15 | GOA circuit and display panel |
| PCT/CN2019/080230 WO2020118971A1 (en) | 2018-12-15 | 2019-03-28 | Goa circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811537694.7A CN109410820B (en) | 2018-12-15 | 2018-12-15 | GOA circuit and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109410820A CN109410820A (en) | 2019-03-01 |
| CN109410820B true CN109410820B (en) | 2020-05-22 |
Family
ID=65459310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811537694.7A Active CN109410820B (en) | 2018-12-15 | 2018-12-15 | GOA circuit and display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109410820B (en) |
| WO (1) | WO2020118971A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109410820B (en) * | 2018-12-15 | 2020-05-22 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN110264940B (en) * | 2019-07-16 | 2020-11-10 | 深圳市华星光电半导体显示技术有限公司 | Driving circuit |
| CN110930918B (en) * | 2019-11-19 | 2023-06-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN113721794B (en) * | 2021-09-08 | 2024-01-30 | Tcl华星光电技术有限公司 | Gate scanning touch scanning integrated circuit architecture, driving method thereof and display device |
| CN114758635B (en) * | 2022-04-27 | 2023-07-25 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
| CN115862511B (en) * | 2022-11-30 | 2024-04-12 | Tcl华星光电技术有限公司 | Gate driving circuit and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118416A (en) * | 2015-09-23 | 2015-12-02 | 深圳市华星光电技术有限公司 | GOA circuit, displayer and driving method for the GOA circuit |
| CN105118465A (en) * | 2015-09-23 | 2015-12-02 | 深圳市华星光电技术有限公司 | GOA circuit and driving method thereof, and liquid crystal displayer |
| CN106409213A (en) * | 2016-12-16 | 2017-02-15 | 上海中航光电子有限公司 | Shift register unit, gate drive circuit and display device |
| CN107221299A (en) * | 2017-07-12 | 2017-09-29 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN107919100A (en) * | 2018-01-04 | 2018-04-17 | 深圳市华星光电技术有限公司 | A kind of gate driving circuit and liquid crystal display |
| CN108320717A (en) * | 2018-02-06 | 2018-07-24 | 深圳市华星光电技术有限公司 | A kind of GOA driving circuits and its liquid crystal display panel of preparation |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680453B (en) * | 2013-12-20 | 2015-09-16 | 深圳市华星光电技术有限公司 | Array base palte horizontal drive circuit |
| CN104064159B (en) * | 2014-07-17 | 2016-06-15 | 深圳市华星光电技术有限公司 | There is the gate driver circuit of self-compensating function |
| KR20160053191A (en) * | 2014-10-31 | 2016-05-13 | 엘지디스플레이 주식회사 | Gate Driver Of Display Device |
| CN105427786B (en) * | 2015-11-19 | 2018-03-20 | 北京大学深圳研究生院 | A kind of gate drive circuit unit and gate driving circuit |
| CN105513525B (en) * | 2016-02-02 | 2018-03-27 | 京东方科技集团股份有限公司 | Shift register cell, shift register, gate driving circuit and display device |
| CN109410820B (en) * | 2018-12-15 | 2020-05-22 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
-
2018
- 2018-12-15 CN CN201811537694.7A patent/CN109410820B/en active Active
-
2019
- 2019-03-28 WO PCT/CN2019/080230 patent/WO2020118971A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118416A (en) * | 2015-09-23 | 2015-12-02 | 深圳市华星光电技术有限公司 | GOA circuit, displayer and driving method for the GOA circuit |
| CN105118465A (en) * | 2015-09-23 | 2015-12-02 | 深圳市华星光电技术有限公司 | GOA circuit and driving method thereof, and liquid crystal displayer |
| CN106409213A (en) * | 2016-12-16 | 2017-02-15 | 上海中航光电子有限公司 | Shift register unit, gate drive circuit and display device |
| CN107221299A (en) * | 2017-07-12 | 2017-09-29 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN107919100A (en) * | 2018-01-04 | 2018-04-17 | 深圳市华星光电技术有限公司 | A kind of gate driving circuit and liquid crystal display |
| CN108320717A (en) * | 2018-02-06 | 2018-07-24 | 深圳市华星光电技术有限公司 | A kind of GOA driving circuits and its liquid crystal display panel of preparation |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020118971A1 (en) | 2020-06-18 |
| CN109410820A (en) | 2019-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109410820B (en) | GOA circuit and display panel | |
| US10573245B2 (en) | Shift register unit using a bootstrap effect and driving method thereof, shift register and display device | |
| CN108766340B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| US9646526B2 (en) | Gate driving unit, gate driving circuit and driving method thereof, and display device | |
| US9824656B2 (en) | Gate driver unit, gate driver circuit and driving method thereof, and display device | |
| US10540923B2 (en) | Shift register, method for driving same, gate driving circuit | |
| CN109493783B (en) | GOA circuit and display panel | |
| US9530521B2 (en) | Shift register unit, gate driving circuit, and display device | |
| EP3249638B1 (en) | Goa unit and driving method, goa circuit and display device | |
| CN108320717B (en) | GOA driving circuit and liquid crystal display panel prepared by same | |
| CN107180619B (en) | Latch and driving method thereof, source electrode driving circuit and display device | |
| CN107516505B (en) | Shifting register unit and driving method thereof, grid driving circuit and display panel | |
| US11361723B2 (en) | Shift register unit, gate driving circuit and method for driving the same, and display apparatus | |
| CN109935192B (en) | GOA circuit and display panel | |
| US10535414B2 (en) | Shift register element, method for driving the same, and display device | |
| US10467937B2 (en) | Shift register unit, driving method thereof, gate driving circuit and display device | |
| CN111145680B (en) | Drive circuit and display panel | |
| CN109166542B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US11342037B2 (en) | Shift register unit, driving method, light emitting control gate driving circuit, and display apparatus | |
| US11282469B2 (en) | Shift register unit and method for driving the same, gate driving circuit and display apparatus | |
| US11468820B2 (en) | Control circuit configuration for shift register unit, gate driving circuit and display device, and method for driving the shift register unit | |
| CN109345998B (en) | GOA circuit and display panel | |
| US20210335194A1 (en) | Gate driving circuit, driving method thereof, and display apparatus | |
| CN110930918B (en) | GOA circuit and display panel | |
| CN110570799B (en) | GOA circuit and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |