CN107919100A - A kind of gate driving circuit and liquid crystal display - Google Patents
A kind of gate driving circuit and liquid crystal display Download PDFInfo
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- CN107919100A CN107919100A CN201810006413.9A CN201810006413A CN107919100A CN 107919100 A CN107919100 A CN 107919100A CN 201810006413 A CN201810006413 A CN 201810006413A CN 107919100 A CN107919100 A CN 107919100A
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- film transistor
- tft
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The present invention proposes a kind of gate driving circuit and liquid crystal display, the gate driving circuit includes multiple GOA units of cascade, corresponding clock signal is accessed per level-one GOA unit, signal source of clock CLK, constant pressure low level source VSS, pull-up control module, pull-up module, drop-down module, drop-down maintenance module, bootstrap capacitor Cb, the first module and the second module are included per level-one GOA unit；First module and second module include low frame rate and high rate signals input terminal；First module and second module are according to the low frame rate or high rate signals received, export different scanning signals, the gate driving circuit is met the high frame frequency refresh rate of liquid crystal display panel, solve the problems, such as motion blur phenomenon or undercharge of the liquid crystal display panel when high image frames work and occur showing abnormal.
Description
Technical field
The present invention relates to display panel manufacturing field, more particularly to a kind of raster data model.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) is the display being most widely used currently on the market
Product, its production Technology is very ripe, and product yield is high, and production cost is relatively low, and market acceptance is high.
The development of existing liquid crystal display device shows the development trend of narrow frame, slimming and low cost, wherein one
The important technology of item is GOA (Gate Drive On Array, the driving of array base palte row) technology.By GOA technologies by scan line
Drive circuit is integrated on the array base palte of liquid crystal panel, thus reduced in terms of the material cost with manufacture craft product into
This.
Fig. 1 is a kind of GOA circuit diagrams of the prior art.In the GOA circuits, including pull-up control module 10,
(it includes the first drop-down drop-down of maintenance module 41 and second and maintains mould for pull-up module 20, drop-down module 30, drop-down maintenance module 40
Block 42).When the G (n-2) being electrically connected with the 11st thin film transistor (TFT) is high potential, Q (n), which is electrically charged, to be drawn high, and at this time second
11 thin film transistor (TFT) T21 are turned on, and G (n) is pulled up and exported high potential scanning signal by CK1 high potentials；When with it is the 31st thin
When the G (n+2) that film transistor and the 41st thin film transistor (TFT) are electrically connected is high potential, module is pulled down by G (n) and Q (n) points
Current potential drag down at the same time.The operating point current potential of first drop-down maintenance module and the second drop-down maintenance module for Q (n) low potentials and
LC1 (or LC2) high potential, the control sequential of GOA circuits are as shown in Figure 2.Wherein, LC1 the and LC2 cycles are 2 times of frame periods, duty
Than the low frequency signal for 1/2, LC 1 and LC2 phases differed for 1/2 cycle, and GOA drive circuits are driven using 4CLK, and 4CLK drives successively
The scanning signal output of moving grid pole, its cascade mode are input signal of the output of G (n) as G (n+2), while as G (n-
2) reset signal.
Available liquid crystal panel refresh speed is typically 60Hz at present, and the refreshing speed for some high-speed motion pictures 60Hz
Degree can produce serious motion blur phenomenon, if using higher refresh rate such as 120Hz or 240Hz may there are the wind of undercharge
Danger.
The content of the invention
The present invention provides a kind of array base palte and display panel, to solve existing display panel in high frame per second picture, because
Gate driving circuit undercharge and occur showing the problem of abnormal.
To solve the above problems, technical solution provided by the invention is as follows：
The present invention proposes a kind of gate driving circuit, and for liquid crystal display, the gate driving circuit includes cascade
N level GOA units, include per level-one GOA unit：
Signal source of clock, for providing the clock signal of this grade, the clock signal is low including the first high level and first
Level；
Constant pressure low level source, for providing the second low level；
Control module is pulled up, this is generated for receiving the first scanning signal, and according to the control of first scanning signal
The scanning level signal of level；
Module is pulled up, this level is drawn high for the scanning level signal according to described level and the clock signal of described level
Scanning signal；
Module is pulled down, for according to the second scanning signal, second low level that constant pressure low level source is provided to be defeated
Go out the output terminal of the scanning signal to described level；
Maintenance module is pulled down, for maintaining the low electricity of the scanning level signal of described level and the scanning signal of described level
It is flat；
Bootstrap capacitor, the high level of the scanning level signal for generating described level；And
First module, for exporting first scanning signal and the second scanning signal；
Second module, for exporting the 3rd scanning signal and the 4th scanning signal；
Input terminal and first module of the pull-up control module, the pull-up module, the module, described of pulling down
Pull down maintenance module and the bootstrap capacitor is electrically connected；The constant pressure low level source with it is described drop-down maintenance module and it is described under
Drawing-die block is electrically connected；The signal source of clock is electrically connected with the pull-up module；Second module and the lower drawing-die
Block is electrically connected.
According to one preferred embodiment of the present invention, first control module includes the 71st thin film transistor (TFT) and the 70th
Two thin film transistor (TFT)s, the grid input low frequency frame signal of the 71st thin film transistor (TFT), the 72nd film crystal
The grid input high frequency frame signal of pipe；
Second control module includes the 81st thin film transistor (TFT) and the 82nd thin film transistor (TFT), and the described 80th
The grid input low frequency frame signal of one thin film transistor (TFT), described the inputs high frequency frame signal the grid of 12 thin film transistor (TFT)s.
According to one preferred embodiment of the present invention, when the liquid crystal display is in the work of low frame rate picture, the grid
Drive circuit is equipped with 8 clock signals, and GOA unit described in adjacent two-stage is carried out at the same time scanning, GOA unit described in adjacent two-stage
Scanning sequence signal is identical；
The output terminal of first module exports first scanning signal, and the pull-up control module is used to receive conduct
The n-th -2 grades scanning signals of first scanning signal, and controlled by the n-th -2 grades level communications number as first order communication number
System, the drop-down module are used for according to the n-th+2 grades scanning signals as the 3rd scanning signal, constant pressure low level source are provided
The second low level output to described level scanning signal output terminal.
According to one preferred embodiment of the present invention, when the liquid crystal display is in the work of high image frames, the grid
Drive circuit is equipped with 8 clock signals, and odd-numbered line is identical with the waveform that even number line exports, and shares scanning sequence signal；
The output terminal of first module exports second scanning signal, and the pull-up control module is used to receive conduct
The n-th -4 grades scanning signals of the first scanning signal, and controlled by the n-th -4 grades level communications number as first order communication number, institute
State drop-down module to be used for according to the n-th+4 grades scanning signals as the 4th scanning signal, that constant pressure low level source is provided
Two low level outputs to the scanning signal of described level output terminal.
According to one preferred embodiment of the present invention, the pull-up module includes the 21st thin film transistor (TFT), and described 21
The grid of thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, and drain electrode is electrically connected to the clock signal
Source, source electrode are electrically connected to the output terminal of the scanning signal of described level.
According to one preferred embodiment of the present invention, the drop-down module is thin including the 31st thin film transistor (TFT) and the 41st
Film transistor；
The grid of 31st thin film transistor (TFT) is electrically connected to the output terminal of the second scanning signal, and source electrode electrically connects
It is connected to
The constant pressure low level source, drain electrode are electrically connected to the output terminal of the scanning signal of described level；
The grid of 41st thin film transistor (TFT) is electrically connected to the output terminal of the second scanning signal, and source electrode electrically connects
The constant pressure low level source is connected to, drain electrode is electrically connected to the output terminal of the pull-up control module.
According to one preferred embodiment of the present invention, the pull-up control module includes the 11st thin film transistor (TFT), and the described tenth
The grid of one thin film transistor (TFT) is electrically connected to the input terminal of the first order communication number, and source electrode is electrically connected to the pull-up control
The output terminal of molding block, drain electrode are electrically connected to the input terminal of the first scanning signal.
According to one preferred embodiment of the present invention, the drop-down maintenance module includes the first drop-down maintenance unit and the second drop-down
Maintenance unit；
The first drop-down maintenance unit includes the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 50th
Three thin film transistor (TFT)s, the 54th thin film transistor (TFT), the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；
The grid and drain electrode the first square-wave signal of access, source electrode of 51st thin film transistor (TFT) are electrically connected at institute
State the drain electrode of the 52nd thin film transistor (TFT) and the grid of the 53rd thin film transistor (TFT)；
The grid of 52nd thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, source electrode electricity
Property is connected to the constant pressure low level source；
The drain electrode of 53rd thin film transistor (TFT) accesses the first square-wave signal, and source electrode is electrically connected to the described 50th
The grid of the draining of four thin film transistor (TFT)s, the grid of the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)
Pole；
The grid of 54th thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, source electrode electricity
Property is connected to the constant pressure low level source；
The source electrode of 42nd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected to
The output terminal of the pull-up control module；
The source electrode of 32nd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected to
The output terminal of the scanning signal of described level；
The second drop-down maintenance unit includes the 61st thin film transistor (TFT), the 62nd thin film transistor (TFT), the 60th
Three thin film transistor (TFT)s, the 64th thin film transistor (TFT), the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)；
The grid and drain electrode the second square-wave signal of access, source electrode of 61st thin film transistor (TFT) are electrically connected at institute
State the drain electrode of the 62nd thin film transistor (TFT) and the grid of the 63rd thin film transistor (TFT)；
The grid of 62nd thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, source electrode electricity
Property is connected to the constant pressure low level source；
The drain electrode of 63rd thin film transistor (TFT) accesses the second square-wave signal, and source electrode is electrically connected at the described 60th
The grid of the draining of four thin film transistor (TFT)s, the grid of the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)
Pole；
The grid of 64th thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, source electrode electricity
Property is connected to the constant pressure low level source；
The source electrode of 43rd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected at
The output terminal of the pull-up control module；
The source electrode of 33rd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected at
The output terminal of the scanning signal of described level.
According to one preferred embodiment of the present invention, the bootstrap capacitor is arranged on output terminal and the institute of the pull-up control module
Between the output terminal for stating the scanning signal of this grade.
The invention also provides a kind of liquid crystal display, including above-mentioned gate driving circuit.
Beneficial effects of the present invention are：The present invention sets the first module and the second mould in existing gate driving circuit
Block, first module and second module include low frame rate and high rate signals input terminal；First module and institute
The second module is stated according to the low frame rate or high rate signals that receive, different scanning signals is exported, makes the raster data model electricity
Road can meet the high frame frequency refresh rate of liquid crystal display panel, solve smear of the liquid crystal display panel when high image frames work
Phenomenon or undercharge and occur showing the problem of abnormal.
Brief description of the drawings
, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution of the prior art
Attached drawing is briefly described needed in description, it should be apparent that, drawings in the following description are only some invented
Embodiment, for those of ordinary skill in the art, without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is present invention gate driving circuit schematic diagram a kind of in the prior art；
Fig. 2 is the present invention control sequential figure of gate driving circuit a kind of in the prior art；
Fig. 3 is a kind of gate driving circuit schematic diagram in the preferred embodiment of the present invention；
Fig. 4 is a kind of control sequential of gate driving circuit when the high frame frequency of liquid crystal panel works in the preferred embodiment of the present invention
Figure；
Fig. 5 is a kind of control sequential of gate driving circuit when liquid crystal panel low frame rate works in the preferred embodiment of the present invention
Figure.
Embodiment
The explanation of following embodiment is with reference to additional diagram, to illustrate the particular implementation that the present invention can be used to implementation
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used is to illustrate and understand the present invention, and is not used to
The limitation present invention.In figure, the similar unit of structure is with being given the same reference numerals.
The present invention provides a kind of gate driving circuit, and suitable for liquid crystal display, the gate driving circuit includes cascade
Multiple GOA units, corresponding clock signal is accessed per level-one GOA unit.When gate driving circuit is equipped with 2 clock signals：
First clock signal clk 1, second clock signal CLK2, each clock signal include the first high level VGH and the first low level
VGL, wherein the first clock CLK1 accesses the 1st, 3,5 ... (2k+1) level GOA units, second clock CLK2 accesses the 2nd, 4,6 ... (2k
+ 2) level GOA unit, k are integer.At this time, the first clock CLK1, second clock CLK2 are the square-wave signal that duty cycle is 1/2,
And it was delayed successively for 1/2 cycle.And when gate driving circuit is equipped with 4 clock signals：First clock signal clk 1, second clock letter
Number CLK2, the 3rd clock signal clk 3, the 4th clock signal clk 4, each clock signal include the first high level VGH and the
One low level VGL, wherein the first clock CLK1 the 1st, 5,9 ... (4k+1) level GOA units of access, second clock CLK2 accesses the 2nd,
6th, 10 ... (4k+2) level GOA units, the 3rd clock CLK1 access the 3rd, 7,11 ... (4k+3) level GOA units, the 4th clock CLK2
The 4th, 8,12 ... (4k+4) level GOA units are accessed, k is integer.At this time, the first clock CLK1, second clock CLK2, the 3rd clock
CLK3, the 4th clock CLK4 are the square-wave signal that duty cycle is 1/2, and are delayed successively for 1/4 cycle；Grid of the present invention
Drive circuit is provided with 8 clock signals.
Fig. 3 show a kind of connection diagram of gate driving circuit of the preferred embodiment of the present invention, the raster data model electricity
Road includes the n level GOA units of cascade, includes per level-one GOA unit：
Signal source of clock CLK, constant pressure low level source VSS, pull-up control module 10, pull-up module 20, drop-down module 30, under
Draw maintenance module 40, bootstrap capacitor Cb, the first module 50 and the second module 60；It is described pull-up control module 10 input terminal with
First module 50, the pull-up module 20, drop-down module 30, the drop-down maintenance module 40 and the bootstrap capacitor
It is electrically connected；The constant pressure low level source is electrically connected with the drop-down maintenance module 40 and the drop-down module 30；When described
Clock signal source is electrically connected with the pull-up module 20；Second module 60 is electrically connected with the drop-down module 30；
Wherein, signal source of clock CLK, for providing the clock signal of this grade, the clock signal includes the first high level
And first low level；Constant pressure low level source VSS, for providing the second low level；Control module 10 is pulled up, is swept for receiving first
Signal is retouched, and the scanning level signal Q (n) of this grade is generated according to the control of first scanning signal；Module 20 is pulled up, is used for
The scanning signal of this grade is drawn high according to the clock signal clk of the scanning level signal Q (n) of described level and described level；Under
Drawing-die block 30, for according to the second scanning signal, by second low level output that constant pressure low level source is provided to described
The output terminal of this grade of scanning signal；Pull down maintenance module 40, for maintain described level scanning level signal and described
The low level of the scanning signal of level；Bootstrap capacitor, the high level of the scanning level signal for generating described level；First module
50, for exporting first scanning signal and the second scanning signal；Second module 60, for exporting the 3rd scanning signal
With the 4th scanning signal；
In addition, first control module includes the 71st thin film transistor (TFT) T71 and the 72nd thin film transistor (TFT)
The grid input low frequency frame signal of T72, the 71st thin film transistor (TFT) T71, the 72nd thin film transistor (TFT) T72's
Grid inputs high frequency frame signal；Second control module includes the 81st thin film transistor (TFT) T81 and the 82nd film is brilliant
The grid input low frequency frame signal of body pipe T82, the 81st thin film transistor (TFT) T81, described the 12 thin film transistor (TFT)s
Grid input high frequency frame signal.
In invention first preferred embodiment, when the display panel is in the work of low frame rate picture, the raster data model
Circuit is equipped with 8 clock signals, and GOA unit described in adjacent two-stage is carried out at the same time scanning, the scanning of GOA unit described in adjacent two-stage
Clock signal is identical；
The output terminal of first module 50 exports first scanning signal, and the pull-up control module 10 is used to receive
As the n-th -2 grades scanning signals of first scanning signal, and by the n-th -2 grades level communications number as first order communication number
Control, the drop-down module 30 is used for according to the n-th+2 grades scanning signals as the 3rd scanning signal, by constant pressure low level source institute
There is provided the second low level output to described level scanning signal output terminal.
In second preferred embodiment of the invention, when the display panel is in the work of high image frames, the grid drives
Dynamic circuit is equipped with 8 clock signals, and odd-numbered line is identical with the waveform that even number line exports, and shares scanning sequence signal；
The output terminal of first module 50 exports second scanning signal, and the pull-up control module 10 is used to receive
Controlled as the n-th -4 grades scanning signals of the first scanning signal, and by the n-th -4 grades level communications number as first order communication number
System, the drop-down module 30 are used for according to the n-th+4 grades scanning signals as the 4th scanning signal, constant pressure low level source are carried
Supply the second low level output to described level scanning signal output terminal.
When the display panel is in low frame rate picture or high image frames work, the connection relation of each element is basic
Identical, the gate driving circuit is designed with 8 clock signals, both differences are：The 7th in first module 50
The grid of 11 thin film transistor (TFT) T71 receives low frame rate signal, and the 71st thin film transistor (TFT) T71 is turned on, and the first module 50 is defeated
Go out the n-th -2 grades scanning scanning signal G (n-2), the pull-up control module 10 in the gate driving circuit is to be subject to the n-th -2 grades to sweep
Retouch the control of signal G (n-2)；The grid of the 81st thin film transistor (TFT) T81 in second module 60 receives low frame rate signal, the
81 thin film transistor (TFT) T81 are turned on, and export the n-th+2 grades scanning scanning signal G (n+2), in the gate driving circuit under
Drawing-die block 30 is controlled by the n-th+2 grades scanning signal G (n+2), and the control sequential of specific GOA circuits is as shown in figure 4, adjacent two
The level GOA unit is carried out at the same time scanning, and the scanning sequence signal of GOA unit described in adjacent two-stage is identical；
The grid of the 72nd thin film transistor (TFT) T72 in first module 50 receives high rate signals, the 72nd film
Transistor T72 is turned on, the n-th -4 grades scanning scanning signal G (n-4) of the first module 50 output, upper in the gate driving circuit
It is to be subject to the control of the n-th -4 grades scanning signal G (n-4) to draw control module 10；The 82nd film crystal in second module 60
The grid of pipe T82 receives low frame rate signal, and the 82nd thin film transistor (TFT) T82 conductings, export the n-th+4 grades scanning scanning signal G
(n+4), the drop-down module 30 in the gate driving circuit is controlled by the n-th+4 grades scanning signal G (n+4), specific GOA electricity
The control sequential on road shares scanning sequence signal as shown in figure 5, odd-numbered line is identical with the waveform that even number line exports.
As shown in Figure 3 to Figure 4, it is specifically described below with liquid crystal display panel when high frame frequency works；In the present invention
In one preferred embodiment, first control module includes the 71st thin film transistor (TFT) T71 and the 72nd thin film transistor (TFT)
The grid input low frequency frame signal of T72, the 71st thin film transistor (TFT) T71, the 72nd thin film transistor (TFT) T72's
Grid inputs high frequency frame signal；Second control module includes the 81st thin film transistor (TFT) T81 and the 82nd film is brilliant
The grid input low frequency frame signal of body pipe T82, the 81st thin film transistor (TFT) T81, described the 12 thin film transistor (TFT)s
Grid input high frequency frame signal；First module 50 and second module 60 are according to the low frame rate or high frame frequency received
Signal, exports different scanning signals, the gate driving circuit is met the high frame frequency refresh rate of liquid crystal display panel,
Solve the problems, such as motion blur phenomenon or undercharge of the liquid crystal display panel when high image frames work and occur showing abnormal.
The pull-up module 20 includes the 21st thin film transistor (TFT) T21, the grid of the 21 thin film transistor (TFT) T21
The output terminal of the pull-up control module 10 is electrically connected to, drain electrode is electrically connected to the signal source of clock, and source electrode electrically connects
It is connected to the output terminal of the scanning signal G (n) of described level.The grid of i.e. described 21 thin film transistor (TFT) T21 is electrically connected to
The control for Q (n) signals that the output terminal of the pull-up control module 10 is exported.
The drop-down module 30 includes the 31st thin film transistor (TFT) T31 and the 41st thin film transistor (TFT) T41；Described
The grid of 31 thin film transistor (TFT) T31 is electrically connected to the output terminal of the n-th+4 grades scanning signal G (n+4), and source electrode is electrically connected
To the constant pressure low level source VSS, drain electrode is electrically connected to the output terminal of the scanning signal G (n) of described level；Described 40th
The grid of one thin film transistor (TFT) T41 is electrically connected to the output terminal of the n-th+4 grades scanning signal G (n+4), and source electrode is electrically connected to institute
Constant pressure low level source VSS is stated, drain electrode is electrically connected to the output terminal (accessing Q (n) signal) of the pull-up control module 10.
The pull-up control module 10 includes the 11st thin film transistor (TFT) T11, the grid of the 11st thin film transistor (TFT) T11
Pole is electrically connected to the output terminal of the first module 50, i.e., the output terminal of the n-th -4 grades level communication ST (n-4), and source electrode is electrically connected
To the output terminal of the pull-up control module 10, drain electrode is electrically connected to the input terminal of the n-th -4 grades scanning signal G (n-4).
The drop-down maintenance module 40 includes the first drop-down maintenance unit and the second drop-down maintenance unit.
It is described first drop-down maintenance unit include the 51st thin film transistor (TFT) T51, the 52nd thin film transistor (TFT) T52,
53rd thin film transistor (TFT) T53, the 54th thin film transistor (TFT) T54, the 42nd thin film transistor (TFT) T42 and the 32nd
Thin film transistor (TFT) T32；The grid and drain electrode the first square-wave signal LC1 of access of the 51st thin film transistor (TFT) T51, source electrode
It is electrically connected at the drain electrode of the 52nd thin film transistor (TFT) T52 and the grid of the 53rd thin film transistor (TFT) T53；
The output terminal that the grid of the 52nd thin film transistor (TFT) T52 is electrically connected to the pull-up control module 10 (accesses Q
(n) signal), source electrode is electrically connected at the constant pressure low level source VSS；The drain electrode of the 53rd thin film transistor (TFT) T53 connects
Enter the first square-wave signal LC1, source electrode is electrically connected to the draining of the 54th thin film transistor (TFT) T54, the described 42nd
The grid of the grid of thin film transistor (TFT) T42 and the 32nd thin film transistor (TFT) T32；54th thin film transistor (TFT)
The grid of T54 is electrically connected to the output terminal (accessing Q (n) signal) of the pull-up control module 10, and source electrode is electrically connected at
The constant pressure low level source VSS；The source electrode of the 42nd thin film transistor (TFT) T42 is electrically connected at the constant pressure low level source
VSS, drain electrode are electrically connected to the output terminal (accessing Q (n) signal) of the pull-up control module 10；32nd film
The source electrode of transistor T32 is electrically connected at the constant pressure low level source VSS, and drain electrode is electrically connected to the scanning signal of described level
The output terminal of G (n).
It is described second drop-down maintenance unit include the 61st thin film transistor (TFT) T61, the 62nd thin film transistor (TFT) T62,
63rd thin film transistor (TFT) T63, the 64th thin film transistor (TFT) T64, the 43rd thin film transistor (TFT) T43 and the 33rd
Thin film transistor (TFT) T33.The grid and drain electrode the second square-wave signal LC2 of access of the 61st thin film transistor (TFT) T61, source electrode
It is electrically connected at the drain electrode of the 62nd thin film transistor (TFT) T62 and the grid of the 63rd thin film transistor (TFT) T63；
The output terminal that the grid of the 62nd thin film transistor (TFT) T62 is electrically connected to the pull-up control module 10 (accesses this
The scanning level signal Q (n) of level), source electrode is electrically connected to the constant pressure low level source VSS；63rd film crystal
The drain electrode of pipe T63 accesses the second square-wave signal LC2, source electrode be electrically connected at the 64th thin film transistor (TFT) T64 drain electrode,
The grid of the 43rd thin film transistor (TFT) T43 and the grid of the 33rd thin film transistor (TFT) T33；Described 60th
The output terminal that the grid of four thin film transistor (TFT) T64 is electrically connected to the pull-up control module 10 (accesses the scanning electricity of this grade
Ordinary mail Q (n)), source electrode is electrically connected at the constant pressure low level source VSS；The source electrode of the 43rd thin film transistor (TFT) T43
The constant pressure low level source VSS is electrically connected at, the output terminal that drain electrode is electrically connected at the pull-up control module 10 (accesses
This grade of scanning level signal Q (n))；The source electrode of the 33rd thin film transistor (TFT) T33 is electrically connected at the low electricity of the constant pressure
Flat source VSS, drain electrode are electrically connected at the output terminal of the scanning signal G (n) of described level.
The bootstrap capacitor Cb is arranged on the output terminal of the pull-up control module 10 and the scanning signal G of described level
(n) between output terminal.
In addition, in the first embodiment, it is preferable that the first square-wave signal LC 1 and the second square-wave signal LC2 is duty
Than the square wave for 1/2, phase differs 1/2 cycle, and the first drop-down maintenance unit and the second drop-down maintenance unit work alternatively, and make
Whole circuit is obtained more to stablize.
As shown in Figure 3 and Figure 4, when liquid crystal display panel is in the work of high frame frequency, i.e. the in the first module 50 the 70th
Two thin film transistor (TFT) T72 receive high rate signals, and the drain electrode of the 72nd thin film transistor (TFT) T72 inputs the n-th -4 grades scanning signal G
(n-4)；When using gate driving circuit, scan drive circuit is started by enabling signal STV, as the n-th -4 grades level communication ST
(n-4) when being high level, the 11st thin film transistor (TFT) T11 conductings, the high level of the n-th -4 grades scanning signal G (n-4) passes through the tenth
One thin film transistor (TFT) T11 charges to bootstrap capacitor Cb so that reference point Q (n) rises to a higher level.Subsequent the n-th -4 grades levels
Communication ST (n-4) switchs to low level, and the 11st thin film transistor (TFT) T11 is disconnected, and reference point Q (n) is maintained by bootstrap capacitor Cb
One higher level.At this time, the 21st thin film transistor (TFT) pipe T21 is turned on, and the clock signal of this grade is via pull-up module 20103
Export to the output terminal of the scanning signal G (n) of described level.
Meanwhile continue to charge to bootstrap capacitor Cb by the 21st thin film transistor (TFT) T21 so that reference point Q (n) reaches
The level of one higher, the scanning signal G (n) of this grade and the n-th+4 grades level communication ST (n+4) also switch to the first high level VGH.
From the timing control figure of gate driving circuit can be seen that CLK1 and CLK2, CLK3 and CLK4, CLK5 and CLK6,
The oscillogram that CLK7 and CLK8 is exported is identical, and G1 and G2, G3 and G4, G5 and G6, G7 are identical with the oscillogram that G8 is exported, and adjacent two
Group was delayed for 1/4 cycle successively, and this time adjustment can be equivalent to two adjacent groups GOA unit and be carried out at the same time scanning, be differentiated by reducing
Rate lifts the panel charging rate under high image frames.
Fig. 5 is timing control figure of the liquid crystal display panel when low frame rate works, its operation principle with setting in the prior art
The operation principle for putting 4 clock signal gate driving circuits is identical, and two adjacent groups were delayed for 1/8 cycle successively, did not existed herein
Repeat.
The invention also provides a kind of liquid crystal display, including above-mentioned gate driving circuit.
The present invention proposes a kind of gate driving circuit and liquid crystal display, and the gate driving circuit includes the more of cascade
A GOA unit, corresponding clock signal is accessed per level-one GOA unit, includes signal source of clock CLK, constant pressure per level-one GOA unit
Low level source VSS, pull-up control module, pull-up module, drop-down module, drop-down maintenance module, bootstrap capacitor Cb, the first module with
And second module；First module and second module include low frame rate and high rate signals input terminal；Described first
Module and second module export different scanning signals, make the grid according to the low frame rate or high rate signals that receive
Pole drive circuit can meet the high frame frequency refresh rate of liquid crystal display panel, solve liquid crystal display panel and work in high image frames
When motion blur phenomenon or undercharge and occur showing the problem of abnormal.
In conclusion although the present invention is disclosed above with preferred embodiment, above preferred embodiment simultaneously is not used to limit
The system present invention, those of ordinary skill in the art, without departing from the spirit and scope of the present invention, can make various changes and profit
Decorations, therefore protection scope of the present invention is subject to the scope that claim defines.
Claims (10)
1. a kind of gate driving circuit, for liquid crystal display, it is characterised in that the gate driving circuit includes the n of cascade
Level GOA unit, includes per level-one GOA unit：
Signal source of clock, for providing the clock signal of this grade, the clock signal includes the first high level and the first low level；
Constant pressure low level source, for providing the second low level；
Control module is pulled up, this grade is generated for receiving the first scanning signal, and according to the control of first scanning signal
Scan level signal；
Module is pulled up, sweeping for this grade is drawn high for the scanning level signal according to described level and the clock signal of described level
Retouch signal；
Module is pulled down, for according to the second scanning signal, second low level output that constant pressure low level source is provided to be extremely
The output terminal of the scanning signal of described level；
Maintenance module is pulled down, for maintaining the low level of the scanning level signal of described level and the scanning signal of described level；
Bootstrap capacitor, the high level of the scanning level signal for generating described level；And
First module, for exporting first scanning signal and the second scanning signal；
Second module, for exporting the 3rd scanning signal and the 4th scanning signal；
The input terminal of the pull-up control module and first module, the pull-up module, the drop-down module, the drop-down
Maintenance module and the bootstrap capacitor are electrically connected；The constant pressure low level source and the drop-down maintenance module and the lower drawing-die
Block is electrically connected；The signal source of clock is electrically connected with the pull-up module；Second module and the drop-down module electricity
Property connection.
2. gate driving circuit according to claim 1, it is characterised in that first control module includes the 71st
Thin film transistor (TFT) and the 72nd thin film transistor (TFT), the grid input low frequency frame signal of the 71st thin film transistor (TFT), institute
State the grid input high frequency frame signal of the 72nd thin film transistor (TFT)；
Second control module includes the 81st thin film transistor (TFT) and the 82nd thin film transistor (TFT), and the described 81st is thin
The grid input low frequency frame signal of film transistor, described the inputs high frequency frame signal the grid of 12 thin film transistor (TFT)s.
3. gate driving circuit according to claim 1, it is characterised in that drawn when the liquid crystal display is in low frame rate
When face works, the gate driving circuit is equipped with 8 clock signals, and GOA unit described in adjacent two-stage is carried out at the same time scanning, adjacent
The scanning sequence signal of GOA unit described in two-stage is identical；
The output terminal of first module exports first scanning signal, and the pull-up control module is used to receive described in conduct
The n-th -2 grades scanning signals of the first scanning signal, and controlled by the n-th -2 grades level communications number as first order communication number, institute
State drop-down module to be used for according to the n-th+2 grades scanning signals as the 3rd scanning signal, that constant pressure low level source is provided
Two low level outputs to the scanning signal of described level output terminal.
4. gate driving circuit according to claim 1, it is characterised in that drawn when the liquid crystal display is in high frame frequency
When face works, the gate driving circuit is equipped with 8 clock signals, and odd-numbered line is identical with the waveform that even number line exports, and shares and sweeps
Retouch clock signal；
The output terminal of first module exports second scanning signal, and the pull-up control module, which is used to receive, is used as first
The n-th -4 grades scanning signals of scanning signal, and controlled by the n-th -4 grades level communications number as first order communication number, under described
Drawing-die block is used for according to the n-th+4 grades scanning signals as the 4th scanning signal, and second that constant pressure low level source is provided is low
Level exports the output terminal of the scanning signal to described level.
5. gate driving circuit according to claim 1, it is characterised in that the pull-up module includes the 21st film
Transistor, the grid of 21 thin film transistor (TFT) are electrically connected to the output terminal of the pull-up control module, and drain electrode is electrical
The signal source of clock is connected to, source electrode is electrically connected to the output terminal of the scanning signal of described level.
6. gate driving circuit according to claim 1, it is characterised in that the drop-down module includes the 31st film
Transistor and the 41st thin film transistor (TFT)；
The grid of 31st thin film transistor (TFT) is electrically connected to the output terminal of the second scanning signal, and source electrode is electrically connected to
The constant pressure low level source, drain electrode are electrically connected to the output terminal of the scanning signal of described level；
The grid of 41st thin film transistor (TFT) is electrically connected to the output terminal of the second scanning signal, and source electrode is electrically connected to
The constant pressure low level source, drain electrode are electrically connected to the output terminal of the pull-up control module.
7. gate driving circuit according to claim 1, it is characterised in that it is thin that the pull-up control module includes the 11st
Film transistor, the grid of the 11st thin film transistor (TFT) are electrically connected to the input terminal of the first order communication number, source electrode electricity
Property be connected to the output terminal of the pull-up control module, drain electrode is electrically connected to the input terminal of the first scanning signal.
8. gate driving circuit according to claim 1, it is characterised in that the drop-down maintenance module includes the first drop-down
Maintenance unit and the second drop-down maintenance unit；
The first drop-down maintenance unit includes the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 53rd thin
Film transistor, the 54th thin film transistor (TFT), the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；
The grid of 51st thin film transistor (TFT) and drain electrode the first square-wave signal of access, source electrode are electrically connected at described the
The drain electrode of 52 thin film transistor (TFT)s and the grid of the 53rd thin film transistor (TFT)；
The grid of 52nd thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The drain electrode of 53rd thin film transistor (TFT) accesses the first square-wave signal, and it is thin that source electrode is electrically connected to the described 54th
The grid of the draining of film transistor, the grid of the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；
The grid of 54th thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The source electrode of 42nd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected to described
Pull up the output terminal of control module；
The source electrode of 32nd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected to described
The output terminal of this grade of scanning signal；
The second drop-down maintenance unit includes the 61st thin film transistor (TFT), the 62nd thin film transistor (TFT), the 63rd thin
Film transistor, the 64th thin film transistor (TFT), the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)；
The grid of 61st thin film transistor (TFT) and drain electrode the second square-wave signal of access, source electrode are electrically connected at described the
The drain electrode of 62 thin film transistor (TFT)s and the grid of the 63rd thin film transistor (TFT)；
The grid of 62nd thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The drain electrode of 63rd thin film transistor (TFT) accesses the second square-wave signal, and it is thin that source electrode is electrically connected at the described 64th
The grid of the draining of film transistor, the grid of the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)；
The grid of 64th thin film transistor (TFT) is electrically connected to the output terminal of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The source electrode of 43rd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected at described
Pull up the output terminal of control module；
The source electrode of 33rd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected at described
The output terminal of this grade of scanning signal.
9. gate driving circuit according to claim 1, it is characterised in that the bootstrap capacitor is arranged on the pull-up control
Between the output terminal of the scanning signal of the output terminal of molding block and described level.
10. a kind of liquid crystal display, it is characterised in that including any gate driving circuits of claim 1-9.
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| CN201810006413.9A CN107919100B (en) | 2018-01-04 | 2018-01-04 | Grid driving circuit and liquid crystal display |
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| CN201810006413.9A CN107919100B (en) | 2018-01-04 | 2018-01-04 | Grid driving circuit and liquid crystal display |
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| CN109410820A (en) * | 2018-12-15 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN109637423A (en) * | 2019-01-21 | 2019-04-16 | 深圳市华星光电半导体显示技术有限公司 | GOA device and gate driving circuit |
| CN110827780A (en) * | 2019-11-25 | 2020-02-21 | 成都中电熊猫显示科技有限公司 | Gate driving unit, gate scanning driving circuit and liquid crystal display device |
| CN113643643A (en) * | 2021-09-02 | 2021-11-12 | 深圳市华星光电半导体显示技术有限公司 | Gate drive circuit and display device |
| CN114783341A (en) * | 2022-04-14 | 2022-07-22 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
| CN114842786A (en) * | 2022-04-26 | 2022-08-02 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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| CN114842786A (en) * | 2022-04-26 | 2022-08-02 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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| Publication number | Publication date |
|---|---|
| CN107919100B (en) | 2020-10-13 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |