CN107492362A - A kind of gate driving circuit and liquid crystal display - Google Patents
A kind of gate driving circuit and liquid crystal display Download PDFInfo
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- CN107492362A CN107492362A CN201710886368.6A CN201710886368A CN107492362A CN 107492362 A CN107492362 A CN 107492362A CN 201710886368 A CN201710886368 A CN 201710886368A CN 107492362 A CN107492362 A CN 107492362A
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- film transistor
- signal
- tft
- thin film
- module
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The invention provides a kind of gate driving circuit, and suitable for liquid crystal display, the gate driving circuit includes multiple GOA units of cascade, wherein, n-th grade of GOA unit includes：Signal source of clock, constant pressure low level source, pull-up control module, top rake control signal module, pull-up module, lower transmission module, drop-down module, drop-down maintenance module and bootstrap capacitor；The output end and the pull-up module, the lower transmission module, drop-down module, the drop-down maintenance module and the bootstrap capacitor for pulling up control module are electrically connected with；The constant pressure low level source is electrically connected with the drop-down maintenance module and the drop-down module；The signal source of clock is electrically connected with the top rake control signal module, and the top rake control signal module is electrically connected with the pull-up module and the lower transmission module.
Description
Technical field
The present invention relates to liquid panel technique field, more particularly to a kind of gate driving circuit and liquid crystal display.
Background technology
The development of existing liquid crystal display device shows the development trend of narrow frame, slimming and low cost, wherein one
The important technology of item is GOA (Gate Drive On Array, the driving of array base palte row) technology.By GOA technologies by scan line
Drive circuit is integrated on the array base palte of liquid crystal panel, so as to reduce in terms of the material cost with manufacture craft product into
This.
Fig. 1 is a kind of GOA circuit theory diagrams of the prior art.In the GOA circuits, including pull-up control module 101,
(it includes the first drop-down maintenance module 1041 and second and pulled down for pull-up module 102, drop-down module 103, drop-down maintenance module 104
Maintenance module 1042).When the G (n-5) being electrically connected with the 11st thin film transistor (TFT) is high potential, Q (n), which is electrically charged, to be drawn high,
Now the 21st thin film transistor (TFT) T21 is turned on, and G (n) is pulled up and exported high potential scanning signal by CK1 high potentials；When with
When the G (n+5) that 31 thin film transistor (TFT)s and the 41st thin film transistor (TFT) are electrically connected with is high potential, module is pulled down by G (n)
Dragged down simultaneously with the current potential of Q (n) points.The operating point current potential of first drop-down maintenance module and the second drop-down maintenance module is low for Q (n)
Current potential and LC1 (or LC2) high potential, the control sequential of GOA circuits are as shown in Figure 2.Wherein, LC1 the and LC2 cycles are 2 times of frame weeks
Phase, dutycycle are 1/2 low frequency signal, LC1 and LC2 phases differed for 1/2 cycle.
At present, what large scale liquid crystal display was mainly applied is still a-Si semiconductor technologies, and a-Si TFT masters at present
Still simple in construction, process costs are based on BCE (Back Channel Etching) structure, the advantages of this structure
Relatively low, its shortcoming is that parasitic capacitance is larger, especially the source electrode (one end being connected with pixel electrode) and grid of thin film transistor (TFT)
The moment that parasitic capacitance between pole terminates in gated sweep, the current potential of pixel electrode can be caused to be pulled low, this phenomenon is claimed
For feedthrough effect (feed through), the formula of feed-trough voltage is：Vth=(Vgl-Vgh) * Cgd/ (Cgd+Clc+Cst), its
Vgh and Vgl in middle equation represent voltage when gate turn-on and cut-off respectively, and Clc represents the liquid crystal voltage of pixel electrode,
Cst represents the storage voltage of pixel electrode.But feed-trough voltage can cause liquid crystal display to produce flicker (flicker) etc. no
Good influence, therefore, how to reduce the influence of feed-trough voltage then turns into a problem important in design liquid crystal display.
The content of the invention
It is an object of the present invention to provide a kind of gate driving circuit, to reduce feedthrough effect to caused by liquid crystal panel
Influence, so as to improve the display effect of liquid crystal panel and using reliability.
The invention provides a kind of gate driving circuit, and suitable for liquid crystal display, the gate driving circuit includes level
Multiple GOA units of connection, wherein, n-th grade of GOA unit includes：Signal source of clock, it is described for providing the clock signal of this grade
Clock signal includes the first high level and the first low level；Constant pressure low level source, for providing the second low level；Pull-up control mould
Block, for receiving the first scanning signal, and the scanning level signal for generating this grade is controlled by first order biography signal；Top rake controls
Signaling module, top rake control signal is exported for the control of the clock signal by described level；Module is pulled up, for by described
The control of this grade of scanning level signal, the top rake control signal is exported to the output end of the scanning signal of this grade；Under pass
Module, for receiving the top rake control signal, and the control generation second level for being scanned by described level level signal passes letter
Number；Module is pulled down, for according to the second scanning signal, by the second low level output that constant pressure low level source is provided to described
The output end of the scanning signal of level；Maintenance module is pulled down, for maintaining the scanning level signal and described level of described level
The low level of scanning signal；Bootstrap capacitor, the high level of the scanning level signal for generating described level；The pull-up control
The output end of module with it is described pull-up module, the lower transmission module, it is described drop-down module, it is described drop-down maintenance module and it is described from
Electric capacity is lifted to be electrically connected with；The constant pressure low level source is electrically connected with the drop-down maintenance module and the drop-down module；It is described
Signal source of clock and the top rake control signal module are electrically connected with, the top rake control signal module and the pull-up module and
The lower transmission module is electrically connected with.
In an embodiment of the present invention, when the gate driving circuit is provided with 2 clock signals, the pull-up control mould
Block is used to receive (n-1)th grade of scanning signal as the first scanning signal, and by (n-1)th grade of level biography that signal is passed as the first order
The control of signal, the control generation that the lower transmission module is used to be scanned level signal by described level pass signal as the second level
(n+1)th grade of level pass signal, it is described drop-down module be used for according to (n+1)th grade of scanning signal as the second scanning signal, by perseverance
The second low level output that level source provided is forced down to the output end of the scanning signal of described level；And when the grid drives
When dynamic circuit is provided with 4 clock signals, the pull-up control module is used to receive the n-th -2 grades scannings as the first scanning signal
Signal, and passed signal by the n-th -2 grades levels for passing signal as the first order and controlled, the lower transmission module are used for by described level
The control generation for scanning level signal passes the n-th+2 grades levels biography signal of signal as the second level, and the drop-down module is used for basis
As the n-th+2 grades scanning signals of the second scanning signal, by the second low level output that constant pressure low level source is provided to described
The output end of this grade of scanning signal.
In an embodiment of the present invention, the top rake control signal module includes the 23rd thin film transistor (TFT), and described
The grid of 23 thin film transistor (TFT)s accesses the clock signal of described level, drain electrode access top rake control signal, and source electrode electrically connects
It is connected to the pull-up module and the lower transmission module.
In an embodiment of the present invention, the pull-up module includes the 21st thin film transistor (TFT), 21 film
The grid of transistor is electrically connected to the output end of the pull-up control module, and drain electrode is electrically connected to the top rake control signal
Module, source electrode are electrically connected to the output end of the scanning signal of described level.
In an embodiment of the present invention, the drop-down module includes the 31st thin film transistor (TFT) and the 41st film is brilliant
Body pipe；The grid of 31st thin film transistor (TFT) is electrically connected to the output end of the second scanning signal, and source electrode is electrically connected with
To the constant pressure low level source, drain electrode is electrically connected to the output end of the scanning signal of described level；41st film
The grid of transistor is electrically connected to the output end of the second scanning signal, and source electrode is electrically connected to the constant pressure low level source, leakage
Pole is electrically connected to the output end of the pull-up control module.
In an embodiment of the present invention, the pull-up control module includes the 11st thin film transistor (TFT), and the described 11st is thin
The grid of film transistor is electrically connected to the input that the first order passes signal, and source electrode is electrically connected to the pull-up control mould
The output end of block, drain electrode are electrically connected to the input of the first scanning signal.
In an embodiment of the present invention, the lower transmission module includes the 22nd thin film transistor (TFT), and the described 22nd is thin
The grid of film transistor is electrically connected to the output end of the pull-up control module, and source electrode is electrically connected to the second level and passes letter
Number output end.
In an embodiment of the present invention, the drop-down maintenance module includes the first drop-down maintenance unit and the second drop-down maintains
Unit；
The first drop-down maintenance unit includes the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 50th
Three thin film transistor (TFT)s, the 54th thin film transistor (TFT), the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；It is described
The grid and drain electrode the first square-wave signal of access of 51st thin film transistor (TFT), it is thin that source electrode is electrically connected at the described 52nd
The drain electrode of film transistor and the grid of the 53rd thin film transistor (TFT)；The grid electricity of 52nd thin film transistor (TFT)
Property be connected to the output end of the pull-up control module, source electrode is electrically connected at the constant pressure low level source；Described 53rd
The drain electrode of thin film transistor (TFT) accesses the first square-wave signal, source electrode be electrically connected to the 54th thin film transistor (TFT) drain electrode,
The grid of 42nd thin film transistor (TFT) and the grid of the 32nd thin film transistor (TFT)；54th film
The grid of transistor is electrically connected to the output end of the pull-up control module, and source electrode is electrically connected at the constant pressure low level
Source；The source electrode of 42nd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected to described
Pull up the output end of control module；The source electrode of 32nd thin film transistor (TFT) is electrically connected at the constant pressure low level source,
Drain electrode is electrically connected to the output end of the scanning signal of described level；The second drop-down maintenance unit includes the 61st film
Transistor, the 62nd thin film transistor (TFT), the 63rd thin film transistor (TFT), the 64th thin film transistor (TFT), the 43rd film
Transistor and the 33rd thin film transistor (TFT)；The grid and drain electrode the second square wave of access of 61st thin film transistor (TFT)
Signal, source electrode are electrically connected at the drain electrode of the 62nd thin film transistor (TFT) and the grid of the 63rd thin film transistor (TFT)
Pole；The grid of 62nd thin film transistor (TFT) is electrically connected to the output end of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；The drain electrode of 63rd thin film transistor (TFT) accesses the second square-wave signal, and source electrode electrically connects
It is connected to the draining of the 64th thin film transistor (TFT), the grid and the described 33rd of the 43rd thin film transistor (TFT)
The grid of thin film transistor (TFT)；The grid of 64th thin film transistor (TFT) is electrically connected to the output of the pull-up control module
End, source electrode are electrically connected at the constant pressure low level source；The source electrode of 43rd thin film transistor (TFT) is electrically connected at described
Constant pressure low level source, drain electrode are electrically connected at the output end of the pull-up control module；33rd thin film transistor (TFT)
Source electrode is electrically connected at the constant pressure low level source, and drain electrode is electrically connected at the output end of the scanning signal of described level.
In an embodiment of the present invention, the bootstrap capacitor is arranged on the output end for pulling up control module and described
Between the output end of the scanning signal of level.
In addition, the present invention provides a kind of liquid crystal display, including above-mentioned gate driving circuit.
Gate driving circuit and liquid crystal display of the present invention are on the basis of existing GOA circuits, by being controlled in pull-up
The input of molding block increases a thin film transistor (TFT) newly, and the grid of the thin film transistor (TFT) is electrically connected into clock signal, together
When the thin film transistor (TFT) input access there is periodic top rake control signal, to reduce feedthrough effect to liquid crystal panel institute
Caused by influence, so as to improve the display effect of liquid crystal panel and using reliability.
Brief description of the drawings
Fig. 1 is existing GOA circuit theory diagrams；
Fig. 2 is the control sequential figure of existing GOA circuits；
Fig. 3 is the connection diagram of the gate driving circuit in first embodiment of the invention；
Fig. 4 is the control sequential figure of the gate driving circuit in first embodiment of the present invention；
Fig. 5 is the connection diagram of the gate driving circuit in second embodiment of the invention；
Fig. 6 is the control sequential figure of the gate driving circuit in second embodiment of the present invention；
Fig. 7 is the structural representation of the liquid crystal display of the preferred embodiment of the present invention.
Embodiment
The embodiment of gate driving circuit provided by the invention and liquid crystal display is done in detail below in conjunction with the accompanying drawings
Describe in detail bright.
Referring to shown in Fig. 3 to Fig. 6, the present invention provides a kind of gate driving circuit, suitable for liquid crystal display, the grid
Drive circuit includes multiple GOA units of cascade, and corresponding clock signal is accessed per one-level GOA unit.Work as gate driving circuit
Provided with 2 clock signals：First clock signal clk 1, second clock signal CLK2, each clock signal include the first high level
VGH and the first low level VGL, wherein the first clock CLK1 accesses the 1st, 3,5 ... (2k+1) level GOA units, second clock
CLK2 accesses the 2nd, 4,6 ... (2k+2) level GOA units, and k is integer.Now, the first clock CLK1, second clock CLK2 are to account for
Sky was delayed for 1/2 cycle successively than the square-wave signal for 1/2.And when gate driving circuit is provided with 4 clock signals：When first
Clock signal CLK1, second clock signal CLK2, the 3rd clock signal clk 3, the 4th clock signal clk 4, each clock signal bag
The first high level VGH and the first low level VGL is included, wherein the 1st, 5,9 ... (4k+1) level GOA of the first clock CLK1 accesses are mono-
Member, second clock CLK2 access the 2nd, 6,10 ... (4k+2) level GOA units, and the 3rd clock CLK1 accesses the 3rd, 7,11 ... (4k+3)
Level GOA unit, the 4th clock CLK2 access the 4th, 8,12 ... (4k+4) level GOA units, and k is integer.Now, the first clock
CLK1, second clock CLK2, the 3rd clock CLK3, the 4th clock CLK4 are the square-wave signal that dutycycle is 1/2, and are prolonged successively
When 1/4 cycle.
Wherein, n-th grade of GOA unit includes：Signal source of clock CLK, constant pressure low level source VSS, pull-up control module 101,
Top rake control signal module 102, pull-up module 103, lower transmission module 104, drop-down module 105, drop-down maintenance module 106 and bootstrapping
Electric capacity Cb；Pull up the output end and the pull-up module 103, the lower transmission module 104, the drop-down module of control module 101
105th, the drop-down maintenance module 106 and the bootstrap capacitor Cb are electrically connected with；The constant pressure low level source VSS and the drop-down
Maintenance module 106 and the drop-down module 105 are electrically connected with；The signal source of clock CLK and the top rake control signal module
102 are electrically connected with, and the top rake control signal module 102 electrically connects with the pull-up module 103 and the lower transmission module 104
Connect.
Wherein, signal source of clock CLK, for providing the clock signal of this grade, the clock signal includes the first high level
And first low level；Constant pressure low level source VSS, for providing the second low level；Control module 101 is pulled up, for receiving first
Scanning signal, and the scanning level signal Q (n) for generating this grade is controlled by first order biography signal；Top rake control signal module
102, export top rake control signal for the control of the clock signal clk by described level；Module 103 is pulled up, for by institute
The scanning level signal Q (n) of this grade control is stated, the top rake control signal is exported to the output end of the scanning signal of this grade
G(n)；Lower transmission module 104, for receiving the top rake control signal, and the control of the scanning level signal Q (n) by described level
The system generation second level passes signal；Module 105 is pulled down, for according to the second scanning signal, constant pressure low level source VSS to be provided
Second low level output to the scanning signal G (n) of described level output end；Maintenance module 106 is pulled down, for maintaining described
The scanning level signal Q (n) of level and the scanning signal G (n) of described level low level；Bootstrap capacitor Cb, it is described for generating
This grade of scanning level signal Q (n) high level；It is described pull-up control module 101 output end with it is described pull-up module 103,
The lower transmission module 104, drop-down module 105, the drop-down maintenance module 106 and the bootstrap capacitor Cb are electrically connected with；
The constant pressure low level source VSS is electrically connected with the drop-down maintenance module 106 and the drop-down module 105；The clock letter
Number source CLK is electrically connected with the top rake control signal module 102, the top rake control signal module 102 and the upper drawing-die
Block 103 and the lower transmission module 104 are electrically connected with.
In the first embodiment of the invention, when the gate driving circuit is provided with 2 clock signals, the pull-up control
Module 101 is used to receive (n-1)th grade of scanning signal as the first scanning signal, and is passed the (n-1)th of signal by as the first order
Level level passes the control of signal, and the control generation that the lower transmission module 104 is used to scan level signal by described level is used as the
(n+1)th grade of level that two level passes signal passes signal, and the drop-down module 105 is used for according to (n+1)th grade as the second scanning signal
Scanning signal, the output end by the second low level output that constant pressure low level source is provided to the scanning signal of described level.
In second embodiment of the invention, when the gate driving circuit is provided with 4 clock signals, the pull-up control
Module 101 is used to receive the n-th -2 grades scanning signals as the first scanning signal, and is passed the n-th -2 of signal by as the first order
Level level passes the control of signal, and the control generation that the lower transmission module 104 is used to scan level signal by described level is used as the
The n-th+2 grades levels that two level passes signal pass signal, and the drop-down module 105 is used for according to the n-th+2 grades as the second scanning signal
Scanning signal, the output end by the second low level output that constant pressure low level source is provided to the scanning signal of described level.
That is, 2 clock signals gate driving circuit and 4 clock signals gate driving circuit each element
Annexation it is essentially identical, both differences are：The gate driving circuit and 2 clock signals of 4 clock signals
Gate driving circuit cascade system it is different, the pull-up control module 101 in the gate driving circuit of 4 clock signals be by
Pass the control of signal ST (n-2) and the n-th -2 grades scanning signal G (n-2) to the n-th -2 grades levels, and the raster data model of 2 clock signals
Pull-up control module 101 in circuit is to be passed signal ST (n-1) and (n-1)th grade of scanning signal G (n-1) by (n-1)th grade of level
Control；Lower transmission module 104 in the gate driving circuit of 4 clock signals is the n-th+2 grades levels biography signal ST (n+2) of production, and 2
Lower transmission module 104 in the gate driving circuit of individual clock signal is that (n+1)th grade of level of production passes signal ST (n+1)；4 clock letters
Number gate driving circuit in drop-down module 105 be to be controlled by the n-th+2 grades scanning signal G (n+2), and 2 clock signals
Drop-down module 105 in gate driving circuit is controlled by (n+1)th grade of scanning signal G (n+1), for details, reference can be made to Fig. 3 and Fig. 5.
In addition, the gate driving circuit of 2 clock signals and the gate driving circuit of 4 clock signals be respectively suitable for it is different types of
Liquid crystal panel.
Below by by taking the gate driving circuit of 2 clock signals as an example, it is further described.
Referring to shown in Fig. 3 to Fig. 4, in the first embodiment of the invention, the top rake control signal module 102 includes second
13 thin film transistor (TFT) T23, the 23rd thin film transistor (TFT) T23 grid accesses the clock signal of described level, drain electrode
Top rake control signal is accessed, source electrode is electrically connected to the pull-up module 103 and the lower transmission module 104.According to prior art
, it is known that in order to reduce feedthrough effect, the voltage except reducing Cgd parasitic capacitances, it is also necessary to which gated sweep signal is subjected to top rake
Processing, one periodic top rake control signal of input is then passed through, to improve gated sweep signal, and then liquid crystal surface can be improved
The display effect of plate and use reliability.
The pull-up module 103 includes the 21st thin film transistor (TFT) T21, the grid of the 21 thin film transistor (TFT) T21
Pole is electrically connected to the output end of the pull-up control module 101, and drain electrode is electrically connected to the top rake control signal module
102, source electrode is electrically connected to the scanning signal G (n) of described level output end.That is, 21 film crystal
The control for Q (n) signals that the output end that pipe T21 grid is electrically connected to the pull-up control module 101 is exported.
The drop-down module 105 includes the 31st thin film transistor (TFT) T31 and the 41st thin film transistor (TFT) T32；It is described
31st thin film transistor (TFT) T31 grid is electrically connected to the output end of (n+1)th grade of scanning signal G (n+1), and source electrode electrically connects
The constant pressure low level source VSS is connected to, drain electrode is electrically connected to the scanning signal G (n) of described level output end；Described 4th
11 thin film transistor (TFT) T41 grid is electrically connected to the output end of (n+1)th grade of scanning signal G (n+1), and source electrode is electrically connected to
The constant pressure low level source VSS, the output end that drain electrode is electrically connected to the pull-up control module 101 (access Q (n) letters
Number).
The pull-up control module 101 includes the 11st thin film transistor (TFT) T11, the 11st thin film transistor (TFT) T11's
Grid is electrically connected to the input that (n-1)th grade of level passes signal ST (n-1), and source electrode is electrically connected to the pull-up control module
101 output end, drain electrode are electrically connected to the input of (n-1)th grade of scanning signal G (n-1).
The lower transmission module 104 includes the 22nd thin film transistor (TFT) T22, the 22nd thin film transistor (TFT) T22's
Grid is electrically connected to the output end (accessing Q (n) signal) of the pull-up control module 101, and source electrode is electrically connected to (n+1)th
Level level passes signal ST (n+1) output end.
The drop-down maintenance module 106 includes the first drop-down maintenance unit 1061 and second and pulls down maintenance unit 1062.
The first drop-down maintenance unit 1061 includes the 51st thin film transistor (TFT) T51, the 52nd thin film transistor (TFT)
T52, the 53rd thin film transistor (TFT) T53, the 54th thin film transistor (TFT) T54, the 42nd thin film transistor (TFT) T42 and the 3rd
12 thin film transistor (TFT) T32；The grid and drain electrode the first square-wave signal LC1 of access of the 51st thin film transistor (TFT) T51,
Source electrode is electrically connected at the drain electrode of the 52nd thin film transistor (TFT) T52 and the 53rd thin film transistor (TFT) T53
Grid；The grid of the 52nd thin film transistor (TFT) T52 is electrically connected to the output end of the pull-up control module 101 (i.e.
Access Q (n) signal), source electrode is electrically connected at the constant pressure low level source VSS；The leakage of the 53rd thin film transistor (TFT) T53
The first square-wave signal LC1 is accessed in pole, and source electrode is electrically connected to the draining of the 54th thin film transistor (TFT) T54, the described 4th
The grid of 12 thin film transistor (TFT) T42 grid and the 32nd thin film transistor (TFT) T32；54th film is brilliant
Body pipe T54 grid is electrically connected to the output end (accessing Q (n) signal) of the pull-up control module 101, and source electrode electrically connects
It is connected to the constant pressure low level source VSS；The source electrode of the 42nd thin film transistor (TFT) T42 is electrically connected at the low electricity of the constant pressure
Flat source VSS, drain electrode are electrically connected to the output end (accessing Q (n) signal) of the pull-up control module 101；Described 30th
Two thin film transistor (TFT) T32 source electrode is electrically connected at the constant pressure low level source VSS, and drain electrode is electrically connected to sweeping for described level
Retouch signal G (n) output end.
The second drop-down maintenance unit 1062 includes the 61st thin film transistor (TFT) T61, the 62nd thin film transistor (TFT)
T62, the 63rd thin film transistor (TFT) T63, the 64th thin film transistor (TFT) T64, the 43rd thin film transistor (TFT) T43 and the 3rd
13 thin film transistor (TFT) T33.The grid and drain electrode the second square-wave signal LC2 of access of the 61st thin film transistor (TFT) T61,
Source electrode is electrically connected at the drain electrode of the 62nd thin film transistor (TFT) T62 and the 63rd thin film transistor (TFT) T63
Grid；The grid of the 62nd thin film transistor (TFT) T62 is electrically connected to the output end of the pull-up control module 101 (i.e.
Access the scanning level signal Q (n) of this grade), source electrode is electrically connected to the constant pressure low level source VSS；Described 63rd is thin
Film transistor T63 drain electrode accesses the second square-wave signal LC2, and source electrode is electrically connected at the 64th thin film transistor (TFT) T64
Drain, the grid of the 43rd thin film transistor (TFT) T43 and the 33rd thin film transistor (TFT) T33 grid；Institute
State the 64th thin film transistor (TFT) T64 grid be electrically connected to it is described pull-up control module 101 output end (access this level
Scanning level signal Q (n)), source electrode is electrically connected at the constant pressure low level source VSS；43rd thin film transistor (TFT)
T43 source electrode is electrically connected at the constant pressure low level source VSS, and drain electrode is electrically connected at the defeated of the pull-up control module 101
Go out end (the scanning level signal Q (n) for accessing this grade)；The source electrode of the 33rd thin film transistor (TFT) T33 is electrically connected at
The constant pressure low level source VSS, drain electrode are electrically connected at the scanning signal G (n) of described level output end.
The bootstrap capacitor Cb is arranged on the output end of the pull-up control module 101 and the scanning signal G of described level
(n) between output end.
In addition, in the first embodiment, it is preferable that the first square-wave signal LC1 and the second square-wave signal LC2 is dutycycle
For 1/2 square wave, phase differs 1/2 cycle, and the first drop-down maintenance unit 1061 and second pulls down maintenance unit 1062 and replaced
Work so that whole circuit is more stable.
With continued reference to shown in Fig. 3 and Fig. 4, when using gate driving circuit, turntable driving electricity is started by enabling signal STV
Road, when it is high level that (n-1)th grade of level, which passes signal ST (n-1), the 11st thin film transistor (TFT) T11 conductings, (n-1)th grade of scanning signal
G (n-1) high level is charged by the 11st thin film transistor (TFT) T11 to bootstrap capacitor Cb so that reference point Q (n) rises to one
Higher level.Subsequent (n-1)th grade of level passes signal ST (n-1) and switchs to low level, and the 11st thin film transistor (TFT) T11 disconnects, reference point Q
(n) a higher level is maintained by bootstrap capacitor Cb.Now, the 21st thin film transistor (TFT) pipe T21 and the 22nd film
Transistor T22 is turned on.
When the clock signal of this grade switchs to high level so that the 23rd thin film transistor (TFT) T23 is turned on, and then top rake controls
Signaling module 102 exports a top rake control signal, and is exported via pull-up module 103 to the scanning signal G's (n) of described level
Output end.
Meanwhile continue to charge to bootstrap capacitor Cb by the 21st thin film transistor (TFT) T21 so that reference point Q (n) reaches
One higher level, scanning signal G (n) and (n+1)th grade of level of this grade pass signal ST (n+1) and also switch to the first high level VGH.
Then, the clock signal of this grade switchs to the first low level so that the 23rd thin film transistor (TFT) T23 ends.Then,
This grade of scanning signal G (n) level is placed in the first low level.
When (n+1)th grade of scanning signal G (n+1) is high level, the 31st thin film transistor (TFT) T31 and the 41st
Thin film transistor (TFT) T41 is turned on, and the scanning signal G (n) of this grade level is placed in the second low level by constant pressure low level source VSS, by
It is less than the second low level in the first low level, so as to make up feed-trough voltage caused by parasitic capacitance.
Finally, maintenance module is pulled down by the first drop-down maintenance module 1061 and second pulled down in maintenance module 106
1062 alternating action, ensure reference point Q (n) low potential, the scanning signal G (n) in second low level level is risen
To maintenance effect.
In addition, referring to Fig. 5 and Fig. 6, in second embodiment of the invention, i.e., 4 clocks are provided with gate driving circuit
Signal, its operation principle are substantially similar to the gate driving circuit of 2 clock signals.Simply scanning signal G (n) odd-numbered line and
The problems of even number line needs two different top rake control signals, with solution in the prior art.
Therefore, the circuit of first embodiment or second embodiment is on the basis of existing gate driving circuit, by upper
Draw the input of control module to increase a thin film transistor (TFT) newly, and the grid of the thin film transistor (TFT) is electrically connected to clock letter
Number, while the input access of the thin film transistor (TFT) has periodic top rake control signal, to reduce feedthrough effect to liquid crystal
Influence caused by panel, so as to improve the display effect of liquid crystal display panel and using reliability.
The present invention also provides a kind of liquid crystal display, including above-mentioned gate driving circuit 720, refers to accompanying drawing 7, Fig. 7
It is the structural representation of the liquid crystal display of the preferred embodiment of the present invention
In the preferred embodiment, liquid crystal display includes liquid crystal panel 710 and is arranged on the grid of liquid crystal panel side
Drive circuit 720, the structure and operation principle of the gate driving circuit 720 can be found in the first of above-mentioned gate driving circuit
Embodiment and second embodiment, will not be repeated here.
Because the gate driving circuit 720 in liquid crystal display passes through the input newly-increased one in pull-up control module 101
Thin film transistor (TFT) T23, and thin film transistor (TFT) T23 grid is electrically connected to clock signal, while the thin film transistor (TFT)
T23 input access has periodic top rake control signal, to reduce feedthrough effect to the influence caused by liquid crystal panel,
So as to improve the display effect of liquid crystal display panel and using reliability.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of gate driving circuit, suitable for liquid crystal display, it is characterised in that the gate driving circuit includes cascade
Multiple GOA units, wherein, n-th grade of GOA unit includes：
Signal source of clock, for providing the clock signal of this grade, the clock signal includes the first high level and the first low level；
Constant pressure low level source, for providing the second low level；
Control module is pulled up, for receiving the first scanning signal, and signal is passed by the first order and is controlled the scanning for generating this grade electric
Ordinary mail number；
Top rake control signal module, top rake control signal is exported for the control of the clock signal by described level；
Module is pulled up, for being scanned controlling for level signal by described level, the top rake control signal is exported to this level
Scanning signal output end；
Lower transmission module, for receiving the top rake control signal, and scanned by described level the control generation the of level signal
Two level passes signal；
Module is pulled down, for according to the second scanning signal, by the second low level output that constant pressure low level source is provided to described
The output end of this grade of scanning signal；
Maintenance module is pulled down, for maintaining the low level of the scanning level signal of described level and the scanning signal of described level；
Bootstrap capacitor, the high level of the scanning level signal for generating described level；
The output end of the pull-up control module and the pull-up module, the lower transmission module, the drop-down module, the drop-down
Maintenance module and the bootstrap capacitor are electrically connected with；The constant pressure low level source and the drop-down maintenance module and the lower drawing-die
Block is electrically connected with；The signal source of clock is electrically connected with the top rake control signal module, the top rake control signal module
It is electrically connected with the pull-up module and the lower transmission module.
2. gate driving circuit according to claim 1, it is characterised in that
When the gate driving circuit is provided with 2 clock signals, the pull-up control module is used to receive as the first scanning
(n-1)th grade of scanning signal of signal, and controlled by (n-1)th grade of level biography signal that signal is passed as the first order, pass mould under described
The control generation that block is used to be scanned level signal by described level passes signal, institute as (n+1)th grade of level of second level biography signal
State drop-down module to be used for according to (n+1)th grade of scanning signal as the second scanning signal, that constant pressure low level source is provided
Two low level outputs to the scanning signal of described level output end；And
When the gate driving circuit is provided with 4 clock signals, the pull-up control module is used to receive as the first scanning
The n-th -2 grades scanning signals of signal, and controlled by the n-th -2 grades levels biography signal that signal is passed as the first order, pass mould under described
The control generation that block is used to be scanned level signal by described level passes signal, institute as the n-th+2 grades levels of second level biography signal
State drop-down module to be used for according to the n-th+2 grades scanning signals as the second scanning signal, that constant pressure low level source is provided
Two low level outputs to the scanning signal of described level output end.
3. gate driving circuit according to claim 1, it is characterised in that the top rake control signal module includes second
13 thin film transistor (TFT)s, the grid of the 23rd thin film transistor (TFT) access the clock signal of described level, and drain electrode access is cut
Angle control signal, source electrode are electrically connected to the pull-up module and the lower transmission module.
4. gate driving circuit according to claim 1, it is characterised in that the pull-up module includes the 21st film
Transistor, the grid of 21 thin film transistor (TFT) are electrically connected to the output end of the pull-up control module, and drain electrode is electrical
The top rake control signal module is connected to, source electrode is electrically connected to the output end of the scanning signal of described level.
5. gate driving circuit according to claim 1, it is characterised in that the drop-down module includes the 31st film
Transistor and the 41st thin film transistor (TFT)；
The grid of 31st thin film transistor (TFT) is electrically connected to the output end of the second scanning signal, and source electrode is electrically connected to
The constant pressure low level source, drain electrode are electrically connected to the output end of the scanning signal of described level；
The grid of 41st thin film transistor (TFT) is electrically connected to the output end of the second scanning signal, and source electrode is electrically connected to
The constant pressure low level source, drain electrode are electrically connected to the output end of the pull-up control module.
6. gate driving circuit according to claim 1, it is characterised in that it is thin that the pull-up control module includes the 11st
Film transistor, the grid of the 11st thin film transistor (TFT) are electrically connected to the input that the first order passes signal, source electrode electricity
Property be connected to the output end of the pull-up control module, drain electrode is electrically connected to the input of the first scanning signal.
7. gate driving circuit according to claim 1, it is characterised in that the lower transmission module includes the 22nd film
Transistor, the grid of the 22nd thin film transistor (TFT) are electrically connected to the output end of the pull-up control module, source electrode electricity
Property be connected to the output end that the second level passes signal.
8. gate driving circuit according to claim 1, it is characterised in that the drop-down maintenance module includes the first drop-down
Maintenance unit and the second drop-down maintenance unit；
The first drop-down maintenance unit includes the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 53rd thin
Film transistor, the 54th thin film transistor (TFT), the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；
The grid of 51st thin film transistor (TFT) and drain electrode the first square-wave signal of access, source electrode are electrically connected at described the
The drain electrode of 52 thin film transistor (TFT)s and the grid of the 53rd thin film transistor (TFT)；
The grid of 52nd thin film transistor (TFT) is electrically connected to the output end of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The drain electrode of 53rd thin film transistor (TFT) accesses the first square-wave signal, and it is thin that source electrode is electrically connected to the described 54th
The grid of the draining of film transistor, the grid of the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；
The grid of 54th thin film transistor (TFT) is electrically connected to the output end of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The source electrode of 42nd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected to described
Pull up the output end of control module；
The source electrode of 32nd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected to described
The output end of this grade of scanning signal；
The second drop-down maintenance unit includes the 61st thin film transistor (TFT), the 62nd thin film transistor (TFT), the 63rd thin
Film transistor, the 64th thin film transistor (TFT), the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)；
The grid of 61st thin film transistor (TFT) and drain electrode the second square-wave signal of access, source electrode are electrically connected at described the
The drain electrode of 62 thin film transistor (TFT)s and the grid of the 63rd thin film transistor (TFT)；
The grid of 62nd thin film transistor (TFT) is electrically connected to the output end of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The drain electrode of 63rd thin film transistor (TFT) accesses the second square-wave signal, and it is thin that source electrode is electrically connected at the described 64th
The grid of the draining of film transistor, the grid of the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)；
The grid of 64th thin film transistor (TFT) is electrically connected to the output end of the pull-up control module, and source electrode electrically connects
It is connected to the constant pressure low level source；
The source electrode of 43rd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected at described
Pull up the output end of control module；
The source electrode of 33rd thin film transistor (TFT) is electrically connected at the constant pressure low level source, and drain electrode is electrically connected at described
The output end of this grade of scanning signal.
9. gate driving circuit according to claim 1, it is characterised in that the bootstrap capacitor is arranged on the pull-up control
Between the output end of the scanning signal of the output end of molding block and described level.
10. a kind of liquid crystal display, it is characterised in that including any described gate driving circuits of claim 1-9.
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| CN201710886368.6A CN107492362B (en) | 2017-09-27 | 2017-09-27 | Grid driving circuit and liquid crystal display |
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| CN108535924A (en) * | 2018-04-19 | 2018-09-14 | 深圳市华星光电技术有限公司 | Liquid crystal display device and its driving method |
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| CN109119011A (en) * | 2018-07-25 | 2019-01-01 | 深圳市华星光电技术有限公司 | GOA circuit and display panel and display device including it |
| CN109119036A (en) * | 2018-07-26 | 2019-01-01 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| CN114038387A (en) * | 2021-12-07 | 2022-02-11 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN114842786A (en) * | 2022-04-26 | 2022-08-02 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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| CN114038387A (en) * | 2021-12-07 | 2022-02-11 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN114038387B (en) * | 2021-12-07 | 2023-08-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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