CN105448250A - Gate driving method for displays and driving module - Google Patents
Gate driving method for displays and driving module Download PDFInfo
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- CN105448250A CN105448250A CN201410429541.6A CN201410429541A CN105448250A CN 105448250 A CN105448250 A CN 105448250A CN 201410429541 A CN201410429541 A CN 201410429541A CN 105448250 A CN105448250 A CN 105448250A
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Abstract
A gate driving method for displays comprises the following steps: sequentially supplying multiple scanning signal sets to multiple scanning line sets, wherein each scanning signal set includes multiple scanning signals which are respectively transmitted to multiple scanning lines of the corresponding scanning line set; and performing multiple shading operations on the multiple scanning signals to reduce the high voltage level of the scanning signals. Multiple first time intervals between the time of the upper edges of the scanning signals and the start time of the corresponding shading operations or multiple second time intervals between the time of the upper edges of the scanning signals and the end time of the corresponding shading operations sequentially increase or decrease for the different scanning signal sets. A driving module is further disclosed.
Description
Technical field
The present invention relates to a kind of driving method and driver module, and the grid drive method in particular to a kind of display and the driver module in order to driving display.
Background technology
Display technique, in constantly progress in recent years, except the picture quality that user can be provided good, can stride forward toward the direction saving space and low power consumption again.For example, liquid crystal display owing to producing high image quality, and can reach the demand of thinning and power saving simultaneously, therefore significantly replaces conventional cathode ray tube (CRT) and becomes the main flow in market.
In addition, display now mostly generally is flat-panel screens, and therefore when picture dimension increases, the increase of the thickness of display is also few.Thus, this feature of flat-panel screens is just suitable for the display developing large picture, with the visual enjoyment providing user higher, but can not too take space, incity.
But, when display is toward large picture development, because the electric conduction routing on display panel is elongated, the impedance of array coiling (wireonarray, WOA) is increased, and the leakage current of thin film transistor (TFT) also increase.Thus, will easily cause horizontal band-like district display frame occurring different brightness, picture namely can be made uneven.
In order to solve the problem, the fine setting of display panel technique can be adopted or redesign display panel and reach, but such solution be by the time of at substantial, and significantly can increase cost of manufacture.
Summary of the invention
The invention provides a kind of grid drive method of display, it mode that is simple and easy, low cost can solve the problem in the horizontal band-like district of the different brightness of display frame.
The invention provides a kind of driver module, it can provide a kind of scheme solving the problem in the horizontal band-like district of the different brightness of display frame in mode that is simple and easy, low cost.
One embodiment of the invention propose a kind of grid drive method of display, and display comprises multiple sweep trace, and these sweep traces are sequentially divided into multiple scanline groups.The grid drive method of this display comprises: sequentially provide multiple sweep signal group to these scanline groups respectively, and wherein each sweep signal group comprises multiple sweep signals of the multiple sweep traces being passed to corresponding scanline groups respectively; And respectively multiple chamfering operation is carried out to these sweep signals, to reduce the high voltage level of these sweep signals.Multiple very first time interval between the time of the rising edge of these sweep signals and the starting time of these corresponding respectively chamfering operation or and the termination time of these corresponding respectively chamfering operation between multiple second time intervals be sequentially increasing or decreasing for these different sweep signal groups.
One embodiment of the invention propose a kind of driver module, in order to driving display.Display comprises multiple sweep trace, and these sweep traces are sequentially divided into multiple scanline groups.This driver module comprises multiple gate drivers, power supply unit and control module.These gate drivers sequentially provide multiple sweep signal group to these scanline groups respectively, and each sweep signal group comprises multiple sweep signals of the multiple sweep traces being passed to corresponding scanline groups respectively.Power supply unit is in order to provide high levle signal and low level signal to these gate drivers, and these gate drivers thus switch high levle signal and low level signal and form these sweep signals.Control module transmits top rake and controls signal to these gate drivers or power supply unit, to carry out multiple chamfering operation to these sweep signals respectively, and then reduces the high voltage level of these sweep signals.Multiple very first time interval between the time of the rising edge of these sweep signals and the starting time of these corresponding respectively chamfering operation or and the termination time of these corresponding respectively chamfering operation between multiple second time intervals be sequentially increasing or decreasing for these different sweep signal groups.
In one embodiment of this invention, top rake control signal is the output enable signal being sent to these gate drivers, and the sequentially increasing or decreasing of these second time intervals for these different sweep signal groups reaches to these gate drivers by transmitting the output enable signal with distinct pulse widths in different multiple periods respectively.
In one embodiment of this invention, these chamfering operation of carrying out these sweep signals respectively carry out chamfering operation by these gate drivers of correspondence to high levle signal reached, and the size in these second time intervals along with its corresponding respectively these gate drivers to the distance of the conducting wire of power supply unit order from far near and successively decrease.
In one embodiment of this invention, these chamfering operation of carrying out these sweep signals respectively carry out chamfering operation by power supply unit to high levle signal reached, and the size in these second time intervals along with its corresponding respectively these gate drivers to the distance of the conducting wire of power supply unit order from far near and increase progressively.
In one embodiment of this invention, top rake control signal is the gate drivers clock signal being sent to these gate drivers, and the sequentially increasing or decreasing of these very first time intervals for these different sweep signal groups reaches to these gate drivers by transmitting the gate drivers clock signal with distinct pulse widths in different multiple periods respectively.
In one embodiment of this invention, these very first time intervals size along with its corresponding respectively these gate drivers to the distance of the conducting wire of power supply unit order from far near and increase progressively.
In one embodiment of this invention, top rake control signal is the grid pulse modulation signal being sent to power supply unit, and these chamfering operation of carrying out these sweep signals respectively carry out chamfering operation by the sequential of corresponding grid pulse modulation signal to high levle signal reached.
In one embodiment of this invention, the sequentially increasing or decreasing of these very first time intervals for these different sweep signal groups be by transmit respectively in different multiple periods the grid pulse modulation signal with distinct pulse widths to power supply unit with high levle is carried out top rake dynamic institute reach.
In one embodiment of this invention, these very first time intervals size along with its corresponding respectively these gate drivers to the distance of the conducting wire of power supply unit order from far near and successively decrease.
In one embodiment of this invention, display is liquid crystal display.
In the grid drive method and driver module of the display of embodiments of the invention, due to the multiple very first time interval between time of the rising edge of these sweep signals and the starting time of these corresponding respectively chamfering operation or and the termination time of these corresponding respectively chamfering operation between multiple second time intervals be sequentially increasing or decreasing for these different sweep signal groups, therefore can produce more consistent feed-trough voltage in the different horizontal band-shaped zone of display, and then make display frame comparatively even.Thus, just effectively can solve the problem in horizontal band-like district display frame occurring different brightness at drive end, namely can with comparatively simple and easy, to save time and cost-effective mode solves this problem.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is the calcspar of the display of one embodiment of the invention.
Figure 1B illustrates the relation of sweep trace and gate drivers in the display of Figure 1A and the relation of data line and source electrode driver.
Fig. 2 is the signal waveforms of the display driving Figure 1A.
To be gate drivers initial pulse signal in the display of Figure 1A corresponding to the oscillogram of period of gate drivers different in Figure 1A from the output enable signal being sent to gate drivers to Fig. 3 A.
Fig. 3 B be sweep signal group different in the display of Figure 1A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.
Fig. 4 A is the circuit diagram of a pixel in the display of Figure 1A.
Fig. 4 B is the signal waveforms of another comparative examples of the display panels driving Figure 1A.
Fig. 4 C is an enlarged drawing through the sweep signal of top rake in Fig. 2.
Fig. 4 D is in the oscillogram of the sweep signal of Different periods in the another comparative examples driving the display panels of Figure 1A.
The schematic diagram of the display frame that the sweep signal that Fig. 4 E is Fig. 4 D produces.
To be gate drivers initial pulse signal in the display of another embodiment of the present invention corresponding to the oscillogram of period of gate drivers different in Figure 1A from the gate drivers clock signal being sent to gate drivers to Fig. 5 A.
Fig. 5 B be sweep signal group different in the display of Figure 1A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.
Fig. 6 A is the calcspar of the display of another embodiment of the present invention.
Fig. 6 B is the signal waveforms of the display driving Fig. 6 A.
Fig. 7 is in the oscillogram of the sweep signal of Different periods in another comparative examples of the display panels driving Fig. 6 A.
To be gate drivers initial pulse signal in the display of Fig. 6 A corresponding to the oscillogram of period of gate drivers different in Fig. 6 A from the output enable signal being sent to gate drivers to Fig. 8 A.
Fig. 8 B be sweep signal group different in the display of Fig. 6 A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.
To be gate drivers initial pulse signal, grid pulse modulation signal and high levle signal in the display of one more embodiment of the present invention corresponding to the oscillogram of period of gate drivers 210d different in Fig. 6 A to Fig. 9 A.
Fig. 9 B be sweep signal group different in the display of Fig. 6 A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.
Embodiment
Figure 1A is the calcspar of the display of one embodiment of the invention, Figure 1B illustrates the relation of sweep trace and gate drivers in the display of Figure 1A and the relation of data line and source electrode driver, Fig. 2 is the signal waveforms of the display driving Figure 1A, to be gate drivers initial pulse (gatedriverstartpulse) signal in the display of Figure 1A corresponding to the oscillogram of period of gate drivers different in Figure 1A from the output enable signal (outputenablesignaltogatedrivers) being sent to gate drivers to Fig. 3 A, and Fig. 3 B be sweep signal group different in the display of Figure 1A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.
Please also refer to Figure 1A to Figure 1B, Fig. 2 and Fig. 3 A to Fig. 3 B, the driver module 200 of the present embodiment is in order to driving display 100.In the present embodiment, display is such as liquid crystal display, and driver module 200 shows in order to drive display panels 300.Display 100 comprises multiple sweep trace 310, and these sweep traces 310 are sequentially divided into multiple scanline groups G, such as scanline groups G3, G2 and G1.Driver module 200 comprises multiple gate drivers 210 (such as gate drivers 210c, 210b and 210a), power supply unit 220 and control module 230.These gate drivers 210 sequentially provide multiple sweep signal group S to these scanline groups G respectively, and each sweep signal group S comprises multiple sweep signal SC of the multiple sweep traces 310 being passed to corresponding scanline groups G respectively.
Power supply unit 220 is in order to provide high levle signal VGH and low level signal VGL to these gate drivers 210, and these gate drivers 210 form these sweep signal SC by switching high levle signal VGH and low level signal VGL.Control module 230 transmits top rake and controls signal to these gate drivers 210 or power supply unit 220, to carry out multiple chamfering operation to these sweep signal SC respectively, and then reduces the high voltage level VH of these sweep signal SC.Wherein, the high voltage level VH of these sweep signal SC provided by high levle signal VGH, and the low voltage level VL of these sweep signal SC provided by low level signal VGL.In the present embodiment, control module 230 is time schedule controller (timingcontroller), and top rake control signal is output enable signal (outputenablesignal) OE being sent to gate drivers 210.
Multiple very first time interval T 1 between the time of the rising edge of these sweep signal SC and the starting time of these corresponding respectively chamfering operation or and the termination time of these corresponding respectively chamfering operation between multiple second time interval T2 be sequentially increasing or decreasing for different these sweep signals group S.In the present embodiment, these second time intervals T2 for different these sweep signals group S for sequentially successively decreasing.In the present embodiment, second time interval T2c of the sweep signal SC of the sweep signal group S transmitted in scanline groups G3 is greater than second time interval T2b of the sweep signal SC of the sweep signal group S transmitted in scanline groups G2, and second time interval T2b of the sweep signal SC of the sweep signal group S transmitted in scanline groups G2 is greater than second time interval T2a of the sweep signal SC of the sweep signal group S transmitted in scanline groups G1, as Fig. 3 B illustrate.
Fig. 4 A is the circuit diagram of a pixel in the display of Figure 1A, Fig. 4 B is the signal waveforms of another comparative examples of the display panels driving Figure 1A, Fig. 4 C is an enlarged drawing through the sweep signal of top rake in Fig. 2, Fig. 4 D is in the oscillogram of the sweep signal of Different periods in the another comparative examples driving the display panels of Figure 1A, and the schematic diagram of the display frame that the sweep signal that Fig. 4 E is Fig. 4 D produces.Please also refer to Figure 1A and Fig. 4 A, display panels 300, except having multiple sweep trace 310, still has multiple signal wire 320, multiple transistor 330 and common electrode 340.The grid 332 of each transistor 330 is even is connected to sweep trace 310, the source electrode 334 of each transistor 330 is even is connected to signal wire 320, a liquid crystal capacitance Clc is formed through a liquid crystal layer between the drain electrode 336 (and being connected to the pixel electrode of drain electrode 336) of each transistor 330 and common electrode 340 (being such as the common electrode layer being positioned at subtend substrate), and the drain electrode 336 (and being connected to the pixel electrode of drain electrode 336) of each transistor 330 and common electrode 340 (are such as the bridging lines being positioned at thin-film transistor array base-plate, it is electrically connected with the common electrode layer of subtend substrate) between form memory capacitance Cst.In addition, naturally there is stray capacitance Cgd between the drain electrode of transistor 330 that sweep trace 310 connects with it.
On the other hand, driver module 200 also comprises at least one source electrode driver 240 (being for multiple source electrode driver 240 in Figure 1A and Figure 1B), and source electrode driver 240 provides multiple data-signal D to these sweep traces 310 respectively.In the present embodiment, sweep trace 310 is sequentially divided into many groups, and these source electrode drivers 240 are coupled to the sweep trace 310 of different group respectively.As Fig. 4 B illustrate, when arbitrary sweep trace 310 transmits square wave sweep signal SC ' as Fig. 4 B to the grid 332 of corresponding transistor 330, corresponding data line 320 transmission is if the square wave data-signal D ' of Fig. 4 B is to the source electrode 334 of transistor 330.When the voltage quasi position of grid 332 is in high voltage level VH, transistor 330 conducting, and from the data-signal D ' of source electrode, memory capacitance Cst and liquid crystal capacitance Clc is charged, make the voltage rise of drain electrode 336 to the high voltage level VSH of data-signal D '.Wherein, the voltage signal at 336 places of draining is drain voltage signal VD.But when sweep signal SC ' changes low voltage level VL into from high voltage level VH, due to the capacitive coupling effect of stray capacitance Cgd, make the virtual voltage of drain electrode 336 to decline at this moment a voltage, this voltage is feed-trough voltage Δ VFT.
The large I of feed-trough voltage Δ VFT is calculated by following (1) formula and obtains:
But, due to the impedance of sweep trace 310, in the process that the sweep signal SC ' in square wave is transmitted at sweep trace 310, produce distortion gradually.Therefore, the sweep signal SC of the present embodiment adopts the square-wave signal through top rake, and the B point of waveform after top rake essentially dictates the size of feed-trough voltage Δ VFT.Because the voltage of B point and the difference of low voltage level VL are less than the difference of high voltage level VH and low voltage level VL, and when the square-wave signal of top rake produces distortion in the process that sweep trace 310 transmits, mainly can determine that the difference of the point of the size of feed-trough voltage Δ VFT and low voltage level VL can close to the difference of the voltage of B point and low voltage level VL.Thus, just can by the common voltage Vcom ' being originally positioned at the common electrode 340 at the center of the amplitude of the positive negative cycle of data-signal D ' be down adjusted Δ VFT to Vcom, and the intermediate value of the voltage that the low voltage level VSL of the voltage obtained after making the high voltage level VSH of the positive period that the value of this common voltage Vcom is data-signal cut feed-trough voltage Δ VFT and negative cycle obtains after cutting feed-trough voltage Δ VFT, and make the amplitude of the voltage difference of positive negative cycle identical and the flicker of screen can not be caused.
But the distance that low level signal VGL is passed to from power supply unit 220 conducting wire that different gate drivers 210 is passed through is different, and can cause impedance in various degree.In figure ia, the length of the conducting wire of power supply unit 220 to gate drivers 210c is greater than the length of the conducting wire of power supply unit 220 to gate drivers 210b, and the length of the conducting wire of power supply unit 220 to gate drivers 210b is greater than the length of the conducting wire of power supply unit 220 to gate drivers 210a.Because longer conducting wire can produce larger impedance, therefore, as Fig. 4 D illustrate, low voltage level VL3 corresponding to the sweep signal SC3 ' of sweep signal group G3 can than corresponding to the low voltage level VL2 of sweep signal SC2 ' of sweep signal group G2 closer to zero level (i.e. ground connection level), and low voltage level VL2 can than the low voltage level VL1 of the sweep signal SC1 ' corresponding to sweep signal group G1 closer to zero level.Because low voltage level VL1, VL2 and VL3 are all lower than zero level, therefore VL3>VL2>VL1.In addition, if the transistor 330 in display panels 300 has the situation of electric leakage, also this kind of result is easily caused.
On the other hand, in the present embodiment, these chamfering operation of carrying out these sweep signal SC respectively carry out chamfering operation by these gate drivers 210 couples of high levle signal VGH of correspondence reached, such as, be reached by the top rake circuit in gate drivers 210 well-known to those skilled in the art.For example, flash-over characteristic when operating in saturation region by transistor (such as MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)) reaches the top rake effect that high voltage level VH is declined.The drain electrode discharge current ID that this flash-over characteristic produces meets following (2) formula:
I
d=K × (VGN-VL)
2(2) formula
Wherein, VGN is the control voltage of the grid putting on this MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and VL is the low voltage level VL of low level signal VGL when being passed to the gate drivers 210 comprising this MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and K is proportionality constant.
From above (2) formula, due to more away from power supply unit 220 gate drivers 210 received by low voltage level VL larger, therefore its discharge current ID is less, and namely discharge rate is slower, and namely the absolute value of the slope of top rake is less.In the present embodiment, the absolute value of the top rake slope of sweep signal SC3 ' is less than the absolute value of the top rake slope of sweep signal SC2 ', and the absolute value of the top rake slope of sweep signal SC2 ' is less than the top rake slope absolute value of sweep signal SC1 '.
Comprehensive above two kinds of effects, that is low voltage level VL can produce different values along with conductive path length from the situation of transistor drain current at different gate drivers 210 places, and due to the difference of low voltage level VL the difference of guiding discharge speed, and then make the voltage of the B point of sweep signal SC3 ', SC2 ' and SC1 ' different, so can make the difference DELTA V3 ' of B point voltage from low voltage level VL3, VL2 and VL1, the Δ V2 ' of sweep signal SC3 ', SC2 ' and SC1 ' and Δ V1 ' different.
In the present embodiment, the top rake of the high voltage level VH that the decline degree of low voltage level VL causes than the decline because of low voltage level and the degree that declines is little, therefore in the present embodiment, Δ V3 ' > Δ V2 ' > Δ V1 '.Thus, can obtain corresponding respectively to the not identical result of different feed-trough voltage Δ VFT3, Δ VFT2 and Δ VFT1 of scanline groups G3, G2 and G1 after replace (VH-VL) in (1) formula respectively with Δ V3 ', Δ V2 ' and Δ V1 ', in the present embodiment, Δ VFT3> Δ VFT2> Δ VFT1, so by make to correspond respectively in the viewing area AA of display 100 different scanline groups G3, G2 and G1 the brightness of different horizontal band-shaped zone A3, A2 and A1 inconsistent, and easily cause the flicker of picture.
In order to head it off, referring again to Fig. 3 A and Fig. 3 B, in the present embodiment, the second time interval T2c due to the sweep signal SC of sweep signal group S transmitted in scanline groups G3 is greater than second time interval T2b of the sweep signal SC of the sweep signal group S transmitted in scanline groups G2, and second time interval T2b of the sweep signal SC of the sweep signal group S transmitted in scanline groups G2 is greater than second time interval T2a of the sweep signal SC of the sweep signal group S transmitted in scanline groups G1, therefore different scanline groups G3 is corresponded to, the sweep signal group S3 of G2 and G1, the low voltage level VL3 that the B point voltage of S2 and S1 is corresponding with it, the difference of VL2 and VL1 can be comparatively close or equal in fact, that is second time interval T2 of the sweep signal SC making the absolute value of top rake slope larger is shorter.Thus, the feed-trough voltage Δ VFT corresponding to different scanline groups G3, G2 and G1 just can be made more consistent, and then the horizontal band-shaped zone disappearance making brightness different maybe cannot allow human eye discover.In addition, because the feed-trough voltage Δ VFT of whole display panels 300 is more consistent, therefore by common voltage Vcom being adjusted to the central value of the positive negative cycle of the voltage signal received by drain electrode 336, just can effectively suppress or eliminate the flicker of picture.
In other words, in the present embodiment, these second time intervals T2 size along with its order from far near of distance of conducting wire of corresponding respectively these gate drivers 210 to power supply units 220 and successively decrease (i.e. T2c>T2b>T2a).
In the present embodiment, the sequentially increasing or decreasing of these second time intervals T2 for different these sweep signals group S be by transmitting respectively in different multiple period P (being such as period P1, P2 and P3 in the present embodiment), there is distinct pulse widths W3, the output enable signal OE of W2 and W1 reaches to these gate drivers 210.These distinct pulse widths W3, W2 and W1 of output enable signal OE realize by the pulse width modulation mechanism be applicable to.
Please refer to Figure 1A, Fig. 2 and Fig. 3 A, control module 230 transmits gate drivers initial pulse (gatedriverstartpulse, STV) STV to the first gate drivers 210c and define the beginning of a picture frame time (frametime), and from then on the time starts, gate drivers 210c, 210b and 210a sequentially transmit sweep signal group S3, S2 and S1 to scanline groups G3, G2 and G1 respectively, and the sweep signal SC in each sweep signal group S is also the sweep trace 310 being orderly sent to corresponding scanline groups G respectively.In addition, control module 230 transmits gate drivers clock signal (gatedriverclocksignal, CPV) CPV is to gate drivers 210, and gate drivers 210 decides the burst length of the sweep signal SC exporting sweep trace 310 to according to each pulse of gate drivers clock signal C PV, namely sweep signal SC is switched to the time of high voltage level VH.In Fig. 2,4th ~ 8 waveforms are sequentially the sweep signal SC on adjacent front 5 articles of sweep traces 310.
In addition, crosstalk (crosstalk) phenomenon that positive pulse in order to avoid the sweep signal SC received by adjacent two sweep traces 310 is too close and produce between two sweep traces 310, control module 230 transmits output enable signal OE to gate drivers 310, wherein when being in positive pulse time (namely output enable signal OE is in the time of high levle) of output enable signal OE, voltage quasi position higher than low voltage level VL is switched back low voltage level VL by gate drivers 210, this switching action can utilize commutation circuit well-known to those skilled in the art to reach, be not repeated herein.Thus, just the positive pulse of two sweep signal SC of adjacent two sweep traces 310 can be separated with a reasonable time interval by the suitable pulsewidth of the positive pulse time of output enable signal OE, to avoid or to suppress the crosstalk between adjacent two sweep traces 310.
In addition, in the present embodiment, the initial time of chamfering operation is the time of the falling edge of the positive pulse corresponding to gate drivers clock signal C PV, and the rising edge time of the positive pulse of output enable signal OE is the termination time of the positive pulse corresponding to sweep signal SC, namely corresponding to the termination time of chamfering operation, is also the B point time corresponding to sweep signal.
Thus, by the rising edge of the positive pulse of output enable signal OE being adjusted toward positive time orientation or negative time orientation at different period P3, P2, P1, just can change the time that chamfering operation experiences, and the length of the second time T2 can be changed.In the present embodiment, pulsewidth W3<W2<W1, so can make T2c>T2b>T2a.
To be gate drivers initial pulse (gatedriverstartpulse) signal in the display of another embodiment of the present invention corresponding to the oscillogram of period of gate drivers different in Figure 1A from the gate drivers clock signal being sent to gate drivers to Fig. 5 A, and Fig. 5 B be sweep signal group different in the display of Figure 1A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.Please refer to Figure 1A, Fig. 5 A and Fig. 5 B, in the present embodiment, top rake control signal is the gate drivers clock signal C PV being sent to these gate drivers 210, the sequentially increasing or decreasing of these very first time interval T 1 for different these sweep signals group S be by transmitting respectively in different multiple period P, there is distinct pulse widths W31, the gate drivers clock signal C PV of W21 and W11 reaches to these gate drivers 210.These distinct pulse widths W31, W21 and W11 of gate drivers clock signal C PV realize by the pulse width modulation mechanism be applicable to.
In addition, in the present embodiment, very first time interval T 1c corresponding to sweep signal group S3 is less than the very first time interval T 1b corresponding to sweep signal group S2, and the very first time interval T 1b corresponding to sweep signal group S2 is less than the very first time interval T 1a corresponding to sweep signal group S1.In other words, these very first time interval T 1 size along with its corresponding respectively these gate drivers 210 to power supply units 220 conducting wire distance order from far near and increase progressively.That is, the falling edge of the positive pulse of gate drivers clock signal C PV sequentially adjusts toward positive time orientation from period P3 to period P1, so just sequentially can extend very first time T1 gradually.
Thus, the difference of the B point of sweep signal group S3, S2 and S1 and the low voltage level VL3 corresponding to it, VL2 and VL1 just can be more consistent, and then effectively eliminate or suppress the horizontal band-like district of different brightness of display frame.
In the driver module 200 of the display 100 of above-described embodiment, due to the multiple very first time interval T 1 between time of the rising edge of these sweep signal SC and the starting time of these corresponding respectively chamfering operation or and the termination time of these corresponding respectively chamfering operation between multiple second time interval T2 be sequentially increasing or decreasing for these different sweep signal groups, therefore can produce more consistent feed-trough voltage in the different horizontal band-shaped zone of display 100, and then make display frame comparatively even.Thus, just effectively can solve the problem in horizontal band-like district display frame occurring different brightness at drive end, namely can with comparatively simple and easy, to save time and cost-effective mode solves this problem.
Fig. 6 A is the calcspar of the display of another embodiment of the present invention, Fig. 6 B is the signal waveforms of the display driving Fig. 6 A, Fig. 7 is in the oscillogram of the sweep signal of Different periods in another comparative examples of the display panels driving Fig. 6 A, to be gate drivers initial pulse signal in the display of Fig. 6 A corresponding to the oscillogram of period of gate drivers different in Fig. 6 A from the output enable signal being sent to gate drivers to Fig. 8 A, and Fig. 8 B be sweep signal group different in the display of Fig. 6 A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.
Please also refer to Fig. 6 A and Fig. 6 B, the display 100d of the present embodiment and the display 100 of driver module 200d and Figure 1A thereof and driver module 200 similar, and both difference is as described below.In the present embodiment in display 100d, top rake circuit is positioned at power supply unit 220d (i.e. outside top rake), and its top rake circuit being different from the display 100 of Figure 1A is arranged in each gate drivers 210 (i.e. inner top rake).The top rake circuit being arranged in power supply unit 220d can realize with top rake circuit well-known to those skilled in the art.In the present embodiment, these chamfering operation of carrying out these sweep signal SC respectively carry out chamfering operation by power supply unit 220d to high levle signal VGH reached.The principle of operation of the top rake circuit in power supply unit 220d can be identical with the principle of operation of the top rake circuit in the gate drivers 210 of Figure 1A, that is produce drain electrode discharge current ID by the flash-over characteristic of transistor operation in saturation region.Now, due to apply the grid of so far transistor control voltage VGN referenced by voltage (such as low voltage level VL) only have one, therefore the absolute value of the top rake slope of its high levle signal VGH produced is identical in the day part of a picture frame time, so the absolute value being passed to the top rake slope of the high levle signal VGH of different gate drivers 210d (such as gate drivers 210dc, 210db and 210da) is also roughly the same.
In addition, in the present embodiment, top rake control signal is grid pulse modulation signal (gatepulsemodulationsignal) OE2 being sent to power supply unit 220d, and these chamfering operation of carrying out these sweep signal SC respectively carry out chamfering operation by the sequential of corresponding grid pulse modulation signal OE2 to high levle signal VGH reached.In the present embodiment, as Fig. 6 B illustrate, the time of the rising edge of the positive pulse of grid pulse modulation signal OE2 is the initial time corresponding to chamfering operation.Time thus, the level of high levle signal VGH declines gradually from high voltage level VH, and when the time of the falling edge of the positive pulse of grid pulse modulation signal OE2, the level just VH of switchback high voltage level again of high levle signal VGH.Thus, when sweep signal SC to be switched to high levle signal VGH and low level signal VGL according to gate drivers clock signal C PV by gate drivers 210d, the sweep signal SC through top rake can just be produced.
On the other hand, control module 230 also transmits output enable signal OE to gate drivers 210d, and therefore as the embodiment of Fig. 2, the time of the rising edge of the positive pulse of output enable signal OE also corresponds to the top rake termination time of sweep signal SC.In addition, in Fig. 6 B, 6th ~ 9 waveforms are sequentially the sweep signal SC on adjacent front 4 articles of sweep traces 310.
Please refer to Fig. 7, because the length of the conducting wire of power supply unit 220d to each gate drivers 210d is not identical, therefore can cause the sweep signal SC3 that gate drivers 210dc (it is farthest away from power supply unit 220d) exports " the sweep signal SC2 that exports than gate drivers 210db (its for time away from power supply unit 220d) of low voltage level VL3 " low voltage level VL2 closer to zero level, and the sweep signal SC2 that exports of gate drivers 210db (its for time away from power supply unit 220d) " the sweep signal SC1 that exports than gate drivers 210da (it is near power supply unit 220d) of low voltage level VL2 " low voltage level VL1 closer to zero level.Because voltage quasi position VL3, VL2 and VL1 are all negative level, therefore VL3>VL2>VL1.In addition, as mentioned above, due to when outside top rake, the absolute value of top rake slope is fixing, therefore, in a comparative examples, if when in different period P, output enable signal OE is identical with the pulsewidth of grid pulse modulation signal OE2, each sweep signal SC3 can be made ", SC2 " and SC1 " B point and the low voltage level VL3 corresponding to it, difference DELTA V3, the Δ V2 of VL2 and VL1 and Δ V1 unequal, be such as Δ V3> Δ V2> Δ V1.The unequal meeting of difference DELTA V3, Δ V2 and Δ V1 causes the not identical of feed-trough voltage, and then produces the horizontal band-shaped zone of different brightness.
Therefore, in the present embodiment, these second time intervals T2d size along with its corresponding respectively these gate drivers 210d to the distance of the conducting wire of power supply unit 220d order from far near and increase progressively.For example, as Fig. 8 B illustrate, the the second time T2dc corresponding to the sweep signal group S3 of gate drivers 210dc is less than the second time T2db of the sweep signal group S2 corresponding to gate drivers 210db, and the second time T2db corresponding to the sweep signal group S2 of gate drivers 210db is less than the second time T2da of the sweep signal group S1 corresponding to gate drivers 210da.
In the present embodiment, the size of the second time T2d in Different periods P3, P2 and P1 just can be changed by the pulsewidth W32 of the output enable signal OE of adjustment in Different periods P3, P2 and P1, the size (being such as the time of the rising edge of its positive pulse of adjustment) of W22 and W12.In the present embodiment, W32>W22>W12.Thus, can make the B point voltage level of each sweep signal group S3, S2 and S1 and the low voltage level VL3 corresponding to it, VL2 and VL1 difference more consistent, and then effectively suppress or eliminate the problem of horizontal band-shaped zone of different brightness in picture.
To be gate drivers initial pulse signal, grid pulse modulation signal and high levle signal in the display of one more embodiment of the present invention corresponding to the oscillogram of period of gate drivers 210d different in Fig. 6 A to Fig. 9 A, and Fig. 9 B be sweep signal group different in the display of Fig. 6 A sweep signal with the rising edge of its respective positive pulse for starting point coincide after waveform schematic diagram.Please refer to Fig. 6 A, Fig. 9 A and Fig. 9 B, the present embodiment is also adopt as the framework of the display 100d of Fig. 6 A, and as described below with not existing together of the embodiment of Fig. 8 A and Fig. 8 B.In the present embodiment, the sequentially increasing or decreasing of these very first times interval T 1d for different these sweep signals group S3, S2, S1 be by transmit respectively in different multiple period P3, P2, P1 have distinct pulse widths W33, W23, W13 grid pulse modulation signal OE2 to power supply unit 220d with high levle is carried out top rake dynamic institute reach.The distinct pulse widths of grid pulse modulation signal OE2 realizes by suitable pulse width modulation mechanism.
In the present embodiment, these very first times interval T 1d size along with its corresponding respectively these gate drivers 210d to the distance of the conducting wire of power supply unit 220d order from far near and successively decrease.For example, the very first time T1dc corresponding to the sweep signal group S3 of gate drivers 210dc is greater than the very first time T1db of the sweep signal group S2 corresponding to gate drivers 210db, and the very first time T1db corresponding to the sweep signal group S2 of gate drivers 210db is greater than the very first time T1da of the sweep signal group S1 corresponding to gate drivers 210da.
In the present embodiment, the size of very first time T1d in Different periods P3, P2 and P1 just can be changed by the pulsewidth W33 of the grid pulse-width signal OE2 of adjustment in Different periods P3, P2 and P1, the size (being such as the time of the rising edge of its positive pulse of adjustment) of W23 and W13.In the present embodiment, W33<W23<W13.Thus, can make the B point voltage level of each sweep signal group S3, S2 and S1 and the low voltage level VL3 corresponding to it, VL2 and VL1 difference more consistent, and then effectively suppress or eliminate the problem of horizontal band-shaped zone of different brightness in picture.
In certain embodiments, also propose the grid drive method of display, it realizes by the driver module 200 in the various embodiments described above, 200d.The grid drive method of this display comprises: sequentially provide respectively multiple sweep signal group S to these scanline groups G (as Figure 1A and Figure 1B illustrate), and each sweep signal group S comprises multiple sweep signal SC of the multiple sweep traces 310 being passed to corresponding scanline groups G respectively; And respectively multiple chamfering operation is carried out to these sweep signal SC, to reduce the high voltage level VH of these sweep signals.Multiple very first time interval T 1 between the time of the rising edge of these sweep signal SC and the starting time of these corresponding respectively chamfering operation or and the termination time of these corresponding respectively chamfering operation between multiple second time interval T2 be sequentially increasing or decreasing for different these sweep signals group S.The grid drive method of the display of these embodiments is described in detail in the various embodiments described above, and its detailed content please refer to above-described embodiment, no longer repeats at this.
In sum, in the grid drive method and driver module of the display of embodiments of the invention, due to the multiple very first time interval between time of the rising edge of these sweep signals and the starting time of these corresponding respectively chamfering operation or and the termination time of these corresponding respectively chamfering operation between multiple second time intervals be sequentially increasing or decreasing for these different sweep signal groups, therefore can produce more consistent feed-trough voltage in the different horizontal band-shaped zone of display, and then make display frame comparatively even.Thus, just effectively can solve the problem in horizontal band-like district display frame occurring different brightness at drive end, namely can with comparatively simple and easy, to save time and cost-effective mode solves this problem.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on accompanying claim.
Claims (20)
1. a grid drive method for display, described display comprises multiple sweep trace, and described multiple sweep trace is sequentially divided into multiple scanline groups, and the grid drive method of described display comprises:
Sequentially provide multiple sweep signal group to described multiple scanline groups respectively, wherein sweep signal group described in each comprises multiple sweep signals of the multiple sweep traces being passed to corresponding described scanline groups respectively; And
Respectively multiple chamfering operation is carried out to described multiple sweep signal, to reduce the high voltage level of described multiple sweep signal, the multiple very first time interval between the time of the rising edge of wherein said multiple sweep signal and the starting time of described multiple chamfering operation corresponding respectively or and the termination time of described multiple chamfering operation corresponding respectively between multiple second time intervals be sequentially increasing or decreasing for different described multiple sweep signal groups.
2. the grid drive method of display as claimed in claim 1, wherein said multiple sweep signal group exported from multiple gate drivers respectively, and the sequentially increasing or decreasing of described multiple second time interval for different described multiple sweep signal groups reaches to described multiple gate drivers by transmitting the output enable signal with distinct pulse widths in different multiple periods respectively.
3. the grid drive method of display as claimed in claim 2, wherein said multiple sweep signal group exported from multiple gate drivers respectively, drive singal described in each is switched by described gate drivers formed from the high levle signal of power supply unit and low level signal, described multiple chamfering operation of carrying out described multiple sweep signal respectively carries out chamfering operation by described multiple gate drivers of correspondence to described high levle signal reached, and the size in described multiple second time interval along with its corresponding respectively described multiple gate drivers to the distance of the conducting wire of described power supply unit order from far near and successively decrease.
4. the grid drive method of display as claimed in claim 2, wherein said multiple sweep signal group exported from multiple gate drivers respectively, drive singal described in each is switched by described gate drivers formed from the high levle signal of power supply unit and low level signal, described multiple chamfering operation of carrying out described multiple sweep signal respectively carries out chamfering operation by described power supply unit to described high levle signal reached, and the size in described multiple second time interval along with its corresponding respectively described multiple gate drivers to the distance of the conducting wire of described power supply unit order from far near and increase progressively.
5. the grid drive method of display as claimed in claim 1, wherein said multiple sweep signal group exported from multiple gate drivers respectively, and the sequentially increasing or decreasing of described multiple very first time interval for different described multiple sweep signal groups reaches to described multiple gate drivers by transmitting the gate drivers clock signal with distinct pulse widths in different multiple periods respectively.
6. the grid drive method of display as claimed in claim 5, wherein said multiple sweep signal group exported from multiple gate drivers respectively, drive singal described in each is that the high levle signal switched from power supply unit by described gate drivers formed with low level signal, and the size at described multiple very first time interval along with its respectively correspondence described multiple gate drivers extremely the distance of the conducting wire of described power supply unit order from far near and increase progressively.
7. the grid drive method of display as claimed in claim 1, wherein said multiple sweep signal group exported from multiple gate drivers respectively, drive singal described in each is switched by described gate drivers formed from the high levle signal of power supply unit and low level signal, and described multiple chamfering operation of carrying out described multiple sweep signal respectively carries out chamfering operation by described power supply unit to described high levle signal reached.
8. the grid drive method of display as claimed in claim 7, the sequentially increasing or decreasing of wherein said multiple very first time interval for different described multiple sweep signal groups reached to carry out chamfering operation to described high levle by transmitting grid pulse modulation signal to the described power supply unit with distinct pulse widths in different multiple periods respectively.
9. the grid drive method of display as claimed in claim 8, the size at wherein said multiple very first time interval along with the corresponding respectively described multiple gate drivers of its institute extremely the distance of the conducting wire of described power supply unit order from far near and successively decrease.
10. the grid drive method of display as claimed in claim 1, wherein said display is liquid crystal display.
11. 1 kinds of driver modules, in order to driving display, described display comprises multiple sweep trace, and described multiple sweep trace is sequentially divided into multiple scanline groups, and described driver module comprises:
Multiple gate drivers, sequentially provide multiple sweep signal group to described multiple scanline groups respectively, and sweep signal group described in each comprises multiple sweep signals of the multiple sweep traces being passed to corresponding described scanline groups respectively;
Power supply unit, in order to provide high levle signal and low level signal to described multiple gate drivers, and described multiple gate drivers forms described multiple sweep signal by the described high levle signal of switching and described low level signal; And
Control module, transmit top rake and control signal to described multiple gate drivers or described power supply unit, to carry out multiple chamfering operation to described multiple sweep signal respectively, and then reduce the high voltage level of described multiple sweep signal, multiple very first time interval between the time of the rising edge of wherein said multiple sweep signal and the starting time of described multiple chamfering operation corresponding respectively or and the termination time of described multiple chamfering operation corresponding respectively between multiple second time intervals be sequentially increasing or decreasing for different described multiple sweep signal groups.
12. driver modules as claimed in claim 11, wherein said top rake control signal is the output enable signal being sent to described multiple gate drivers, and the sequentially increasing or decreasing of described multiple second time interval for different described multiple sweep signal groups reaches to described multiple gate drivers by transmitting the described output enable signal with distinct pulse widths in different multiple periods respectively.
13. driver modules as claimed in claim 12, described multiple chamfering operation of wherein carrying out described multiple sweep signal respectively carries out chamfering operation by described multiple gate drivers of correspondence to described high levle signal reached, and the size in described multiple second time interval along with its corresponding respectively described multiple gate drivers to the distance of the conducting wire of described power supply unit order from far near and successively decrease.
14. driver modules as claimed in claim 12, described multiple chamfering operation of wherein carrying out described multiple sweep signal respectively carries out chamfering operation by described power supply unit to described high levle signal reached, and the size in described multiple second time interval along with its corresponding respectively described multiple gate drivers to the distance of the conducting wire of described power supply unit order from far near and increase progressively.
15. driver modules as claimed in claim 11, wherein said top rake control signal is the gate drivers clock signal being sent to described multiple gate drivers, and the sequentially increasing or decreasing of described multiple very first time interval for different described multiple sweep signal groups reaches to described multiple gate drivers by transmitting the described gate drivers clock signal with distinct pulse widths in different multiple periods respectively.
16. driver modules as claimed in claim 15, the size at wherein said multiple very first time interval along with its corresponding respectively described multiple gate drivers to the distance of the conducting wire of described power supply unit order from far near and increase progressively.
17. driver modules as claimed in claim 11, wherein said top rake control signal is the grid pulse modulation signal being sent to described power supply unit, and described multiple chamfering operation of carrying out described multiple sweep signal respectively carries out chamfering operation by the sequential of the described grid pulse modulation signal of correspondence to described high levle signal reached.
18. driver modules as claimed in claim 17, the sequentially increasing or decreasing of wherein said multiple very first time interval for different described multiple sweep signal groups be by transmit respectively in different multiple periods the described grid pulse modulation signal with distinct pulse widths to described power supply unit with described high levle is carried out top rake dynamic institute reach.
19. driver modules as claimed in claim 18, the size at wherein said multiple very first time interval along with its corresponding respectively described multiple gate drivers to the distance of the conducting wire of described power supply unit order from far near and successively decrease.
20. driver modules as claimed in claim 11, wherein said display is liquid crystal display.
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