CN108320717A - A kind of GOA driving circuits and its liquid crystal display panel of preparation - Google Patents
A kind of GOA driving circuits and its liquid crystal display panel of preparation Download PDFInfo
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- CN108320717A CN108320717A CN201810115595.3A CN201810115595A CN108320717A CN 108320717 A CN108320717 A CN 108320717A CN 201810115595 A CN201810115595 A CN 201810115595A CN 108320717 A CN108320717 A CN 108320717A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 21
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000010409 thin film Substances 0.000 claims description 79
- 239000010408 film Substances 0.000 claims description 21
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000012423 maintenance Methods 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000007599 discharging Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
The present invention provides a kind of GOA driving circuits and its liquid crystal display panel of preparation, by the way that two DC low-voltage cablings are arranged, and TFT devices are added, the grid of the TFT devices is made to be connected to the first direct low voltage signal, source electrode accesses the second direct low voltage signal, and drain electrode is connected to first node.And so that the clock trigger signal current potential of 1 grade of GOA unit of N is slowly drawn high to zero potential by initial low-frequency ac signal in shutdown moment, the second direct low voltage signal current potential is slowly drawn high by initial low potential to zero potential.Effective electric discharge of GOA circuits and pixel electrode, improves the reliability and stability of liquid crystal display panel when being shut down with realizing.
Description
Technical field
The present invention relates to field of liquid crystal display more particularly to a kind of GOA driving circuits and its liquid crystal display panel of preparation.
Background technology
The basic conception of GOA (Gate Driver on Array) is that the gate driving circuit of TFT LCD is integrated in glass
On glass substrate, the turntable driving to liquid crystal display panel is formed.GOA can be saved significantly compared to traditional actuation techniques using COF
About manufacturing cost, and the Bonging processing procedures of the sides Gate COF are eliminated, it is also extremely advantageous to be promoted to production capacity.
In order to realize liquid crystal display panel shutdown repid discharge, existing conventional means is the whole GOA signals made in liquid crystal display panel
(clock signal, clock trigger signal, low level signal, high level signal) is drawn high to realize the repid discharge of pixel.When above-mentioned
When signal is all raised, whole grid signals in liquid crystal display panel are pulled to high potential, at this point, in pixel at the grid of TFT
In high potential, quick discharge function may be implemented in pixel electrode, and under above-mentioned shutdown current potential facilities, pixel electrode is can be with
Realize and effectively discharge, but since all GOA signals are pulled to high potential, Q points at different levels are similarly in high potential, when into
The quick open and close of row are motor-driven when making, when being switched on next time, since multistage Q points are in high potential, cause in pull-up unit with Q points
It couples and is electrically connected clock signal and the multi-level thin film transistor for generating scanning signal is opened, thus would be possible to draw
The high current phenomenon of clock signal is sent out, triggering OCP (over current protect) leads to the phenomenon of picture exception.
Invention content
The present invention provides a kind of GOA driving circuits and its liquid crystal display panel of preparation, and GOA drives when can realize shutdown
Effective electric discharge of circuit and pixel electrode, improves the reliability and stability of liquid crystal display panel, to avoid triggering OCP from leading to picture
Abnormal phenomenon.
To solve the above problems, technical solution provided by the invention is as follows：
The present invention provides a kind of GOA driving circuits, is applied in display panel, including：
At least two mutual cascade GOA units, wherein N grades of GOA units include：Pull-up unit, pull-up control unit,
Lower leaflet member, drop-down unit, drop-down maintenance unit, auxiliary unit and bootstrap capacitor unit；Wherein,
The pull-up control unit, couple first node and be electrically connected at N-1 grades of GOA units scanning signal and
The clock trigger signal of N-1 grades of GOA units is used for the scanning signal according to the N-1 grades of GOA units and the N-
The clock trigger signal of 1 grade of GOA unit generates first segment point control signal；
The bootstrap capacitor unit, the current potential for storing the first segment point control signal；
The pull-up unit couples the first node and is electrically connected clock signal, for according to the first node
It controls signal and the clock signal generates the scanning signal of N grades of GOA units；
The lower leaflet member, couples the first node and is electrically connected the clock signal, for according to described first
Node control signal generates the clock trigger signal of N grades of GOA units with the clock signal；
The drop-down unit couples the first node and is electrically connected the scanning signal of the N grades of GOA units, uses
In dragging down the current potential of the first segment point control signal, and drag down the current potential of the scanning signal of the N grades of GOA units；
The drop-down maintenance unit couples the first node and is electrically connected the scanning letter of the N grades of GOA units
Number, the current potential for maintaining the first segment point control signal, and maintain the electricity of the scanning signal of the N grades of GOA units
Position；
The auxiliary unit, couples the first node and the first direct low voltage signal of electric connection and the second direct current are low
Voltage signal, the moment for shutting down in the display panel, directly according to first direct low voltage signal and described second
Stream low voltage signal drags down the current potential of the first segment point control signal.
According to one preferred embodiment of the present invention, the pull-up control unit includes first film transistor；
The grid of the first film transistor accesses the clock trigger signal of the N-1 grades of GOA units, source electrode access
The scanning signal of the N-1 grades of GOA units, drain electrode are connect with the first node.
According to one preferred embodiment of the present invention, the pull-up unit includes the second thin film transistor (TFT)；
The grid of second thin film transistor (TFT) is connect with the first node, and source electrode accesses the clock signal, drain electrode
It is connect with the output end of the scanning signal of the N grades of GOA units.
According to one preferred embodiment of the present invention, the lower leaflet member includes third thin film transistor (TFT)；
The grid of the third thin film transistor (TFT) is connect with the first node, and source electrode accesses the clock signal, drain electrode
It is connect with the output end of the clock trigger signal of the N grades of GOA units.
According to one preferred embodiment of the present invention, the drop-down unit includes：4th thin film transistor (TFT), the 5th film crystal
Pipe；
The grid of 4th thin film transistor (TFT) accesses the scanning signal of the N+1 grades of GOA units, described in source electrode access
First direct low voltage signal, drain electrode are connect with the output end of the scanning signal of the N grades of GOA units；
The grid of 5th thin film transistor (TFT) accesses the scanning signal of the N+1 grades of GOA units, described in source electrode access
Second direct low voltage signal, drain electrode are connect with the first node.
According to one preferred embodiment of the present invention, the drop-down maintenance unit includes：6th thin film transistor (TFT), the 7th film are brilliant
Body pipe, the 8th thin film transistor (TFT), the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT)；
The grid of 6th thin film transistor (TFT) accesses DC high voltage signal, drain electrode and the 7th film with source electrode
The grid of the drain electrode of transistor and the 8th thin film transistor (TFT) connects；
The grid of 7th thin film transistor (TFT) is connect with the grid of the first node and the 9th thin film transistor (TFT),
Source electrode accesses first direct low voltage signal；
The source electrode of 8th thin film transistor (TFT) accesses the DC high voltage signal, drain electrode and the 9th film crystal
The grid connection of the draining of pipe, the grid of the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT)；
9th thin film transistor (TFT) source electrode accesses first direct low voltage signal；
The source electrode of tenth thin film transistor (TFT) accesses first direct low voltage signal, misses and the N grades of GOA
The output end of the scanning signal of unit connects；
The source electrode of 11st thin film transistor (TFT) accesses second direct low voltage signal, drain electrode and the first segment
Point connection.
According to one preferred embodiment of the present invention, the auxiliary unit includes the 12nd thin film transistor (TFT)；
The grid of 12nd thin film transistor (TFT) accesses first direct low voltage signal, source electrode access described second
Direct low voltage signal, drain electrode are connect with the first node.
According to one preferred embodiment of the present invention, the bootstrap capacitor unit includes bootstrap capacitor；
One end of the bootstrap capacitor is connect with the first node, the scanning of the other end and the N grades of GOA units
The output end of signal connects.
According to one preferred embodiment of the present invention, it is low to be less than second direct current for the current potential of first direct low voltage signal
The current potential of voltage signal, and in the moment of display panel shutdown, the current potential of first direct low voltage signal is pulled to
Zero potential is slowly lowered to after high potential, the clock trigger signal of the N-1 grades of GOA units is slowly dropped by initial high potential
Down to zero potential.
The present invention also provides a kind of liquid crystal display panels prepared using above-described GOA driving circuits.
Beneficial effects of the present invention are：Compared to the GOA driving circuits of available liquid crystal display panel, GOA of the invention drives
Dynamic circuit and its liquid crystal display panel of preparation, by the way that direct low voltage signal is split as two cablings by a cabling, and
Assist dragging down first node current potential by adding TFT in GOA driving circuits, while in the wink of display panel shutdown
Between, design the clock signal, the clock trigger signal, the direct low voltage signal, first DC low-voltage letter
Number and second direct low voltage signal potential change, shutdown action moment all first nodes are pulled to low electricity
Position passes structure compared to grade and is conducive to improve response speed, avoids when being switched on next time, trigger OCP and lead to picture exception
Phenomenon.Effective electric discharge of GOA circuits and pixel electrode, improves the reliability and stability of liquid crystal display panel when realizing shutdown.
Description of the drawings
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some invented
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the circuit diagram of GOA circuits provided in an embodiment of the present invention；
Fig. 2 is the sequence diagram of GOA circuits provided in an embodiment of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes.Obviously, described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, the every other implementation that those skilled in the art are obtained without creative efforts
Example, shall fall within the protection scope of the present invention.
The GOA driving circuits of specific embodiment of the invention offer are provided below in conjunction with the accompanying drawings.
Refering to fig. 1, Fig. 1 is the circuit diagram of GOA circuits provided in an embodiment of the present invention.As shown in Figure 1, the embodiment of the present invention
A kind of GOA circuits, including at least two mutual cascade GOA units are provided, wherein N grades of GOA units include：Pull-up control is single
Member 1, pull-up unit 2, lower leaflet member 3, drop-down unit 4, drop-down maintenance unit 5, bootstrap capacitor unit 6 and auxiliary unit 7.Institute
Stating N grades of GOA unit inputs has the clock triggering of the scanning signal G (N-1) of N-1 grades of GOA units, N-1 grades of GOA units to believe
Number STV (N-1), clock signal CK (N), the first direct low voltage signal VSSG, the second direct low voltage signal VSSQ and straight
Flow high voltage signal LC：Wherein, the current potential of the first direct low voltage signal VSSG is believed less than second DC low-voltage
The current potential of number VSSQ.
Wherein, the pull-up control unit 1, coupling first node Q (N) are simultaneously electrically connected at the N-1 grades of GOA units
Scanning signal G (N-1) and the N-1 grades of GOA units clock trigger signal STV (N-1), for according to the N-
The scanning signal G (N-1) of the 1 grade of GOA unit and clock trigger signal STV (N-1) of the N-1 grades of GOA units generates the
One node control signal；The scanning signal G (N-1) of the N-1 grades of GOA units and the clock of the N-1 grades of GOA units
Trigger signal STV (N-1) is generated by N-1 grades of GOA unit, for triggering N grades of the GOA unit, predominantly institute
It states first node Q (N) and realizes precharge.
Specifically, the pull-up control unit 1 includes：First film transistor T11；The first film transistor T11
Grid access the clock trigger signal STV (N-1) of the N-1 grades of GOA units, source electrode accesses the N-1 grades of GOA units
Scanning signal G (N-1), drain electrode connect with the first node Q (N).
The bootstrap capacitor unit 6, the current potential for storing the first segment point control signal；Specifically, the bootstrapping
Capacitor cell 6 includes bootstrap capacitor Cbt；One end of the bootstrap capacitor Cbt is connect with the first node Q (N), the other end with
The output end of the scanning signal G (N) of N grades of GOA units connects.
The pull-up unit 2 couples the first node Q (N) and is electrically connected the clock signal CK (N), is used for basis
The first segment point control signal and the clock signal CK (N) generate the scanning signal G (N) of the N grades of GOA units.
Specifically, the pull-up unit 2 includes the second thin film transistor (TFT) T21；The grid of the second thin film transistor (TFT) T21
It is connect with the first node Q (N), source electrode accesses the clock signal CK (N), the scanning of drain electrode and the N grades of GOA units
The output end of signal G (N) connects.
The lower leaflet member 3 couples the first node Q (N) and is electrically connected the clock signal CK (N), is used for root
The clock trigger signal ST (N) of N grades of GOA units is generated according to the first segment point control signal and the clock signal CK (N)；
The clock trigger signal ST (N) of the N grades of GOA units is used to trigger N+1 grades of GOA unit.
Specifically, the lower leaflet member 3 includes third thin film transistor (TFT) T22；The grid of the third thin film transistor (TFT) T22
It is connect with the first node Q (N), source electrode accesses the clock signal CK (N), drains described with the N grades of GOA units
The output end of clock trigger signal ST (N) connects.
The drop-down unit 4 couples the first node Q (N) and is electrically connected the scanning letter of the N grades of GOA units
Number G (N), the current potential for dragging down the first segment point control signal, and drag down the scanning signal G of the N grades of GOA units
(N) current potential.
Specifically, the drop-down unit 4 includes：4th thin film transistor (TFT) T31, the 5th thin film transistor (TFT) T41；Described 4th
The grid of thin film transistor (TFT) T31 accesses the scanning signal G (N+1) of the N+1 grades of GOA units, and source electrode access described first is straight
Low voltage signal VSSG is flowed, drain electrode is connect with the output end of the scanning signal G (N) of the N grades of GOA units；Described 5th is thin
The grid of film transistor T41 accesses the scanning signal G (N+1) of the N+1 grades of GOA units, and source electrode accesses second direct current
Low voltage signal VSSQ, drain electrode are connect with the first node Q (N).
The drop-down maintenance unit 5 couples the first node Q (N) and is electrically connected N grades of the described of GOA unit and sweeps
Signal G (N) is retouched, the current potential for maintaining the first segment point control signal, and maintain the described of the N grades of GOA units
The current potential of scanning signal G (N).Electronic component in the drop-down maintenance unit 5 is actually a kind of phase inverter, including high level
Signal, low level signal, when input terminal inputs high potential signal, output end exports low-potential signal, when input terminal input is low
When electric potential signal, output end exports high potential signal.
Specifically, the drop-down maintenance unit 5 includes：6th thin film transistor (TFT) T51, the 7th thin film transistor (TFT) T52, the 8th
Thin film transistor (TFT) T53, the 9th thin film transistor (TFT) T54, the tenth thin film transistor (TFT) T32, the 11st thin film transistor (TFT) T42；
The grid of the 6th thin film transistor (TFT) T51 accesses the DC high voltage signal LC, drain electrode and institute with source electrode
State the drain electrode of the 7th thin film transistor (TFT) T52 and the grid connection of the 8th thin film transistor (TFT) T53；
The grid of the 7th thin film transistor (TFT) T52 and the first node Q (N) and the 9th thin film transistor (TFT) T54
Grid connection, source electrode accesses the first direct low voltage signal VSSG；
The source electrode of the 8th thin film transistor (TFT) T53 accesses the DC high voltage signal LC, drains and the described 9th is thin
The draining of film transistor T54, the grid of the grid of the tenth thin film transistor (TFT) T32 and the 11st thin film transistor (TFT) T42
Pole connects；
The 9th thin film transistor (TFT) T54 source electrodes access the first direct low voltage signal VSSG；
The source electrode of the tenth thin film transistor (TFT) T32 accesses the first direct low voltage signal VSSG, miss with it is described
The output end of the scanning signal G (N) of N grades of GOA units connects；
The source electrode of the 11st thin film transistor (TFT) T42 accesses the second direct low voltage signal VSSQ, drain electrode and institute
State first node Q (N) connections.
The auxiliary unit 7, couple the first node Q (N) and be electrically connected the first direct low voltage signal VSSG and
Second direct low voltage signal VSSQ, the moment for shutting down in the display panel believe according to first DC low-voltage
Number VSSG and the second direct low voltage signal VSSQ drags down the current potential of the first segment point control signal.
Specifically, the auxiliary unit 7 includes the 12nd thin film transistor (TFT) Tgq；The 12nd thin film transistor (TFT) Tgq's
Grid accesses the first direct low voltage signal VSSG, and source electrode accesses the second direct low voltage signal VSSQ, drain electrode with
First node Q (N) connection.
As shown in Fig. 2, for the sequence diagram of GOA circuits provided in an embodiment of the present invention.In the wink of display panel shutdown
Between, the shutdown current potential situation of GOA circuits is as follows：Clock signal CK is pulled to after high potential slowly by initial high frequency ac signal
It is reduced to zero potential, clock trigger signal STV slowly to be drawn high to zero potential, DC high voltage letter by initial low-frequency ac signal
Number LC is slowly lowered to zero potential by initial high potential, and the first direct low voltage signal VSSG is pulled to by initial low potential
Zero potential is slowly lowered to after high potential, the second direct low voltage signal VSSQ is slowly drawn high by initial low potential to zero electricity
Position.To realize that the moment shut down in the display panel, the display panel can quickly discharge.
Specifically, the display panel is divided into display unit and GOA circuit units, when the display panel works normally
When, the gate input voltage Vgs of the 12nd thin film transistor (TFT) Tgq is consistently less than 0 and is closed, and described second is straight
Stream low voltage signal VSSQ will not impact the waveform of the first node.When carrying out shutdown action, for the GOA
The electric discharge of circuit unit should maintain the low potential (not form a high potential at least) of first node Q；It is single for the display
All grid signals, should be pulled to high potential (at least to form a high potential) by the circuit discharging of member.It is mono- with N grades of GOA
For member, under the design of above-mentioned current potential situation, wherein the electric discharge of the GOA circuit units：When N-1 grades of GOA units export
Clock trigger signal STV (N-1) be low potential when, the first film transistor T11 is in off state, and N-1 grades of GOA are mono-
The high potential of the scanning signal G (N-1) of member output does not interfere with the current potential of first node Q (N) points；Described first when input is straight
When stream low voltage signal VSSG is high potential, the second direct low voltage signal VSSQ is low potential, the auxiliary unit
The 12nd thin film transistor (TFT) Tgq is open state, and the first node Q (N) is by second direct low voltage signal
VSSQ is persistently dragged down；It is described when first node Q (N) point is low potential, the DC high voltage signal LC is high potential
11st thin film transistor (TFT) T42 is open state, and the first node Q (N) is held by the second direct low voltage signal VSSQ
It is continuous to drag down；When the scanning signal G (N+1) of N+1 grades of GOA units points are high potential, the 5th thin film transistor (TFT) T41
For open state, the first node Q (N) is persistently dragged down by the second direct low voltage signal VSSQ.
The circuit discharging of the display unit：When the first node Q (N) is low potential, second film crystal
Pipe T21 is in off state, and the clock signal CK does not interfere with the current potential of the scanning signal G (N) of the N grades of GOA units；When
When the first node Q (N) is low potential, the DC high voltage signal LC is high potential, the tenth thin film transistor (TFT) T32
Scanning signal G (N) for open state, the N grades of GOA units is persistently drawn by the first direct low voltage signal VSSG
It is low；When the scanning signal G (N+1) of the N+1 grades of GOA units is high potential, the 4th thin film transistor (TFT) T31 is to open
The scanning signal G (N) of state, the N grades of GOA units is persistently dragged down by the first direct low voltage signal VSSG.
Wherein, the waveform of the clock signal CK can't cause to significantly affect to electric discharge, thus, GOA of the invention electricity
The more traditional setting of waveform of clock signal CK described in line structure simultaneously is not required to change.Furthermore, it is necessary to which supplementary explanation is GOA electricity
Road is that grade passes, and in order to realize quick electric discharge in the present invention, the 12nd thin film transistor (TFT) Tgq of the auxiliary unit can
To own with the moment in the first direct low voltage signal VSSG, the second direct low voltage signal VSSQ potential changes
First node Q points are pulled to low potential, and passing structure compared to grade is conducive to improve response speed.
The present invention also provides a kind of liquid crystal display panels prepared using above-mentioned GOA driving circuits.
Compared to the GOA driving circuits of available liquid crystal display panel, the liquid crystal of GOA driving circuits of the invention and its preparation
Display panel, by the way that direct low voltage signal is split as two cablings by a cabling, and by increasing in GOA driving circuits
If TFT assists dragging down first node current potential, while in the moment of display panel shutdown, designing the clock signal, institute
State clock trigger signal, the direct low voltage signal, first direct low voltage signal and the low electricity of second direct current
All first nodes are pulled to low potential by the potential change for pressing signal in the moment of shutdown action, and passing structure compared to grade is conducive to
Response speed is improved, is avoided when being switched on next time, OCP is triggered and leads to the phenomenon of picture exception.GOA circuits when realizing shutdown
With effective electric discharge of pixel electrode, improve the reliability and stability of liquid crystal display panel
In conclusion although the present invention is disclosed above with preferred embodiment, above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention is subject to the range that claim defines.
Claims (10)
1. a kind of GOA driving circuits are applied in display panel, which is characterized in that including：
At least two mutual cascade GOA units, wherein N grades of GOA units include：Pull-up unit, passes down pull-up control unit
Unit, drop-down unit, drop-down maintenance unit, auxiliary unit and bootstrap capacitor unit；Wherein,
The pull-up control unit couples first node and is electrically connected at the scanning signal and N- of N-1 grades of GOA units
The clock trigger signal of 1 grade of GOA unit, for according to the scanning signal of the N-1 grades of GOA units and N-1 grades described
The clock trigger signal of GOA unit generates first segment point control signal；
The bootstrap capacitor unit, the current potential for storing the first segment point control signal；
The pull-up unit couples the first node and is electrically connected clock signal, for being controlled according to the first node
Signal and the clock signal generate the scanning signal of N grades of GOA units；
The lower leaflet member, couples the first node and is electrically connected the clock signal, for according to the first node
Control the clock trigger signal that signal generates N grades of GOA units with the clock signal；
The drop-down unit couples the first node and is electrically connected the scanning signal of the N grades of GOA units, for drawing
The current potential of the low first segment point control signal, and drag down the current potential of the scanning signal of the N grades of GOA units；
The drop-down maintenance unit couples the first node and is electrically connected the scanning signal of the N grades of GOA units, uses
In the current potential for maintaining the first segment point control signal, and maintain the current potential of the scanning signal of the N grades of GOA units；
The auxiliary unit couples the first node and is electrically connected the first direct low voltage signal and the second DC low-voltage
Signal is the moment for shutting down in the display panel, low according to first direct low voltage signal and second direct current
Voltage signal drags down the current potential of the first segment point control signal.
2. GOA driving circuits according to claim 1, which is characterized in that the pull-up control unit includes the first film
Transistor；
The grid of the first film transistor accesses the clock trigger signal of the N-1 grades of GOA units, described in source electrode access
The scanning signal of N-1 grades of GOA units, drain electrode are connect with the first node.
3. GOA driving circuits according to claim 1, which is characterized in that the pull-up unit includes the second film crystal
Pipe；
The grid of second thin film transistor (TFT) is connect with the first node, and source electrode accesses the clock signal, drain electrode and institute
State the output end connection of the scanning signal of N grades of GOA units.
4. GOA driving circuits according to claim 1, which is characterized in that the lower leaflet member includes third film crystal
Pipe；
The grid of the third thin film transistor (TFT) is connect with the first node, and source electrode accesses the clock signal, drain electrode and institute
State the output end connection of the clock trigger signal of N grades of GOA units.
5. GOA driving circuits according to claim 1, which is characterized in that the drop-down unit includes：4th film crystal
Pipe, the 5th thin film transistor (TFT)；
The grid of 4th thin film transistor (TFT) accesses the scanning signal of the N+1 grades of GOA units, source electrode access described first
Direct low voltage signal, drain electrode are connect with the output end of the scanning signal of the N grades of GOA units；
The grid of 5th thin film transistor (TFT) accesses the scanning signal of the N+1 grades of GOA units, source electrode access described second
Direct low voltage signal, drain electrode are connect with the first node.
6. GOA driving circuits according to claim 1, which is characterized in that the drop-down maintenance unit includes：6th film
Transistor, the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st film
Transistor；
The grid of 6th thin film transistor (TFT) accesses DC high voltage signal, drain electrode and the 7th film crystal with source electrode
The grid of the drain electrode of pipe and the 8th thin film transistor (TFT) connects；
The grid of 7th thin film transistor (TFT) is connect with the grid of the first node and the 9th thin film transistor (TFT), source electrode
Access first direct low voltage signal；
The source electrode of 8th thin film transistor (TFT) accesses the DC high voltage signal, drain electrode and the 9th thin film transistor (TFT)
The grid connection of drain electrode, the grid of the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT)；
9th thin film transistor (TFT) source electrode accesses first direct low voltage signal；
The source electrode of tenth thin film transistor (TFT) accesses first direct low voltage signal, misses and the N grades of GOA units
Scanning signal output end connection；
The source electrode of 11st thin film transistor (TFT) accesses second direct low voltage signal, and drain electrode connects with the first node
It connects.
7. GOA driving circuits according to claim 1, which is characterized in that the auxiliary unit includes that the 12nd film is brilliant
Body pipe；
The grid of 12nd thin film transistor (TFT) accesses first direct low voltage signal, and source electrode accesses second direct current
Low voltage signal, drain electrode are connect with the first node.
8. GOA driving circuits according to claim 1, which is characterized in that the bootstrap capacitor unit includes bootstrap capacitor；
One end of the bootstrap capacitor is connect with the first node, the scanning signal of the other end and the N grades of GOA units
Output end connection.
9. according to claim 1-8 any one of them GOA driving circuits, which is characterized in that the first DC low-voltage letter
Number current potential be less than second direct low voltage signal current potential, and the display panel shutdown moment, described first
The current potential of direct low voltage signal is slowly lowered to zero potential after being pulled to high potential, and the clock of the N-1 grades of GOA units touches
It signals to be slowly lowered to zero potential by initial high potential.
10. liquid crystal display panel prepared by a kind of GOA driving circuits using described in claim 1~9 any claim.
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| CN201810115595.3A CN108320717B (en) | 2018-02-06 | 2018-02-06 | GOA driving circuit and liquid crystal display panel prepared by same |
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| CN201810115595.3A CN108320717B (en) | 2018-02-06 | 2018-02-06 | GOA driving circuit and liquid crystal display panel prepared by same |
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| CN108320717B CN108320717B (en) | 2020-12-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831400A (en) * | 2018-07-26 | 2018-11-16 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and its driving method including GOA circuit |
| CN108962178A (en) * | 2018-09-03 | 2018-12-07 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display panel |
| CN109410820A (en) * | 2018-12-15 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN109616068A (en) * | 2019-01-04 | 2019-04-12 | 深圳市华星光电半导体显示技术有限公司 | GOA scanning circuit and liquid crystal display device |
| CN110619856A (en) * | 2019-08-23 | 2019-12-27 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN110767189A (en) * | 2019-10-12 | 2020-02-07 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display device |
| WO2020124822A1 (en) * | 2018-12-21 | 2020-06-25 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
| CN111402828A (en) * | 2020-04-09 | 2020-07-10 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN112185314A (en) * | 2020-10-19 | 2021-01-05 | Tcl华星光电技术有限公司 | Voltage conversion circuit and display device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104732945A (en) * | 2015-04-09 | 2015-06-24 | 京东方科技集团股份有限公司 | Shifting register, drive method, array substrate grid drive device and display panel |
| CN106205528A (en) * | 2016-07-19 | 2016-12-07 | 深圳市华星光电技术有限公司 | A kind of GOA circuit and display panels |
| US20170018245A1 (en) * | 2015-07-17 | 2017-01-19 | Samsung Display Co., Ltd. | Gate driving circuit and display apparatus having the same |
| CN106504720A (en) * | 2017-01-04 | 2017-03-15 | 合肥鑫晟光电科技有限公司 | Shift register cell and its driving method, gate drive apparatus and display device |
-
2018
- 2018-02-06 CN CN201810115595.3A patent/CN108320717B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104732945A (en) * | 2015-04-09 | 2015-06-24 | 京东方科技集团股份有限公司 | Shifting register, drive method, array substrate grid drive device and display panel |
| US20170018245A1 (en) * | 2015-07-17 | 2017-01-19 | Samsung Display Co., Ltd. | Gate driving circuit and display apparatus having the same |
| CN106205528A (en) * | 2016-07-19 | 2016-12-07 | 深圳市华星光电技术有限公司 | A kind of GOA circuit and display panels |
| CN106504720A (en) * | 2017-01-04 | 2017-03-15 | 合肥鑫晟光电科技有限公司 | Shift register cell and its driving method, gate drive apparatus and display device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831400A (en) * | 2018-07-26 | 2018-11-16 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and its driving method including GOA circuit |
| WO2020019433A1 (en) * | 2018-07-26 | 2020-01-30 | 深圳市华星光电技术有限公司 | Liquid crystal panel comprising goa circuit and driving method for liquid crystal panel |
| WO2020048081A1 (en) * | 2018-09-03 | 2020-03-12 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal panel |
| CN108962178A (en) * | 2018-09-03 | 2018-12-07 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display panel |
| CN109410820A (en) * | 2018-12-15 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN109410820B (en) * | 2018-12-15 | 2020-05-22 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| WO2020124822A1 (en) * | 2018-12-21 | 2020-06-25 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
| CN109616068A (en) * | 2019-01-04 | 2019-04-12 | 深圳市华星光电半导体显示技术有限公司 | GOA scanning circuit and liquid crystal display device |
| WO2021027091A1 (en) * | 2019-08-13 | 2021-02-18 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
| US11355044B2 (en) | 2019-08-13 | 2022-06-07 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | GOA circuit and display panel |
| CN110619856A (en) * | 2019-08-23 | 2019-12-27 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN110767189A (en) * | 2019-10-12 | 2020-02-07 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display device |
| CN111402828A (en) * | 2020-04-09 | 2020-07-10 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN112185314A (en) * | 2020-10-19 | 2021-01-05 | Tcl华星光电技术有限公司 | Voltage conversion circuit and display device |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |