CN109359067A - Obtain the method and system of memory module internal delay time ladder time - Google Patents
Obtain the method and system of memory module internal delay time ladder time Download PDFInfo
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- CN109359067A CN109359067A CN201811210591.XA CN201811210591A CN109359067A CN 109359067 A CN109359067 A CN 109359067A CN 201811210591 A CN201811210591 A CN 201811210591A CN 109359067 A CN109359067 A CN 109359067A
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- communication interface
- time
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- memory module
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The invention discloses the method and system for obtaining the memory module internal delay time ladder time, belong to field of communication technology.The method for obtaining the memory module internal delay time ladder time are as follows: under at least two different sampled points of the clock source, delay process is carried out to the communication interface respectively, obtains two boundaries of the communication interface；The delay time of a delayed step is calculated according to the difference of the delayed step number between the two of the communication interface boundaries.The present invention is by carrying out delay process to communication interface under the different sampled points of clock source, obtain two boundaries of the corresponding communication interface under different sampled points, the delay time of single delayed step is calculated further according to the different delayed time ladder number under different sampled points, in order to which the delay time carried out according to the practical delay time for calculating the delayed step obtained to control unit is adjusted, the stability of memory module is improved.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of methods for obtaining the memory module internal delay time ladder time
And system.
Background technique
In SDIO (Secure Digital Input and Output, secure digital input and output) interface in use, with
The increase of frequency, the problem of SDIO stability be also slowly exposed.In practical application, such as: SDIO unit is to SOC chip
When read signal, although the specification according to SOC chip (System-on-a-Chip) can obtain the unit step of its internal delay time
Duration, but not necessarily accurately, if the duration of unit step is wrong, can mislead in register setting, in turn
Stability of influence system during read signal.However at present can not unit step to the register inside SOC chip into
Row measurement.
Summary of the invention
Aiming at the problem that can not measure at present to the unit step of the register inside SOC chip, one kind is now provided
Aim at the method and system that can obtain the memory module internal delay time ladder time.
A method of the memory module internal delay time ladder time being obtained, the memory module includes storage unit and control
Unit is sampled according to communication interface of the rising edge of the clock source of described control unit to described control unit；The side
Method includes the following steps:
S1. under at least two different sampled points of the clock source, delay process is carried out to the communication interface respectively,
Obtain two boundaries of the communication interface；
S2. a delay rank is calculated according to the difference of the delayed step number between the two of the communication interface boundaries
The delay time of ladder.
Preferably, the step S1 respectively connects the communication under at least two different sampled points of the clock source
Mouth carries out delay process, obtains two boundaries of the communication interface, comprising:
S11. delay process is carried out to the communication interface in the first sampled point of the clock source；
S12. judge whether the communications status of the communication interface is normal, if so, executing step S15；If it is not, accumulative described
The number of communication interface communication abnormality executes step S13；
S13. the communication interface delayed step number is obtained, step S14 is executed；
S14. judge whether the number of the communication abnormality of the communication interface is less than or equal to 1, if executing step S15,
Step S2 is executed if not；
S15. delay process is carried out to the communication interface in the second sampled point of the clock source, executes step S12.
Preferably, it is being calculated in the S2 according to the difference of the delayed step number between the two of the communication interface boundaries
The delay time of one delayed step, comprising:
The time difference between first sampled point and second sampled point is obtained, is connect according to the time difference and the communication
The difference of delayed step number in mouthful between two boundaries of any data interface, when calculating the delay of a delayed step
Between.
Preferably, the communication interface includes data-interface and control interface.
The present invention also provides a kind of system for obtaining the memory module internal unit delayed step time, the memory modules
Including storage unit and control unit, the communication of described control unit is connect according to the rising edge of the clock source of described control unit
Mouth is sampled；Include:
Processing unit, at least two not under sampled point, being carried out respectively to the communication interface in the clock source
Delay process obtains two boundaries of the communication interface；
Computing unit, the difference for the delayed step number between two boundaries according to the communication interface calculate one
The delay time of the delayed step.
Preferably, the processing unit includes:
Postponement module carries out delay process to the communication interface for the first sampled point in the clock source；
Whether first judgment module, the communications status for judging the communication interface are normal；
Accumulation module, for adding up the number of the communication interface communication abnormality；
Module is obtained, for obtaining the communication interface delayed step when the communications status exception of the communication interface
Number；
Second judgment unit, for judging whether the number of communication abnormality of the communication interface is less than or equal to 1；
Processing module, when the communications status of the communication interface is normal or the number of the communication abnormality of the communication interface
When being less than or equal to 1, the unit that adjusts is used to prolong the communication interface in the second sampled point of the clock source
When handle.
Preferably, the computing unit is used to obtain the time difference between first sampled point and second sampled point,
According to the difference of the delayed step number between two boundaries of any data interface in the time difference and the communication interface, calculate
The delay time of one delayed step.
Preferably, the communication interface includes data-interface and control interface.
Above-mentioned technical proposal the utility model has the advantages that
In the technical program, by carrying out delay process to communication interface under the different sampled points of clock source, obtain
Two boundaries of corresponding communication interface under different sampled points are calculated further according to the different delayed time ladder number under different sampled points
The delay time of single delayed step, in order to according to the practical delay time for calculating the delayed step obtained to control unit into
Capable delay time is adjusted, and improves the stability of memory module.
Detailed description of the invention
Fig. 1 is a kind of process of embodiment of the method for the present invention for obtaining the memory module internal delay time ladder time
Figure；
Fig. 2 is the stream of another embodiment of the method for the present invention for obtaining the memory module internal delay time ladder time
Cheng Tu；
Fig. 3 is the communications status schematic diagram of present invention data-interface under different sampled points；
Fig. 4 is a kind of embodiment of the system of the present invention for obtaining the memory module internal unit delayed step time
Module map.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
As shown in Figure 1, the present invention provides a kind of method for obtaining the memory module internal delay time ladder time, the storage
Module includes storage unit and control unit, is led to according to the rising edge of the clock source of described control unit to described control unit
Letter interface is sampled；The method includes the following steps:
S1. under at least two different sampled points of the clock source, delay process is carried out to the communication interface respectively,
Obtain two boundaries of the communication interface；
It should be noted that SDIO unit can be used in storage unit；SOC chip can be used in control unit.This method can answer
For control unit to during storage unit read operation.
As shown in Fig. 2, in a preferred embodiment, at least two different sampled points of the step S1 in the clock source
Under, delay process is carried out to the communication interface respectively, obtains two boundaries of the communication interface, comprising:
S11. delay process is carried out to the communication interface in the first sampled point of the clock source；
S12. judge whether the communications status of the communication interface is normal, if so, executing step S15；If it is not, accumulative described
The number of communication interface communication abnormality executes step S13；
Wherein, communications status indicates that the communication interface is unable to normal communication extremely.
S13. the communication interface delayed step number is obtained, step S14 is executed；
S14. judge whether the number of the communication abnormality of the communication interface is less than or equal to 1, if executing step S15,
Step S2 is executed if not；
S15. delay process is carried out to the communication interface in the second sampled point of the clock source, executes step S12.
It, need to be by when carrying out interface boundary positioning it should be noted that communication interface includes data-interface and control interface
A boundary moment to each interface calculates.The register of SOC chip read signal has 63 delay (delay) settings, often
A step (delayed step) is 50 picoseconds (ps).
S2. a delay rank is calculated according to the difference of the delayed step number between the two of the communication interface boundaries
The delay time of ladder.
In the present embodiment, it by carrying out delay process to communication interface under the different sampled points of clock source, obtains
Two boundaries of corresponding communication interface under different sampled points are calculated further according to the different delayed time ladder number under different sampled points
The delay time of single delayed step, in order to according to the practical delay time for calculating the delayed step obtained to control unit into
Capable delay time is adjusted, and improves the stability of memory module.
In a preferred embodiment, a according to the delayed step between the two of the communication interface boundaries in the S2
The difference of number calculates the delay time of a delayed step, comprising:
The time difference between first sampled point and second sampled point is obtained, is connect according to the time difference and the communication
The difference of delayed step number in mouthful between two boundaries of any data interface, when calculating the delay of a delayed step
Between.
In the present embodiment, it is contemplated that communication interface may include data-interface and control interface, carry out delayed step
Delay time calculate when, can according to any interface in different sampled points corresponding boundary, calculated.
For example and without limitation, with storage unit use SDIO unit, control unit use SOC chip for acquisition
The method of memory module internal delay time ladder time is illustrated:
As shown in figure 3, in the first sampled point, the boundary value of read signal cmd (the control interface) (grey rectangle in figure that is 9
Indicate interface normal communication, white rectangle indicates interface exceptional communication)；In the second sampled point, read signal cmd (control interface)
Boundary value be d；The time difference among first sampled point and the second sampled point differs 1 nanosecond (ns), two boundaries of read signal cmd
Differ 4 ladders, then the internal delay time of single delayed step is about 1/4=0.25ns, i.e., single delayed step be 0.25ns with
Each step that SOC chip specification provides is that 50ps is not consistent, and uses single delayed step 0.25ns for more accurate value.
It should be noted that the method for obtaining the memory module internal delay time ladder time applies also for eMMC
In the communication interface adjustment of (Embedded Multi Media Card) card or TF (Trans-flash Card) card, in order to
Meet cabling requirement when design, improves the stability of system.
As shown in figure 4, the present invention also provides a kind of system for obtaining the memory module internal unit delayed step time, institute
Stating memory module includes storage unit and control unit, according to the rising edge of the clock source of described control unit to the control list
The communication interface of member is sampled；The system for obtaining the memory module internal unit delayed step time can include: 1 He of processing unit
Computing unit 2；Wherein:
Processing unit 1, at least two not under sampled point, being carried out respectively to the communication interface in the clock source
Delay process obtains two boundaries of the communication interface；
Computing unit 2, the difference for the delayed step number between two boundaries according to the communication interface calculate one
The delay time of a delayed step.
It should be noted that SDIO unit can be used in storage unit；SOC chip can be used in control unit.This method can answer
For control unit to during storage unit read operation.
In the present embodiment, it by carrying out delay process to communication interface under the different sampled points of clock source, obtains
Two boundaries of corresponding communication interface under different sampled points are calculated further according to the different delayed time ladder number under different sampled points
The delay time of single delayed step, in order to according to the practical delay time for calculating the delayed step obtained to control unit into
Capable delay time is adjusted, and improves the stability of memory module.
In a preferred embodiment, the processing unit 1 can include:
Postponement module carries out delay process to the communication interface for the first sampled point in the clock source；
Whether first judgment module, the communications status for judging the communication interface are normal；
Accumulation module, for adding up the number of the communication interface communication abnormality；
Module is obtained, for obtaining the communication interface delayed step when the communications status exception of the communication interface
Number；
Second judgment unit, for judging whether the number of communication abnormality of the communication interface is less than or equal to 1；
Processing module, when the communications status of the communication interface is normal or the number of the communication abnormality of the communication interface
When being less than or equal to 1, the unit that adjusts is used to prolong the communication interface in the second sampled point of the clock source
When handle.
In a preferred embodiment, the computing unit 2 is for obtaining first sampled point and second sampled point
Between the time difference, according to the delayed step between two boundaries of any data interface in the time difference and the communication interface
The difference of number calculates the delay time of a delayed step.
In a preferred embodiment, the communication interface includes data-interface and control interface.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (8)
1. a kind of method for obtaining the memory module internal delay time ladder time, the memory module includes that storage unit and control are single
Member is sampled according to communication interface of the rising edge of the clock source of described control unit to described control unit；Its feature exists
In the method includes the following steps:
S1. under at least two different sampled points of the clock source, delay process is carried out to the communication interface respectively, is obtained
Two boundaries of the communication interface；
S2. the delayed step is calculated according to the difference of the delayed step number between the two of the communication interface boundaries
Delay time.
2. the method according to claim 1 for obtaining the memory module internal delay time ladder time, which is characterized in that the step
Rapid S1 carries out delay process to the communication interface respectively, obtains institute under at least two different sampled points of the clock source
State two boundaries of communication interface, comprising:
S11. delay process is carried out to the communication interface in the first sampled point of the clock source；
S12. judge whether the communications status of the communication interface is normal, if so, executing step S15；If it is not, adding up the communication
The number of interface communication exception executes step S13；
S13. the communication interface delayed step number is obtained, step S14 is executed；
S14. judge whether the number of the communication abnormality of the communication interface is less than or equal to 1, if executing step S15, if not
Execute step S2；
S15. delay process is carried out to the communication interface in the second sampled point of the clock source, executes step S12.
3. the method according to claim 2 for obtaining the memory module internal delay time ladder time, which is characterized in that described
Prolonging for the delayed step is calculated according to the difference of the delayed step number between the two of the communication interface boundaries in S2
When the time, comprising:
The time difference between first sampled point and second sampled point is obtained, according in the time difference and the communication interface
The difference of delayed step number between two boundaries of any data interface calculates the delay time of a delayed step.
4. the method according to claim 1 for obtaining the memory module internal delay time ladder time, which is characterized in that described logical
Believe that interface includes data-interface and control interface.
5. a kind of system for obtaining the memory module internal unit delayed step time, the memory module includes storage unit and control
Unit processed is sampled according to communication interface of the rising edge of the clock source of described control unit to described control unit；It is special
Sign is, comprising:
Processing unit, at least two not under sampled point, being delayed respectively to the communication interface in the clock source
Processing, obtains two boundaries of the communication interface；
Computing unit, the difference for the delayed step number between two boundaries according to the communication interface calculate described in one
The delay time of delayed step.
6. the system according to claim 5 for obtaining the memory module internal unit delayed step time, which is characterized in that institute
Stating processing unit includes:
Postponement module carries out delay process to the communication interface for the first sampled point in the clock source；
Whether first judgment module, the communications status for judging the communication interface are normal；
Accumulation module, for adding up the number of the communication interface communication abnormality；
Module is obtained, for obtaining the communication interface delayed step number when the communications status exception of the communication interface；
Second judgment unit, for judging whether the number of communication abnormality of the communication interface is less than or equal to 1；
Processing module, when the communications status of the communication interface is normal or the number of the communication abnormality of the communication interface is small
When 1, the unit that adjusts is used to carry out at delay the communication interface in the second sampled point of the clock source
Reason.
7. the system according to claim 6 for obtaining the memory module internal unit delayed step time, which is characterized in that institute
Computing unit is stated for obtaining time difference between first sampled point and second sampled point, according to time difference and described
The difference of delayed step number in communication interface between two boundaries of any data interface calculates the delayed step
Delay time.
8. the system according to claim 5 for obtaining the memory module internal unit delayed step time, which is characterized in that institute
Stating communication interface includes data-interface and control interface.
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| CN102915761A (en) * | 2012-10-31 | 2013-02-06 | 苏州大学 | Delay control circuit applied to memory unit and static random access memory |
| CN104134454A (en) * | 2007-12-21 | 2014-11-05 | 拉姆伯斯公司 | Method and apparatus for calibrating write timing in a memory system |
| CN105701042A (en) * | 2016-03-02 | 2016-06-22 | 珠海全志科技股份有限公司 | Optimizing method and system for signal quality of memory control interface |
| JP2018142366A (en) * | 2018-05-17 | 2018-09-13 | ラピスセミコンダクタ株式会社 | Semiconductor device, data communication system, and data writing control method |
| CN109167705A (en) * | 2018-09-06 | 2019-01-08 | 晶晨半导体(上海)股份有限公司 | Obtain the method and system of memory module internal delay time ladder time |
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- 2018-10-17 CN CN201811210591.XA patent/CN109359067B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104134454A (en) * | 2007-12-21 | 2014-11-05 | 拉姆伯斯公司 | Method and apparatus for calibrating write timing in a memory system |
| CN102915761A (en) * | 2012-10-31 | 2013-02-06 | 苏州大学 | Delay control circuit applied to memory unit and static random access memory |
| CN105701042A (en) * | 2016-03-02 | 2016-06-22 | 珠海全志科技股份有限公司 | Optimizing method and system for signal quality of memory control interface |
| JP2018142366A (en) * | 2018-05-17 | 2018-09-13 | ラピスセミコンダクタ株式会社 | Semiconductor device, data communication system, and data writing control method |
| CN109167705A (en) * | 2018-09-06 | 2019-01-08 | 晶晨半导体(上海)股份有限公司 | Obtain the method and system of memory module internal delay time ladder time |
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