CN114513293B - Pulse-per-second delay compensation system and method - Google Patents
Pulse-per-second delay compensation system and method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0075—Arrangements for synchronising receiver with transmitter with photonic or optical means
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a second pulse delay compensation system and a method, which relate to the technical field of clock synchronization and comprise the following steps: the device comprises a processor, a voltage-controlled oscillator, a waveform shaper, a logic switch and a pulse trigger circuit. The invention provides a circuit scheme and an implementation method of a pulse per second delay compensation system, which solve the problem that the leading edge deviation of a time reference pulse per second signal of the existing time synchronization system occurs due to transmission delay. A constant temperature voltage controlled crystal oscillator is adopted to provide a reference frequency, and the frequency does not drift along with the temperature change; and a reference frequency calibration and adjustment method is designed, so that the stability of the reference frequency of the processor is guaranteed, and a foundation is laid for accurately shifting the second pulse and realizing accurate delay compensation of the second pulse. When the second pulse delay compensation value is too large, a sliding mode of gradual compensation is designed to be close to and reach the second pulse compensation value, and burst jitter of the second pulse is prevented.
Description
Technical Field
The invention relates to the technical field of clock synchronization, in particular to a pulse-per-second delay compensation system and a pulse-per-second delay compensation method.
Background
At present, a time synchronization system used in a hydraulic power plant and a substation generally consists of a master clock and an extended clock, and generally adopts an optical fiber to transmit a time signal.
For the application scenes of hydropower stations and transformer substations, the installation positions of the main clock and the extended clock are far away, even reach 10 kilometers. In this case, the time reference pulse-per-second signal sent by the main clock must generate a non-negligible delay after being transmitted through the optical fiber, so that when the time reference pulse-per-second signal is received by the spread clock, the leading edge of the signal has already shifted. To achieve high-precision time synchronization, the leading edge of the pulse-per-second signal received by the spread clock needs to be consistent with the leading edge of the main clock.
Disclosure of Invention
Aiming at the defects in the prior art, the pulse per second delay compensation system and method provided by the invention solve the problem that the leading edge deviation of the time reference pulse per second signal of the existing time synchronization system occurs due to transmission delay.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
in a first aspect, a pulse-per-second delay compensation system includes: the device comprises a processor, a voltage-controlled oscillator, a waveform shaper, a logic switch and a pulse trigger circuit;
the processor is an integrated processor internally provided with a pulse capture unit, a storage medium, a timer, a PWM output unit and a digital-to-analog conversion unit, a first GPIO general input/output interface is used as a second pulse signal input end of a second pulse delay compensation system, a reference frequency interface of the processor is connected with the output end of a waveform shaper, a second GPIO general input/output interface of the processor is connected with a first input end of a logic switch, a third GPIO general input/output interface of the processor is connected with a second input end of the logic switch, and a digital-to-analog conversion interface of the processor is connected with a voltage control end of a voltage-controlled oscillator; the output end of the logic switch is connected with the input end of the pulse trigger circuit; the output end of the pulse trigger circuit is used as a pulse per second signal output end of a pulse per second delay compensation system; and the output end of the voltage-controlled oscillator is connected with the input end of the waveform shaper.
Further, the voltage-controlled oscillator is a constant-temperature voltage-controlled crystal oscillator; the waveform shaper is a Schmitt trigger; the logic switch is a NAND gate.
Further, the pulse trigger circuit includes: the circuit comprises a resistor R1, a capacitor C1 and a monostable trigger U1;
the type of the monostable trigger U1 is 74HC123, a power supply terminal VCC of the monostable trigger U is connected with one end of the resistor R1 and serves as a power supply terminal VCC of the pulse trigger circuit, a REXT end of the monostable trigger U is respectively connected with the other end of the resistor R1 and one end of the capacitor C1, a CEXT end of the monostable trigger U is grounded, an A end of the monostable trigger U is grounded, a common end GND of the monostable trigger U is grounded, a B end of the monostable trigger U serves as an input end of the pulse trigger circuit, and a Q end of the monostable trigger U serves as an output end of the pulse trigger circuit.
The system further comprises an upper computer, and the upper computer is connected with a serial communication interface of the processor through a serial bus.
In a second aspect, a pulse per second delay compensation method using the above pulse per second delay compensation system includes the following steps:
s1, setting an array for storing the leading edge time of the second pulse in a storage medium of a processor;
s2, configuring a pulse capture unit, a timer and a storage medium of the processor, enabling the pulse capture unit to continuously capture the signal leading edge of each pulse per second, capturing the value of the timer when the pulse capture unit captures the leading edge of the pulse per second signal, and storing the value into an array in a queue storage mode;
s3, calibrating the reference frequency of the processor according to the data queue dynamically stored in the array;
s4, acquiring a pulse per second time deviation value;
and S5, outputting the second pulse after delay compensation through the processor according to the second pulse time deviation value.
Further, the step S4 includes the following sub-steps:
s41, acquiring the refractive index of the optical fiber and the transmission distance of the pulse per second in the optical fiber;
s42, calculating the time deviation value of the pulse per second according to the refractive index of the optical fiber and the transmission distance of the pulse per second in the optical fiber by the following formula:
wherein, t delay And c is the deviation value of the second pulse time, c is the speed of light, gamma is the refractive index of the optical fiber, and L is the transmission distance of the second pulse in the optical fiber.
Further, the step S5 includes the following sub-steps:
s51, judging whether the pulse per second time deviation value is larger than a deviation threshold value, if so, jumping to a step S53, and if not, jumping to a step S52;
s52, configuring a PWM output unit and a timer of the processor by taking the second pulse time deviation value as a delay compensation value, and enabling the processor to output the second pulse after delay compensation;
and S53, taking the value of delta t increased every second as a delay compensation value, and configuring a PWM (pulse-width modulation) output unit and a timer of the processor to enable the processor to output the delayed and compensated second pulse until the phase shift of the delayed and compensated second pulse reaches the second pulse time deviation value.
In a third aspect, a method for calibrating and adjusting a reference frequency is applied to the above-mentioned pulse-per-second delay compensation system and the above-mentioned pulse-per-second delay compensation method, and includes the following steps:
a1, traversing a data queue in a storage medium array of a processor, and solving the average value of queue data except for the maximum value and the minimum value;
a2, waiting for the update of the data queue, traversing the data queue in the storage medium array of the processor again after the update, and solving the average value of the queue data except the maximum value and the minimum value;
a3, comparing whether the average values of the step A1 and the step A2 are equal, if so, ending, otherwise, skipping to the step A4;
and A4, controlling the voltage-controlled terminal voltage of the voltage-controlled oscillator through a digital-to-analog conversion unit arranged in the processor according to the difference value of the mean values in the step A1 and the step A2 so as to adjust the reference frequency output by the voltage-controlled oscillator.
The beneficial effects of the invention are as follows:
1) The circuit scheme and the implementation method of the system for compensating the pulse per second delay are provided, and the problem that the leading edge deviation of a time reference pulse per second signal of the existing time synchronization system occurs due to transmission delay is solved.
2) A constant temperature voltage controlled crystal oscillator is adopted to provide a reference frequency, and the frequency does not drift along with the temperature change; and a reference frequency calibration and adjustment method is designed, the stability of the reference frequency of the processor is guaranteed, and a foundation is laid for accurately shifting the second pulse and realizing accurate delay compensation of the second pulse.
3) When the second pulse delay compensation value is too large, a sliding mode of gradual change compensation is used to approach and reach the second pulse compensation value, and burst jitter of the second pulse is prevented.
4) Through the design of the logic switch, the error output of error time is prevented, and the accuracy of the second pulse reconstruction type delay compensation output of the processor is guaranteed.
5) Through the design of the pulse trigger circuit, the pulse width of the second pulse of the delay compensation reconstructed by the processor can be matched.
Drawings
FIG. 1 is a circuit diagram of a pulse-per-second delay compensation system according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a pulse trigger circuit according to an embodiment of the present invention;
FIG. 3 is a flowchart of a pulse-per-second delay compensation method according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for calibrating and adjusting a reference frequency according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined by the appended claims, and all changes that can be made by the invention using the inventive concept are intended to be protected.
In one embodiment of the present invention, as shown in fig. 1, a pulse-per-second delay compensation system comprises: the device comprises a processor, a voltage-controlled oscillator, a waveform shaper, a logic switch and a pulse trigger circuit.
The processor is an integrated processor with a built-in pulse capture unit, a storage medium, a timer, a PWM output unit and a digital-to-analog conversion unit.
In this embodiment, the processor is an STM32 single chip microcomputer, a first GPIO general input/output interface of the processor is used as a pulse-per-second signal input end of the pulse-per-second delay compensation system, a reference frequency interface of the processor is connected to an output end of the waveform shaper, a second GPIO general input/output interface of the processor is connected to a first input end of the logic switch, a third GPIO general input/output interface of the processor is connected to a second input end of the logic switch, and a digital-to-analog conversion interface of the processor is connected to a voltage control end of the voltage-controlled oscillator. The output end of the logic switch is connected with the input end of the pulse trigger circuit. The output end of the pulse trigger circuit is used as a pulse per second signal output end of the pulse per second delay compensation system. The output end of the voltage-controlled oscillator is connected with the input end of the waveform shaper.
The voltage-controlled oscillator for providing reference frequency for the processor is connected with a digital-to-analog conversion interface of the processor, so that the voltage-controlled voltage of the voltage-controlled oscillator can be conveniently adjusted, and the frequency is stabilized.
In this embodiment, the voltage-controlled oscillator is an oven controlled crystal oscillator, model number JTM1158B, and operating frequency is 20MHz; the waveform shaper is a Schmitt trigger, and the type number of the Schmitt trigger is 74HC14; the logic switch is a nand gate with the model number 74HC00. The waveform output by the JTM1158B type constant-temperature voltage-controlled crystal oscillator is a sine wave, the sine wave is shaped into a square wave by adopting a 74HC14 chip, and the 74HC14 has a hysteresis effect, so that the stability of the circuit is ensured.
Based on the connection relationship and the device model, in this embodiment, the first GPIO general-purpose input-output interface of the processor is configured in an input mode to obtain a time-reference pulse-per-second signal; the second GPIO general input/output interface is configured to be in an output mode and outputs the pulse per second after delay compensation is carried out on the second GPIO general input/output interface by the processor; the third GPIO general input/output interface is configured to be in an output mode, outputs low level and enables the logic switch to be equivalently turned off; and outputting high level to make the logic switch equal to be opened. In application, the third GPIO general input/output interface controls the logic switch to release pulses within 1ms before and after the leading edge position of the pulse per second, and other pulses are turned off, so that abnormal output of the processor is prevented, and the correctness of output pulses is guaranteed.
As shown in fig. 2, the pulse trigger circuit includes: a resistor R1, a capacitor C1 and a monostable trigger U1.
The monostable trigger U1 is 74HC123, a power supply terminal VCC thereof is connected to one end of the resistor R1 and serves as a power supply terminal VCC of the pulse trigger circuit, a REXT terminal thereof is connected to the other end of the resistor R1 and one end of the capacitor C1, a CEXT terminal thereof is grounded, an a terminal thereof is grounded, a common terminal GND thereof is grounded, a B terminal thereof serves as an input terminal of the pulse trigger circuit, and a Q terminal thereof serves as an output terminal of the pulse trigger circuit.
The pulse trigger circuit is essentially a monostable trigger circuit, and after the second pulse at the input end arrives, the 74HC123 chip can stretch the second pulse by the values of the resistor R1 and the capacitor C1.
The pulse per second delay compensation system of the embodiment further comprises an upper computer, and the upper computer is connected with the serial communication interface of the processor through a serial bus.
In this embodiment, the STM32 type processor performs 3-fold frequency using an internal phase-locked loop technique, and thus, the actual operating frequency of the STM32 is 60MHz.
Fig. 3 shows a pulse-per-second delay compensation method according to this embodiment, which employs the pulse-per-second delay compensation system, and includes the following steps:
s1, setting an array for storing the leading edge time of the second pulse in a storage medium of a processor.
S2, configuring a pulse capture unit, a timer and a storage medium of the processor, enabling the pulse capture unit to continuously capture the signal leading edge of each pulse per second, capturing the value of the timer when the pulse capture unit captures the leading edge of the pulse per second signal, and storing the value into an array in a queue storage mode.
And S3, calibrating the reference frequency of the processor according to the data queue dynamically stored in the array.
And S4, acquiring a pulse per second time deviation value.
The method for acquiring the time offset value of the pulse per second in this embodiment has various ways:
first, the processor gets directly from the serial bus. In the application scenario of the invention, a satellite clock is usually connected to the serial bus, and the time data packet provided by the serial bus contains control information, such as a compensation value required for pulse per second delay.
And secondly, the data is acquired by the upper computer through man-machine interaction with workers.
Thirdly, the upper computer or the processor is obtained through the following method steps:
s41, acquiring the refractive index of the optical fiber and the transmission distance of the second pulse in the optical fiber;
s42, calculating the time deviation value of the second pulse according to the refractive index of the optical fiber and the transmission distance of the second pulse in the optical fiber by the following formula:
wherein, t delay Is time deviation of pulse per secondThe values c are the speed of light, γ is the refractive index of the fiber, and L is the transmission distance of the second pulse in the fiber.
The refractive index of the optical fiber in this example was 1.46, the transmission distance of the pulse per second in the optical fiber was 20 km, and the deviation value of the pulse per second time was calculated to be 96 μ s.
And S5, outputting the delayed compensated second pulse through the processor according to the second pulse time deviation value.
Step S5 includes the following substeps:
s51, judging whether the pulse per second time deviation value is larger than a deviation threshold value, if so, jumping to a step S53, and if not, jumping to a step S52;
s52, configuring a PWM output unit and a timer of the processor by taking the second pulse time deviation value as a delay compensation value, and enabling the processor to output the second pulse after delay compensation;
and S53, taking the value of delta t increased every second as a delay compensation value, and configuring a PWM (pulse-width modulation) output unit and a timer of the processor to enable the processor to output the delayed and compensated second pulse until the phase shift of the delayed and compensated second pulse reaches the second pulse time deviation value.
In this embodiment, Δ t is 50 nanoseconds.
As shown in fig. 4, a method for calibrating and adjusting a reference frequency according to this embodiment is applied to the above-mentioned pulse-per-second delay compensation system and the above-mentioned pulse-per-second delay compensation method, specifically, in step S3 of the pulse-per-second delay compensation method, the method includes the following steps:
a1, traversing data queues in a storage medium array of a processor, and averaging queue data except for the maximum value and the minimum value.
And A2, waiting for the update of the data queue, traversing the data queue in the storage medium array of the processor again after the update, and calculating the average value of the queue data except the maximum value and the minimum value.
And A3, comparing whether the average values in the step A1 and the step A2 are equal, if so, ending, otherwise, skipping to the step A4.
And A4, controlling the voltage-controlled terminal voltage of the voltage-controlled oscillator through a digital-to-analog conversion unit arranged in the processor according to the difference value of the mean values in the step A1 and the step A2 so as to adjust the reference frequency output by the voltage-controlled oscillator. In the embodiment, the voltage output value of the digital-to-analog conversion unit built in the processor is calculated by the PID algorithm according to the difference value of the mean values of the step A1 and the step A2.
The timer of the STM32 is 16 bits, the maximum count value is 65535, the period of the timer is set to be 2ms, the 1 second is 499 periods of the complete timer plus 2 half periods, and the clock synchronization second pulse signal sent by the main clock of the application scene of the invention has integral delay but high precision. Theoretically, the pulse-per-second interval does not shift, and if the pulse-per-second time measured by the processor is not consistent, it can be regarded that the reference frequency of the processor shifts. The accurate reference frequency is the basis for accurately realizing the delay compensation, so the invention designs the reference frequency calibration and adjustment method. And if the deviation occurs, the STM32 outputs voltage through a built-in digital-to-analog conversion unit and a digital-to-analog conversion interface, controls a voltage control end of the constant-temperature crystal oscillator, and adjusts the frequency of the constant-temperature crystal oscillator to ensure that the crystal oscillator stably works at 20M.
In summary, the invention 1) provides a circuit scheme and an implementation method of a system for compensating the pulse per second delay, and solves the problem that the leading edge deviation of a time reference pulse per second signal of the existing time synchronization system occurs due to transmission delay. 2) A constant temperature voltage controlled crystal oscillator is adopted to provide a reference frequency, and the frequency does not drift along with the temperature change; and a reference frequency calibration and adjustment method is designed, the stability of the reference frequency of the processor is guaranteed, and a foundation is laid for accurately shifting the second pulse and realizing accurate delay compensation of the second pulse. 3) When the second pulse delay compensation value is too large, a sliding mode of gradual change compensation is used to approach and reach the second pulse compensation value, and burst jitter of the second pulse is prevented. 4) Through the design of the logic switch, the error output of error time is prevented, and the accuracy of the second pulse reconstruction type delay compensation output of the processor is guaranteed. 5) Through the design of the pulse trigger circuit, the pulse width of the second pulse of the delay compensation reconstructed by the processor can be matched.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (8)
1. A pulse-per-second delay compensation system, comprising: the device comprises a processor, a voltage-controlled oscillator, a waveform shaper, a logic switch and a pulse trigger circuit;
the processor is an integrated processor internally provided with a pulse capture unit, a storage medium, a timer, a PWM output unit and a digital-to-analog conversion unit, a first GPIO general input/output interface is used as a second pulse signal input end of a second pulse delay compensation system, a reference frequency interface of the processor is connected with the output end of a waveform shaper, a second GPIO general input/output interface of the processor is connected with a first input end of a logic switch, a third GPIO general input/output interface of the processor is connected with a second input end of the logic switch, and a digital-to-analog conversion interface of the processor is connected with a voltage control end of a voltage-controlled oscillator; the output end of the logic switch is connected with the input end of the pulse trigger circuit; the output end of the pulse trigger circuit is used as a pulse per second signal output end of a pulse per second delay compensation system; the output end of the voltage-controlled oscillator is connected with the input end of the waveform shaper;
the system is provided with a pulse capture unit, a timer and a storage medium of the processor, so that the pulse capture unit continuously captures the signal leading edge of each pulse per second, and simultaneously captures the value of the timer when the pulse capture unit captures the leading edge of the pulse per second signal, and stores the value into an array in a queue storage mode; traversing a data queue in the storage medium array of the processor, and solving the average value of queue data except the maximum value and the minimum value; waiting for the updating of the data queue, traversing the data queue in the storage medium array of the processor again after the updating, and solving the average value of the queue data except the maximum value and the minimum value; and controlling the voltage-controlled end voltage of the voltage-controlled oscillator through a digital-to-analog conversion unit arranged in the processor according to the difference value of the two average values so as to adjust the reference frequency output by the voltage-controlled oscillator.
2. The pulse-per-second delay compensation system of claim 1, wherein the voltage controlled oscillator is an oven controlled crystal oscillator; the waveform shaper is a Schmitt trigger; the logic switch is a NAND gate.
3. The pulse-per-second delay compensation system of claim 1, wherein the pulse trigger circuit comprises: the circuit comprises a resistor R1, a capacitor C1 and a monostable trigger U1;
the type of the monostable trigger U1 is 74HC123, a power supply terminal VCC of the monostable trigger U is connected with one end of the resistor R1 and serves as a power supply terminal VCC of the pulse trigger circuit, a REXT end of the monostable trigger U is respectively connected with the other end of the resistor R1 and one end of the capacitor C1, a CEXT end of the monostable trigger U is grounded, an A end of the monostable trigger U is grounded, a common end GND of the monostable trigger U is grounded, a B end of the monostable trigger U serves as an input end of the pulse trigger circuit, and a Q end of the monostable trigger U serves as an output end of the pulse trigger circuit.
4. The pulse-per-second delay compensation system according to claim 1, further comprising an upper computer connected to a serial communication interface of the processor through a serial bus.
5. A pulse-per-second delay compensation method using the pulse-per-second delay compensation system according to any one of claims 1 to 4, comprising the steps of:
s1, setting an array for storing the leading edge time of the second pulse in a storage medium of a processor;
s2, configuring a pulse capture unit, a timer and a storage medium of the processor, enabling the pulse capture unit to continuously capture the signal leading edge of each pulse per second, capturing the value of the timer when the pulse capture unit captures the leading edge of the pulse per second signal, and storing the value into an array in a queue storage mode;
s3, calibrating the reference frequency of the processor according to the data queue dynamically stored in the array;
s4, acquiring a pulse per second time deviation value;
and S5, outputting the delayed compensated second pulse through the processor according to the second pulse time deviation value.
6. The pulse-per-second delay compensation method according to claim 5, wherein the step S4 comprises the following substeps:
s41, acquiring the refractive index of the optical fiber and the transmission distance of the second pulse in the optical fiber;
s42, calculating the time deviation value of the pulse per second according to the refractive index of the optical fiber and the transmission distance of the pulse per second in the optical fiber by the following formula:
wherein, t delay And the time deviation value of the second pulse, c is the light speed, gamma is the refractive index of the optical fiber, and L is the transmission distance of the second pulse in the optical fiber.
7. The pulse-per-second delay compensation method according to claim 5, wherein the step S5 comprises the following substeps:
s51, judging whether the second pulse time deviation value is larger than a deviation threshold value, if so, jumping to a step S53, and if not, jumping to a step S52;
s52, configuring a PWM output unit and a timer of the processor by taking the second pulse time deviation value as a delay compensation value, and enabling the processor to output the second pulse after delay compensation;
and S53, taking the value of delta t increased every second as a delay compensation value, configuring a PWM output unit and a timer of the processor, and enabling the processor to output the second pulse after delay compensation until the phase shift of the second pulse after delay compensation reaches the second pulse time deviation value.
8. A method for calibrating and adjusting a reference frequency, applied to the pulse-per-second delay compensation system according to any one of claims 1 to 4 and the pulse-per-second delay compensation method according to any one of claims 5 to 7, comprising the steps of:
a1, traversing a data queue in a storage medium array of a processor, and solving the average value of queue data except for the maximum value and the minimum value;
a2, waiting for the update of the data queue, traversing the data queue in the storage medium array of the processor again after the update, and solving the average value of the queue data except the maximum value and the minimum value;
a3, comparing whether the average values of the step A1 and the step A2 are equal, if so, ending, otherwise, skipping to the step A4;
and A4, controlling the voltage-controlled terminal voltage of the voltage-controlled oscillator through a digital-to-analog conversion unit arranged in the processor according to the difference value of the mean values in the step A1 and the step A2 so as to adjust the reference frequency output by the voltage-controlled oscillator.
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|---|---|---|---|---|
| US4503400A (en) * | 1983-06-23 | 1985-03-05 | Gte Automatic Electric Inc. | Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit |
| CN85103998A (en) * | 1985-05-23 | 1986-12-31 | D·A·V·I·D·系统公司 | High-speed digital loop transceiver |
| CN111416617A (en) * | 2020-03-18 | 2020-07-14 | 广州土圭垚信息科技有限公司 | Clock synchronization method and device and electronic equipment |
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| CN114513293A (en) | 2022-05-17 |
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