CN109167705A - Obtain the method and system of memory module internal delay time ladder time - Google Patents
Obtain the method and system of memory module internal delay time ladder time Download PDFInfo
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- CN109167705A CN109167705A CN201811036678.XA CN201811036678A CN109167705A CN 109167705 A CN109167705 A CN 109167705A CN 201811036678 A CN201811036678 A CN 201811036678A CN 109167705 A CN109167705 A CN 109167705A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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Abstract
The invention discloses the method and system for obtaining the memory module internal delay time ladder time, belong to field of communication technology.The method for obtaining the memory module internal delay time ladder time is to carry out delay process under the sampling clock of at least two outs of phase to the communication interface respectively, obtain two boundaries of the communication interface；The delay time of a delayed step is calculated according to the difference of the delayed step number between the two of the communication interface boundaries.The present invention by adjusting the sampling clock of the communication interface of control unit phase, and delay process is carried out to communication interface, obtain two boundaries of the corresponding communication interface under different sampling clock phases, the delay time of single delayed step is calculated further according to the different delayed time ladder number under different sampling clock phases, in order to which the delay time carried out according to the practical delay time for calculating the delayed step obtained to control unit is adjusted, the stability of memory module is improved.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of methods for obtaining the memory module internal delay time ladder time
And system.
Background technique
Make in SDIO (Secure Digital Input and Output Card, secure digital input-output card) interface
In, with the increase of frequency, the problem of SDIO stability, is also slowly exposed.In practical application, such as: SDIO unit to
When SOC chip read signal, although the specification according to SOC chip (System-on-a-Chip) can obtain the unit of its internal delay time
The duration of ladder, but not necessarily accurately, if the duration of unit step is wrong, mistake can be generated in register setting
It leads, and then influences stability of system during read signal.However it at present can not be to the unit of the register inside SOC chip
Ladder measures.
Summary of the invention
Aiming at the problem that can not measure at present to the unit step of the register inside SOC chip, one kind is now provided
Aim at the method and system that can obtain the memory module internal delay time ladder time.
The present invention provides a kind of method for obtaining the memory module internal delay time ladder time, the memory module includes depositing
Storage unit and control unit, according to the rising edge of the sampling clock of described control unit to the communication interface of described control unit into
Row sampling；The method includes the following steps:
S1. under the sampling clock of at least two outs of phase, delay process is carried out to the communication interface respectively, is obtained
Two boundaries of the communication interface；
S2. a delay rank is calculated according to the difference of the delayed step number between the two of the communication interface boundaries
The delay time of ladder.
Preferably, the step S1 is under the sampling clock of at least two outs of phase, respectively to the communication interface into
Line delay processing, obtains two boundaries of the communication interface, comprising:
S11. when the sampling clock is default phase, delay process is carried out to the communication interface；
S12. judge whether the communications status of the communication interface is normal, if so, executing step S15；If it is not, accumulative described
The number of communication interface communication abnormality executes step S13；
S13. the communication interface delayed step number is obtained, step S14 is executed；
S14. judge whether the number of the communication abnormality of the communication interface is less than or equal to 1, if executing step S15,
Step S2 is executed if not；
S15. the phase for adjusting the sampling clock carries out delay process to the communication interface, executes step S12.
Preferably, the phase that the sampling clock is adjusted in the step S15, carries out at delay the communication interface
Reason, comprising:
The phase shift adjustment that 90 degree are carried out to the current phase of the sampling clock, carries out at delay the communication interface
Reason.
Preferably, it is being calculated in the S2 according to the difference of the delayed step number between the two of the communication interface boundaries
The delay time of one delayed step, comprising:
According to the difference of the delayed step number between two boundaries of any data interface in the communication interface, and obtain
The delay time of two phase difference calculatings, one delayed step of corresponding sampling clock when taking described two boundaries.
The present invention also provides a kind of system for obtaining the memory module internal unit delayed step time, the memory modules
Communication including storage unit and control unit, according to the rising edge of the sampling clock of described control unit to described control unit
Interface is sampled；Include:
Processing unit, for prolonging respectively to the communication interface under the sampling clock of at least two outs of phase
When handle, obtain two boundaries of the communication interface；
Computing unit, the difference for the delayed step number between two boundaries according to the communication interface calculate one
The delay time of the delayed step.
Preferably, the processing unit includes:
Postponement module, for carrying out delay process to the communication interface when the sampling clock is default phase；
Whether first judgment module, the communications status for judging the communication interface are normal；
Accumulation module, for adding up the number of the communication interface communication abnormality；
Module is obtained, for obtaining the communication interface delayed step when the communications status exception of the communication interface
Number；
Second judgment unit, for judging whether the number of communication abnormality of the communication interface is less than or equal to 1；
Adjustment module, when the communications status of the communication interface is normal or the number of the communication abnormality of the communication interface
When being less than or equal to 1, the phase for adjusting unit and being used to adjust the sampling clock is delayed to the communication interface
Processing.
Preferably, the adjustment module is used to adjust the phase shift that the current phase of the sampling clock carries out 90 degree, right
The communication interface carries out delay process.
Preferably, the computing unit is between two boundaries according to any data interface in the communication interface
The difference of delayed step number, and two phase difference calculatings one of the corresponding sampling clock when obtaining described two boundaries
The delay time of the delayed step.
Above-mentioned technical proposal the utility model has the advantages that
In the technical program, by adjusting the phase of the sampling clock of the communication interface of control unit, and communication is connect
Mouth carries out delay process, obtains two boundaries of the corresponding communication interface under different sampling clock phases, adopts further according to difference
Different delayed time ladder number under sample clock phase calculates the delay time of single delayed step, in order to be obtained according to practical calculating
The delay time that the delay time of the delayed step taken carries out control unit is adjusted, and improves the stability of memory module.
Detailed description of the invention
Fig. 1 is a kind of process of embodiment of the method for the present invention for obtaining the memory module internal delay time ladder time
Figure；
Fig. 2 is the stream of another embodiment of the method for the present invention for obtaining the memory module internal delay time ladder time
Cheng Tu；
Fig. 3 is the communications status schematic diagram of the sampling clock of the invention data-interface in out of phase；
Fig. 4 is a kind of embodiment of the system of the present invention for obtaining the memory module internal unit delayed step time
Module map.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
As shown in Figure 1, the present invention provides a kind of method for obtaining the memory module internal delay time ladder time, the storage
Module includes storage unit and control unit, according to the rising edge of the sampling clock of described control unit to described control unit
Communication interface is sampled；The method includes the following steps:
S1. under the sampling clock of at least two outs of phase, delay process is carried out to the communication interface respectively, is obtained
Two boundaries of the communication interface；
It should be noted that SDIO unit can be used in storage unit；SOC chip can be used in control unit.This method can answer
For storage unit to during control unit read operation.
As shown in Fig. 2, in a preferred embodiment, the step S1 under the sampling clock of at least two outs of phase,
Delay process is carried out to the communication interface respectively, obtains two boundaries of the communication interface, comprising:
S11. when the sampling clock is default phase, delay process is carried out to the communication interface；
S12. judge whether the communications status of the communication interface is normal, if so, executing step S15；If it is not, accumulative described
The number of communication interface communication abnormality executes step S13；
Wherein, communications status indicates that the communication interface is unable to normal communication extremely.
S13. the communication interface delayed step number is obtained, step S14 is executed；
S14. judge whether the number of the communication abnormality of the communication interface is less than or equal to 1, if executing step S15,
Step S2 is executed if not；
S15. the phase for adjusting the sampling clock carries out delay process to the communication interface, executes step S12.
Further, the phase that the sampling clock is adjusted in the step S15, is delayed to the communication interface
Processing, comprising:
The phase shift adjustment that 90 degree are carried out to the current phase of the sampling clock, carries out at delay the communication interface
Reason.
It, need to be by when carrying out interface boundary positioning it should be noted that communication interface includes data-interface and control interface
A boundary moment to each interface calculates.The register of SOC chip read signal has 63 delay (delay) settings, often
A step (delayed step) is 50 picoseconds (ps), is up to 3.150ns, but the clock cycle of a 200Mhz is 5ns, only this
Delay setting can not find read signal window edge.There are 4 according to the sampling clock of SDIO read signal in the present embodiment
Phase, each period are 5ns, and each phase is 1.25ns, cooperates the maximum delay time 3.125ns of SOC chip register, can
Find the window edge of read signal.
S2. a delay rank is calculated according to the difference of the delayed step number between the two of the communication interface boundaries
The delay time of ladder.
In the present embodiment, by adjusting the phase of the sampling clock of the communication interface of control unit, and communication is connect
Mouth carries out delay process, obtains two boundaries of the corresponding communication interface under different sampling clock phases, adopts further according to difference
Different delayed time ladder number under sample clock phase calculates the delay time of single delayed step, in order to be obtained according to practical calculating
The delay time that the delay time of the delayed step taken carries out control unit is adjusted, and improves the stability of memory module.
In a preferred embodiment, a according to the delayed step between the two of the communication interface boundaries in the S2
The difference of number calculates the delay time of a delayed step, comprising:
According to the difference of the delayed step number between two boundaries of any data interface in the communication interface, and obtain
The delay time of two phase difference calculatings, one delayed step of corresponding sampling clock when taking described two boundaries.
In the present embodiment, it is contemplated that communication interface may include data-interface and control interface, carry out delayed step
Delay time calculate when, can according to any interface in different sampling clock phases corresponding boundary, calculated.
For example and without limitation, with storage unit use SDIO unit, control unit use SOC chip for acquisition
The method of memory module internal delay time ladder time is illustrated:
As shown in figure 3, the boundary value of read signal DATA0 is 0x29 when the phase co-phase=2 of sampling clock；Sampling
When the phase co-phase=1 of clock, the boundary value of read signal DATA0 is that (grey rectangle indicates the positive normal open of interface to 0x19 in figure
Letter, white rectangle indicate interface exceptional communication), 0x29-0x19=0x10 (for 16 system numbers), so sharing 16 delay ranks
Ladder, phase phase difference position 1.25ns of the phase co-phase of sampling clock between 2 and 1, then the inside of single delayed step is prolonged
Shi Yuewei 1.25/16=0.078ns, i.e., each step that single delayed step is 78ps and SOC chip specification provides is 50ps
It is not consistent, uses single delayed step 78ps for more accurate value.
It should be noted that the method for obtaining the memory module internal delay time ladder time applies also for eMMC
In the communication interface adjustment of (Embedded Multi Media Card) card or TF (Trans-flash Card) card, in order to
Meet cabling requirement when design, improves the stability of system.
As shown in figure 4, the present invention also provides a kind of system for obtaining the memory module internal unit delayed step time, institute
Stating memory module includes storage unit and control unit, according to the rising edge of the sampling clock of described control unit to the control
The communication interface of unit is sampled；The system for obtaining the memory module internal unit delayed step time can include: processing unit 1
With computing unit 2；Wherein:
Processing unit 1, for prolonging respectively to the communication interface under the sampling clock of at least two outs of phase
When handle, obtain two boundaries of the communication interface；
Computing unit 2, the difference for the delayed step number between two boundaries according to the communication interface calculate one
The delay time of a delayed step.
It should be noted that SDIO unit can be used in storage unit；SOC chip can be used in control unit.This method can answer
For storage unit to during control unit read operation.
In the present embodiment, by adjusting the phase of the sampling clock of the communication interface of control unit, and communication is connect
Mouth carries out delay process, obtains two boundaries of the corresponding communication interface under different sampling clock phases, adopts further according to difference
Different delayed time ladder number under sample clock phase calculates the delay time of single delayed step, in order to be obtained according to practical calculating
The delay time that the delay time of the delayed step taken carries out control unit is adjusted, and improves the stability of memory module.
In a preferred embodiment, the processing unit 1 includes:
Postponement module, for carrying out delay process to the communication interface when the sampling clock is default phase；
Whether first judgment module, the communications status for judging the communication interface are normal；
Accumulation module, for adding up the number of the communication interface communication abnormality；
Module is obtained, for obtaining the communication interface delayed step when the communications status exception of the communication interface
Number；
Second judgment unit, for judging whether the number of communication abnormality of the communication interface is less than or equal to 1；
Adjustment module, when the communications status of the communication interface is normal or the number of the communication abnormality of the communication interface
When being less than or equal to 1, the phase for adjusting unit and being used to adjust the sampling clock is delayed to the communication interface
Processing.
Further, the adjustment module is used to adjust the phase shift that the current phase of the sampling clock carries out 90 degree,
Delay process is carried out to the communication interface.
In a preferred embodiment, the computing unit 2 is used for according to two of any data interface in the communication interface
The difference of delayed step number between a boundary, and obtain two phases of corresponding sampling clock when described two boundaries
Potential difference calculates the delay time of a delayed step.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (8)
1. a kind of method for obtaining the memory module internal delay time ladder time, the memory module includes that storage unit and control are single
Member is sampled according to communication interface of the rising edge of the sampling clock of described control unit to described control unit；Its feature
It is, the method includes the following steps:
S1. under the sampling clock of at least two outs of phase, delay process is carried out to the communication interface respectively, described in acquisition
Two boundaries of communication interface；
S2. the delayed step is calculated according to the difference of the delayed step number between the two of the communication interface boundaries
Delay time.
2. the method according to claim 1 for obtaining the memory module internal delay time ladder time, which is characterized in that the step
Rapid S1 carries out delay process to the communication interface respectively under the sampling clock of at least two outs of phase, obtains described logical
Believe two boundaries of interface, comprising:
S11. when the sampling clock is default phase, delay process is carried out to the communication interface；
S12. judge whether the communications status of the communication interface is normal, if so, executing step S15；If it is not, adding up the communication
The number of interface communication exception executes step S13；
S13. the communication interface delayed step number is obtained, step S14 is executed；
S14. judge whether the number of the communication abnormality of the communication interface is less than or equal to 1, if executing step S15, if not
Execute step S2；
S15. the phase for adjusting the sampling clock carries out delay process to the communication interface, executes step S12.
3. the method according to claim 2 for obtaining the memory module internal delay time ladder time, which is characterized in that described
The phase that the sampling clock is adjusted in step S15 carries out delay process to the communication interface, comprising:
The phase shift adjustment that 90 degree are carried out to the current phase of the sampling clock, carries out delay process to the communication interface.
4. the method according to claim 1 for obtaining the memory module internal delay time ladder time, which is characterized in that described
Prolonging for the delayed step is calculated according to the difference of the delayed step number between the two of the communication interface boundaries in S2
When the time, comprising:
According to the difference of the delayed step number between two boundaries of any data interface in the communication interface, and obtain institute
State the delay time of two phase difference calculatings, one delayed step of corresponding sampling clock when two boundaries.
5. a kind of system for obtaining the memory module internal unit delayed step time, the memory module includes storage unit and control
Unit processed is sampled according to communication interface of the rising edge of the sampling clock of described control unit to described control unit；Its
It is characterized in that, comprising:
Processing unit, for being carried out at delay to the communication interface under the sampling clock of at least two outs of phase respectively
Reason, obtains two boundaries of the communication interface；
Computing unit, the difference for the delayed step number between two boundaries according to the communication interface calculate described in one
The delay time of delayed step.
6. the system according to claim 5 for obtaining the memory module internal unit delayed step time, which is characterized in that institute
Stating processing unit includes:
Postponement module, for carrying out delay process to the communication interface when the sampling clock is default phase；
Whether first judgment module, the communications status for judging the communication interface are normal；
Accumulation module, for adding up the number of the communication interface communication abnormality；
Module is obtained, for obtaining the communication interface delayed step number when the communications status exception of the communication interface；
Second judgment unit, for judging whether the number of communication abnormality of the communication interface is less than or equal to 1；
Adjustment module, when the communications status of the communication interface is normal or the number of the communication abnormality of the communication interface is small
When 1, the phase for adjusting unit and being used to adjust the sampling clock carries out at delay the communication interface
Reason.
7. the system according to claim 6 for obtaining the memory module internal unit delayed step time, which is characterized in that institute
It states the phase shift that adjustment module carries out 90 degree for the current phase to the sampling clock to adjust, the communication interface is prolonged
When handle.
8. the system according to claim 5 for obtaining the memory module internal unit delayed step time, which is characterized in that institute
Computing unit is stated for according to the difference of the delayed step number between two boundaries of any data interface in the communication interface,
And two phase difference calculatings, one delayed step of the corresponding sampling clock prolongs when obtaining described two boundaries
When the time.
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Cited By (1)
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| CN109359067A (en) * | 2018-10-17 | 2019-02-19 | 晶晨半导体(上海)股份有限公司 | Obtain the method and system of memory module internal delay time ladder time |
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