JP2018142366A - Semiconductor device, data communication system, and data writing control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable prohibition release to be performed at an appropriate timing when data update in a storage part is prohibited.SOLUTION: A semiconductor device comprises: a control signal output part which shifts a control signal output from an output terminal to the first level when data is read out from a storage part, and shifts the control signal to the second level when a release signal input to the reset input terminal is shifted to a prescribed level; a release signal output part which outputs the release signal whose signal level is shifted to the prescribed level to supply it to a reset input terminal after the elapse of a prescribed period from the shifting of the signal level of the control signal to the first level; and a data update control part which prohibits update of the data stored in the storage part when the signal level of the control signal is at the first level and permits updating of the data stored in the storage part when the signal level of the control signal is at the second level.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, a data communication system, and a data write control method.

  As a technique related to data communication between semiconductor devices, for example, in Patent Document 1, serial data is input while a chip select signal supplied from a microcomputer is active, and then the chip select signal is inactive. There is described a serial EEPROM configured to write input data to a memory cell when changed to. When the rising edge of the chip select signal is detected, the serial EEPROM data input control unit permits the input of serial data. When the falling edge is detected before the end of the data input cycle, the data input control unit is based on the detected edge. Prohibit serial data input.

Japanese Patent Laid-Open No. 2003-331877

  In a data communication system that performs serial communication between semiconductor devices, data stored in a register provided in one semiconductor device (subcomputer) is read to the other semiconductor device (main computer) and data for the register is stored. There is a thing in which writing is performed asynchronously. In such a data communication system, there is a possibility that the read timing and write timing of data to the register overlap. In the case where the register stores multi-bit data including a plurality of bits, the register may be configured by a storage circuit such as a plurality of flip-flops. A common clock signal is supplied to each of the plurality of memory circuits, and data is written simultaneously in synchronization with the clock signal. However, the input timing of the clock signal in each memory circuit is slightly shifted due to a wiring length difference or the like. This causes a shift in data write timing (update timing) in each memory circuit. Therefore, when the data read timing and the write timing overlap in the register, there is a possibility that mismatch between bits occurs in the read data. That is, in the read data, there is a possibility that the bit after the data update and the bit before the data update are mixed.

  In order to prevent such inconsistency between bits in the read data, it is conceivable to prohibit the update of data to the register when the data is read from the register. In this way, when data is prohibited from being updated in the register when data is read from the register, in order to prevent a stagnation of processing in the semiconductor device, the register is promptly read after completion of data reading from the register. It is desirable to release the prohibition of data update in

  Therefore, the completion of reading data from the register is determined based on the chip select signal and the communication clock signal supplied from the master-side semiconductor device (main computer), and the slave-side semiconductor device ( A method of canceling the prohibition of data update in the register provided in the sub-computer) can be considered.

  Here, the chip select signal is a signal for notifying the start and end of communication given from the master-side semiconductor device (main computer) to the slave-side semiconductor device (subcomputer). The semiconductor device (main computer) on the master side notifies the start of communication to the slave side (sub computer) by, for example, changing the chip select signal to high level, and changes the chip select signal to low level. Then, the end of communication is notified to the semiconductor device (subcomputer) on the slave side. For example, when the end of communication is notified by the chip select signal, the semiconductor device (subcomputer) on the slave side determines that the reading of data to the register has been completed, and cancels the prohibition of updating the data in the register To do.

  On the other hand, the communication clock signal is a clock signal given from the master-side semiconductor device (main computer) to the slave-side semiconductor device (subcomputer), and communication between these semiconductor devices is synchronized with the communication clock. Done. For example, the semiconductor device (subcomputer) on the slave side determines that the reading of data from the register has been completed based on a communication clock signal supplied after data updating is prohibited in the register. Cancel the prohibition of data update.

  However, in the method in which the completion of reading data from the register is determined based on the chip select signal and the communication clock signal and the prohibition of updating the data in the register is canceled, the prohibition of updating may not be properly performed. . That is, the master-side semiconductor device (main computer) may stop supplying the communication clock signal immediately after the data update is prohibited in the register. Further, the master-side semiconductor device (main computer) may continue to maintain the chip select signal in the active state (high level) even after the data reading to the register is completed. In such a case, the semiconductor device (subcomputer) on the slave side cannot determine the completion of reading data from the register, and cannot quickly cancel the prohibition of data update.

  The present invention has been made in view of the above points, and in the case where updating of data in a storage unit such as a register is prohibited, a semiconductor device, a data communication system, and data writing that can be released at an appropriate timing An object is to provide a control method.

  The semiconductor device according to the present invention is stored in the first storage unit when data is written and read asynchronously and when data is read from the first storage unit. Control to cancel the update of the data stored in the storage unit after a predetermined period has elapsed since the update of the data stored in the first storage unit is prohibited. Control means to perform.

  According to the present invention, there is provided a semiconductor device, a data communication system, and a data write control method capable of canceling prohibition at an appropriate timing when updating of data in a storage unit such as a register is prohibited.

It is a block diagram which shows the structure of the data communication system which concerns on embodiment of this invention. It is a block diagram which shows the structure of the subcomputer which concerns on embodiment of this invention. It is a figure which shows the state with which the write-in timing and read-out timing of data overlapped. It is a timing chart which shows an example of operation of a subcomputer concerning an embodiment of the present invention. It is a timing chart which shows an example of operation of a subcomputer concerning an embodiment of the present invention. It is a block diagram which shows the structure of the subcomputer which concerns on other embodiment of this invention. It is a circuit diagram about the composition of the filter concerning other embodiments of the present invention. It is a block diagram which shows the structure of the subcomputer which concerns on a comparative example. It is a timing chart which shows an example of operation of a subcomputer concerning a comparative example.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding components and parts are denoted by the same reference numerals.

[First Embodiment]
FIG. 1 is a block diagram showing an example of a configuration of a data communication system 100 according to the embodiment of the present invention. The data communication system 100 according to the present embodiment includes a main computer 10, a sub computer 20, and sensors 12a and 12b. The main computer 10, the sub computer 20, and the sensors 12a and 12b are each configured as an independent semiconductor device and are mounted on a single wiring board. The subcomputer 20 is an example of a semiconductor device in the present invention, and the main computer 10 is an example of another semiconductor device in the present invention. The data communication system 100 is an example of a data communication system in the present invention.

  The sensors 12a and 12b are, for example, a temperature sensor, a humidity sensor, an acceleration sensor, a geomagnetic sensor, an infrared sensor, a pressure sensor, a proximity sensor, an illuminance sensor, and the like. The sensors 12a and 12b may be different types of sensors. In addition, although the data communication system 100 according to the present embodiment is configured to include two sensors, it may be configured to include one or three or more sensors.

  In the communication system 100 according to the present embodiment, the main computer 10 is, for example, an application processor, and the sub computer 20 is a microcontroller that controls the sensors 12a and 12b. Since the sub computer 20 is responsible for sensor control, the load on the main computer 10 can be reduced as compared with a configuration in which the main computer 10 performs sensor control. That is, while the sub computer 20 is accessing the sensors 12a and 12b, the main computer 10 can be in a standby state. Thereby, it becomes possible to suppress the power consumption of the whole system.

  The main computer 10 and the sub computer 20 are connected by an SPI (Serial Peripheral Interface) bus 301 and an I2C (I-squared-C) bus 302. The main computer 10 and the sub computer 20 perform serial communication of data via one or both of the SPI bus 301 and the I2C bus 302.

  The SPI bus 301 forms a transmission path between the terminals 101 to 104 of the main computer 10 and the corresponding terminals 201 to 204 of the sub computer 20. A chip select signal SCS output from the main computer 10 is supplied to the terminal 201 of the subcomputer 20. The chip select signal SCS notifies the start and end of data communication performed via the SPI bus 301 performed between the main computer 10 and the sub computer 20. The main computer 10 changes the chip select signal SCS to a high level when starting data communication with the sub computer 20, and changes the chip select signal SCS to a low level when ending communication. The chip select signal SCS can also be used by the main computer 10 to select a sub computer that performs data communication with the main computer 10 in a system in which a plurality of sub computers exist, for example.

  A communication clock signal SCLK output from the main computer 10 is supplied to the terminal 202 of the subcomputer 20. Data communication between the main computer 10 and the sub computer 20 performed via the SPI bus 301 is performed in synchronization with the communication clock signal SCLK.

  An input signal SDI output from the main computer 10 is supplied to the terminal 203 of the subcomputer 20. The input signal SDI includes a command indicating a process to be executed by the sub computer 20, and when data is read from a register provided in the sub computer 20, address information indicating a data read start position is included. .

An output signal SDO output from the terminal 204 of the subcomputer 20 is supplied to the main computer 10 via the SPI bus 301. In the data communication system 100 according to this embodiment, the sensing data _{D A} and _{D B} of the sub-computer 20 has obtained from the sensor 12a and 12b may be supplied to the main computer 10 as an output signal SDO.

  The I2C bus 302 forms a transmission path between the terminals 105 and 106 of the main computer 10 and the corresponding terminals 205 and 206 of the subcomputer 20. A communication clock signal SCL output from the main computer 10 is supplied to a terminal 205 of the subcomputer 20. Data communication between the main computer 10 and the sub computer 20 performed via the I2C bus 302 is performed in synchronization with the communication clock signal SCL. A terminal 206 of the sub computer 20 is a terminal for inputting / outputting a data signal SDA input / output from / to the main computer 10. That is, the data signal SDA is a bidirectional signal.

Sensing data D _A and D _B output from the sensors 12a and 12b, respectively, are supplied to the sub computer 20 via terminals 207 and 208, respectively.

  FIG. 2 is a block diagram showing a configuration of the sub computer 20. In FIG. 2, the components connected to the I2C bus 302 are not shown.

  The sub computer 20 includes an interface unit 21 and a function unit 22. The function unit 22 includes data update control units 30a and 30b, input stage registers 31a and 31b, a clock generation unit 32, and a CPU (Central Processing Unit) 40.

Input stage register 31a is a storage unit for storing the sensing data D _A which is output from the sensor 12a, the input stage register 31b is a storage unit for storing the sensing data D _B outputted from the sensor 12b. Input stage registers 31a and 31b are each composed, including a plurality of flip-flops to hold the value of each bit of the sensing data D _A and D _B composed of a plurality of bits. In this embodiment, the input stage registers 31a and 31b correspond to the sensors 12a and 12b, respectively. However, the input stage registers 31a and 31b do not have a corresponding relationship with the sensors 12a and 12b. May be. In the present embodiment, the sub computer 20 includes two input stage registers 31a and 31b. However, the number of input stage registers may be one or three or more. The input stage registers 31a and 31b are an example of a storage unit in the present invention.

Input stage registers 31a and 31b, respectively, synchronizes the sensing data _{D A} and _{D B} from the sensors 12a and 12b are supplied through the data update control unit 30a and 30b to the clock signal _{C X} generated by the clock generator 32 Capture and hold. Clock signal _{C X} includes a communication clock signal SCLK supplied from the main computer 10 is asynchronous. That is, the data writing based on the clock signal _CX and the data reading based on the communication clock signal SCLK are performed asynchronously with respect to the input stage registers 31a and 31b.

Data update control unit 30a, when the write address indicated by the write address signal WA supplied from CPU40 is the address of the input stage register 31a corresponding to itself, the input stage register sensing data D _A received from the sensor 12a To 31a. The data update control unit 30a determines whether to update or permit updating of data stored in the input stage register 31a based on an update prohibition signal _SF and a read address signal RA, which will be described later. Data update control unit 30a, when prohibiting updates data stored in the input stage register 31a, and supplies the input stage register 31a continues sensing data D _A for update prohibition immediately before. That is, the input stage register 31a is, in a period in which data updating is prohibited, continuously maintains the sensing data D _A which holds the updated prohibited immediately before. On the other hand, the data update control section 30a, to allow updates stored in the input stage register 31a data sequentially updated while outputting the sensing data D _A received from the sensor 12a. That is, in the period in which data updating is permitted, the sensing data D _A which is stored in the input stage register 31a is sequentially updated.

Data update control section 30a, the input stage register 31a of the read address update prohibition signal S _F is indicated by and read address signal RA exhibited (low level in this embodiment) signal level indicating an update prohibition data corresponding to itself If the address is, the update of the data stored in the input stage register 31a is prohibited, and otherwise the update of the data stored in the input stage register 31a is permitted.

Similarly, the data update control unit 30b, if the write address indicated by the write address signal WA supplied from CPU40 is the address of the input stage register 31b corresponding to itself, the sensing data D _B received from the sensor 12b This is supplied to the input stage register 31b. The data update control unit 30b determines whether to update or permit updating of the data stored in the input stage register 31b based on the update prohibition signal _SF and the read address signal RA. Data update control unit 30b, when prohibiting updates stored in the input stage register 31b data, and supplies the input stage register 31b continuously sensing data D _B of the update prohibition immediately before. That is, the input stage register 31b, in the period in which the updating of the data is prohibited, continuously maintains the sensing data D _B held from update prohibition immediately before. On the other hand, the data update control unit 30b, when allowed to update the data stored in the input stage register 31b, and outputs while sequentially updating the measured data D _B received from the sensor 12b. That is, in the period in which data updating is permitted, the sensing data D _B stored in the input stage register 31b is sequentially updated.

Data update control unit 30b is input stage register 31b to the read address update prohibition signal S _F is indicated by and read address signal RA exhibited (low level in this embodiment) signal level indicating an update prohibition data corresponding to itself If the address is, the update of the data stored in the input stage register 31b is prohibited, and otherwise the update of the data stored in the input stage register 31b is permitted. The data update control units 30a and 30b are examples of the data update control unit in the present invention.

  On the other hand, the interface unit 21 of the subcomputer 20 includes a serial / parallel conversion unit 23, an address generation unit 24, a determination unit 25, an update prohibition register 26, a selector 27, an output stage register 28, and a parallel / serial conversion unit 29.

The selector 27, based on the read address signal RA generated by the address generator 24, input stage registers 31a and selects one of the 31b, the selected input stage registers 31a or 31b to the stored sensing data D _A or to the output stage register 28 and _{D B.} The selector 27 selects the input stage register 31a when the read address indicated by the address signal RA is the address of the input stage register 31a, and the read address indicated by the address signal RA is the address of the input stage register 31b. The input stage register 31b is selected.

The output stage register 28 is a storage unit that stores the sensing data D _A or D _B supplied from the selector 27 in synchronization with the communication clock signal SCLK. The output stage register 28 includes a plurality of flip-flops corresponding to each of the plurality of flip-flops constituting the input stage registers 31a and 31b. Data communications has become a parallel communication, the value of each bit of the sensing data D _A and D _B are input stage register in synchronization with the communication clock signal SCLK between the input stage registers 31a and 31b and the output stage register 28 The data are transferred from 31a or 31b to the output stage register 28 at once.

The parallel / serial converter 29 converts the sensing data D _A or D _B given as parallel data from the output stage register 28 into serial data. The parallel / serial conversion unit 29 outputs the sensing data D _A or D _B converted into serial data from the terminal 204 as an output signal SDO, and supplies it to the main computer 10.

  The serial / parallel converter 23 converts the input signal SDI, which is serial data from the main computer 10 input to the terminal 203, into parallel data and supplies the parallel data to the address generator 24. When data is read from the input stage registers 31a and 31b, the input signal SDI includes address information indicating the data read start position.

  The address generation unit 24 specifies a read address by generating a read address signal RA based on address information included in the input signal SDI converted into serial data. The address generation unit 24 has a function of sequentially incrementing the read address at a predetermined timing synchronized with the communication clock signal SCLK. The read address signal RA is supplied to the data update control units 30a and 30b, the selector 27, and the determination unit 25, respectively.

The determination unit 25 determines whether or not the read address indicated by the read address signal RA matches the write address indicated by the write address signal WA. The determination unit 25 outputs a low-level determination signal _SD when it is determined that the read address and the write address match, and outputs a high-level determination signal _SD when it is determined that they do not match. When the determination unit 25 detects the rising edge of the communication clock signal SCLK after outputting the low level determination signal _SD , the determination unit 25 resets the determination signal _SD to the initial high level.

Update prohibition register 26 is configured to include a flip flop in synchronization with the communication clock signal SCLK maintains capture the value of the judgment signal S _D, and outputs the the held value as the update prohibition signal S _F. Update prohibition register 26, the decision signal S and the input terminal D for receiving an input of _D, a clock input terminal C for receiving an input of the communication clock signal SCLK, an output terminal Q for outputting the value stored as an update prohibition signal S _F When, and a reset input terminal R for accepting an input reset signal S _R for resetting the update prohibition signal to the high level in the initial state. The output terminal Q of the update prohibition register 26 is connected to the data update control units 30a and 30b, and is connected to an input terminal of a delay element 50 described later.

Update prohibition signal S _F is a control signal for controlling the update inhibiting and update permission data stored in the input stage registers 31a and 31b. As described above, in the present embodiment, when the update prohibiting signal S _F exhibits a low level, the update data is prohibited in any of the input stage registers 31a and 31b. According to the configuration of the sub-computer 20 according to the present embodiment, when the read address indicated by the read address signal RA and the write address indicated by the write address signal WA match, that is, in the same input stage register, When writing and reading are about to be performed at the same time, updating of data in the input stage register is prohibited.

Update prohibition register 26, when the update prohibition signal S _F is exhibited low level, the reset signal S _R that is input to the reset input terminal R changes to the low level, there an update prohibition signal S _F in the initial state Reset to high level. When the update prohibition signal _SF is reset, the data update prohibition in the input stage register 31a or 31b is released. The update prohibition register 26 is an example of a control signal generation unit in the present invention, and the update prohibition signal _SF is an example of a control signal in the present invention.

  In the sub-computer 20, since data writing and data reading to and from the input stage registers 31a and 31b are performed asynchronously, there is a possibility that the data writing timing and the reading timing overlap the same input stage register. When data writing and reading are performed at the same time on the same input stage register, there is a risk of mismatch between bits in the read data.

FIG. 3 is a diagram for explaining a mismatch between bits in the read data. FIG. 3 illustrates a case where data writing and reading in each flip-flop corresponding to the first to third bits of the input stage register 31a or 31b occur substantially simultaneously. The input timing of the clock signal _CX to each flip-flop may be shifted from each other due to a wiring length difference or the like, and accordingly, the data write timing may be shifted from each other in each flip-flop. Further, as shown in FIG. 3, there is a case where data is read after writing of the first bit data and the second bit data and before writing of the third bit data. In this case, the updated data is read in the first bit and the second bit, and the data before update is read in the third bit. In this way, when data writing and reading are performed at the same time on the same input stage register, there is a possibility that mismatch between bits occurs in the read data.

  According to the sub-computer 20 according to the present embodiment, when data writing and reading are being performed simultaneously in the same input stage register, data updating is prohibited in the input stage register. Therefore, it is possible to prevent mismatch between bits in the read data.

Refer to FIG. 2 again. The subcomputer 20 includes a delay element 50 and an AND gate 52 between the output terminal Q and the reset input terminal R of the update prohibition register 26. The delay element 50 has an input terminal connected to the output terminal Q of the update prohibition register 26 and an output terminal connected to one input terminal of the AND gate 52. Delay element 50 is a circuit that outputs a signal to update prohibition signal S _F is delayed by a predetermined delay time is output from the update disable register 26. The delay element 50 can be configured to include, for example, a plurality of NOT gates or buffer circuits connected in series. The other input terminal of the AND gate 52 is connected to a terminal 201 to which a chip select signal SCS is input. The output terminal of the AND gate 52 is connected to the reset input terminal R of the update prohibition register 26. AND gate 52 supplies the reset input terminal R of the update prohibition register 26 and outputs the result of calculating the logical product of the output signal of the chip select signal SCS and the delay element 50 as a reset signal S _R. The delay element 50 is an example of a delay circuit in the present invention, and the delay element 50 and the AND gate 52 are an example of a release signal output unit in the present invention. Reset signal S _R is an example of a release signal in the present invention.

Thus, by providing the delay element 50 and an AND gate 52 between the output terminal Q and reset input terminal R of the update prohibition register 26, the delay element 50 update prohibition signal S _F is from the transition to the low level It is possible to reset the update prohibition signal _SF to the initial high level after the elapse of a predetermined period. That is, when data update is prohibited in the input stage register 31a or 31b, if a predetermined time elapses, data update is prohibited in the input stage register regardless of the state of the chip select signal SCS or the communication clock signal SCLK. Can be released. Thereby, it is possible to prevent the input stage register 31a or 31b from being released for a long time and the processing from being stagnated. According to the configuration of the subcomputer 20 according to the present embodiment, the update prohibition register 26 is reset even when the chip select signal SCS becomes low level, that is, when the end of communication is notified from the main computer 10. it is possible to transition the update prohibition signal S _F to a low level Te.

  Hereinafter, the operation of the sub computer 20 will be described. FIG. 4 is a timing chart showing an example of the operation of the sub computer 20. The subcomputer 20 starts communication with the main computer 10 when the chip select signal SCS supplied from the main computer 10 via the terminal 201 becomes high level.

  After the chip select signal SCS becomes high level, the communication clock signal SCLK and the input signal SDI are supplied from the main computer 10 to the sub computer 20. Communication between the main computer 10 and the sub computer 20 is performed in synchronization with the communication clock signal SCLK.

The input signal SDI is input from the terminal 203 and supplied to the serial / parallel converter 23. The serial / parallel converter 23 converts the input signal SDI supplied as serial data into parallel data and outputs the parallel data. The input signal SDI includes a command indicating processing to be executed by the subcomputer 20, and when data is read from the input stage registers 31a and 31b, address information indicating a data reading start position is included. . Here, it is assumed that address information of the input stage register 31a is included in the input signal SDI as a read start address with the command that instructs read-out of the input stage register 31a and the sensing data stored in 31b D _A and D _B .

  The address generator 24 generates the read address signal RA based on the address information included in the input signal SDI. Here, it is assumed that the read address signal RA indicating the address of the input stage register 31a is generated. The address generation unit 24 supplies the generated read address signal RA to the determination unit 25, the selector 27, and the data update control units 30a and 30b.

When the read address is specified by the read address signal RA, the determination unit 25 determines whether or not the specified read address matches the write address indicated by the write address signal WA supplied from the CPU 40. . That is, the determination unit 25 determines whether data is being written and read simultaneously in either the input stage register 31a or 31b. If the determination unit 25 determines that the read address and the write address match, the determination unit 25 outputs a low-level determination signal _SD . On the other hand, when the determination unit 25 determines that the read address and the write address do not match or when the write address is not designated, the determination unit 25 outputs a high-level determination signal _SD . Here, it is assumed that the address of the input stage register 31a is specified in both the read address and the write address, and the determination unit 25 outputs a low-level determination signal _SD .

Update prohibition register 26, the judgment signal S _D is becomes a low level, in synchronism with the communication clock signal SCLK and outputs the update prohibition signal S _F of the low level from the output terminal Q. Update prohibition register 26 supplies an update prohibition signal _{S F} to the data update control unit 30a and 30b.

Data update control unit 30a, since the read address update prohibition signal S _F is indicated by and the read address signal RA exhibited low level is the address of the input stage register 31a corresponding to itself, stored in the input stage register 31a Prohibit data update. Input stage register 31a during the updating of the data is prohibited, continuously maintains the sensing data D _A which holds the updated prohibited immediately before. On the other hand, the data update control unit 30b permits the update of data in the input stage register 31b because the read address indicated by the read address signal RA is not the address of the input stage register 31b corresponding to itself.

The selector 27 selects the input stage register 31a because the read address indicated by the read address signal RA is the address of the input stage register 31a. Selector 27, within a period update of data in the input stage register 31a is disabled, supplies sensing data D _A which is stored in the input stage register 31a to the output stage register 28. As described above, when data is read from the input stage register 31a, the update of data in the input stage register 31a is prohibited, thereby preventing inconsistency between bits in the read data.

When the determination unit 25 detects the rising edge of the communication clock signal SCLK after outputting the low-level determination signal _SD , the determination unit 25 resets the determination signal _SD to the initial high level. That is, update prohibition signal S _F transitions after completion of the data transfer from the input stage register 31a to the output stage register 28 to the high level. As a result, the prohibition of data update in the input stage register 31a is released.

Sensing data D _A which is stored in the output stage register 28 is supplied to a parallel / serial converter 29. Parallel / serial converter 29 converts the measured data D _A which is supplied as parallel data into serial data. Parallel / serial converter 29, and sequentially output from the terminal 204 in synchronism with the communication clock signal SCLK sensing data D _A was converted into the serial data as an output signal SDO, and supplies to the main computer 10.

Address generator 24, the transfer to the main computer 10 of the sensing data D _A which has been converted into serial data is completed, a new read address signal is incremented by one the value of the read address in synchronization with the communication clock signal SCLK Generate RA. Thereby, the address of the input stage register 31b is designated as the read address.

When a read address is newly specified, the determination unit 25 determines whether or not the newly specified read address matches the write address. If the determination unit 25 determines that the read address and the write address match, the determination unit 25 outputs a low-level determination signal _SD . Here, it is assumed that the address of the input stage register 31b is specified in both the read address and the write address, and the determination unit 25 outputs a low-level determination signal _SD .

Update prohibition register 26, the judgment signal S _D is becomes a low level, in synchronism with the communication clock signal SCLK and outputs the update prohibition signal S _F of the low level from the output terminal Q. The update prohibition register 26 supplies an update prohibition signal _SF to the data update control units 30a and 30b.

Data update control unit 30b, since the read address update prohibition signal S _F is indicated by and the read address signal RA exhibited low level is the address of the input stage register 31b corresponding to itself, stored in the input stage register 31b Prohibit data update. Input stage register 31b while the updating of the data is prohibited, continuously maintains the sensing data D _B held from update prohibition immediately before. On the other hand, since the read address indicated by the read address signal RA is not the address of the input stage register 31a corresponding to itself, the data update control unit 30a permits the data update in the input stage register 31a.

The selector 27 selects the input stage register 31b because the read address indicated by the read address RA is the address of the input stage register 31b. Selector 27, within a period update of data in the input stage register 31b is prohibited, supplies sensing data D _B stored in the input stage register 31b to the output stage register 28. As described above, when data is read from the input stage register 31b, the update of data in the input stage register 31b is prohibited, thereby preventing inconsistency between bits in the read data.

When the determination unit 25 detects the rising edge of the communication clock signal SCLK after outputting the low-level determination signal _SD , the determination unit 25 resets the determination signal _SD to the initial high level. That is, update prohibition signal S _F transitions after completion of the data transfer from the input stage register 31b to the output stage register 28 to the high level. As a result, the prohibition of data update in the input stage register 31b is released.

5, the input stage register 31a supplies the communication clock signal SCLK at a stage where transmission to the main computer 10 of the stored sensing data D _A is completed is stopped and the chip select signal SCS is maintained at the high level 6 is a timing chart showing the operation of the sub computer 20 in the case of failure. State of the communication clock signal SCLK and the chip select signal SCS, as shown in FIG. 5, for example, require only read sensing data D _A main computer 10 is stored in the input stage register 31a, stored in the input stage register 31b It may occur when not requesting reading for sensing data D _B which is.

According to the sub computer 20 according to the present embodiment, even when the main computer 10 does not require to read the sensor data D _B, by the automatic increment function of the address value address generator 24 has a main computer 10 for sensing data D _A At the stage when transmission to is completed, the address of the input stage register 31b is designated as a read address. When the newly read address, in response to the determination processing result of the determination unit 25, update prohibition signal S _F to update the data is prohibited in the input stage register 31b transitions to a low level.

Delay element 50, the update inhibit signal S _F from the transition to the low level, outputs a signal transition after a delay time determined by the circuit configuration of itself in a low level. The AND gate 52 calculates the logical product of the output signal of the delay element 50 and the chip select signal SCS, thereby outputting the reset signal SR that transitions to the low level at the timing when the output signal of the delay element 50 transitions to the low level. And supplied to the reset input terminal R of the update prohibition register 26. Update prohibition register 26, a reset signal S _R of the low level to the reset input terminal R is input, resets the update prohibition signal S _F to a high level which is an initial state. As a result, the prohibition of data update in the input stage register 31a is released.

Thus, according to the sub computer 20 according to the present embodiment, the update inhibit signal S _F is changed to the high level by the period corresponding to the delay time of the delay element 50 from the transition to the low level it has elapsed. That is, the sub-computer 20 can autonomously cancel the prohibition of data update in the input stage registers 31a and 31b.

  Here, FIG. 8 is a block diagram showing a configuration of the sub-computer 20X according to the comparative example. In FIG. 8, the same or corresponding components as those of the sub computer 20 according to the embodiment of the present invention are given the same reference numerals, and redundant descriptions are omitted. The sub computer 20X according to the comparative example does not include the delay element 50 and the AND gate 52 included in the sub computer 20 according to the embodiment of the present invention, and the chip select signal is supplied to the reset input terminal R of the update prohibition register 26. The SCS is directly input.

9, the supply of the communication clock signal SCLK at a stage where the supply to the main computer 10 of the sensing data D _A which is stored in the input stage register 31a has been completed is stopped, and maintains the chip select signal SCS is a high level state It is a timing chart which shows operation | movement of the subcomputer 20X in the case where it was carried out.

According to the sub computer 20X according to the comparative example, similarly to the sub computer 20 according to the present embodiment, even when the main computer 10 does not require to read the sensor data D _B, auto-increment function of the address value address generator 24 has Accordingly, at the stage where transmission to the main computer 10 of the sensing data D _a is completed, the address of the input stage register 31b is designated as a read address. If a new read address is specified, according to the determination processing result of the determination unit 25, update prohibition signal S _F to update the data it is prohibited in the input stage register 31b transitions to a low level.

According to the sub computer 20X according to the comparative example, as shown in FIG. 9, the supply of the communication clock signal SCLK at a stage where the supply to the main computer 10 of the sensing data D _A is completed is stopped, and the chip select signal SCS is If it is maintained at a high level, since the update inhibiting register 26 is not reset, update prohibition signal S _F is maintained at the low level. As a result, the state where the update of data is prohibited in the input stage register 31b continues. As a result, the processing may be stagnated in the sub computer 20X. As described above, when the cancellation of the data update prohibition in the input stage registers 31a and 31b is performed based only on the signal supplied from the main computer 10, the cancellation of the data update prohibition is performed at an appropriate timing. It may not be possible.

On the other hand, according to the sub computer 20 according to the embodiment of the present invention, the update inhibit signal S _F, since the predetermined time period determined by the delay element 50 from the transition to the low level is switched to the high-level state on the expiration, the communication Regardless of the state of the clock signal SCLK and the chip select signal SCS, it is possible to cancel the prohibition of data update.

[Second Embodiment]
FIG. 6 is a block diagram showing a configuration of a sub computer 20A according to the second embodiment of the present invention. In FIG. 6, the same or corresponding components as those of the sub computer 20 according to the first embodiment are given the same reference numerals, and redundant descriptions are omitted. Sub computer 20A uses filter 54 as a means for applying a delay time with respect update prohibition signal S _F.

  The filter 54 is a circuit that gives a delay time to an input signal and outputs the same as in the delay element 50 included in the sub-computer 20 according to the first embodiment. FIG. FIG. The filter 54 includes a capacitor 61 connected between the input terminal 63 and the ground, and a resistance element 62 connected between the input terminal 63 and the output terminal 64. The input terminal 63 of the filter 54 is connected to the output terminal of the selector 56, and the output terminal 64 of the filter 54 is connected to the input terminal of the selector 57.

  One input terminal of the selector 56 is connected to the output terminal Q of the update prohibition register 26, and the other input terminal of the selector 56 is connected to the terminal 206. One output terminal of the selector 57 is connected to the input terminal of the AND gate 52, and the other output terminal of the selector 57 is connected to the CPU 40 and the like.

In phase for transmitting data to the main computer 10 from the sub-computer 20A, the selector 56 switches the connection of the update prohibition signal S _F which is outputted from the update disable register 26 to supply to the filter 54, the selector 57, the filter 54 switch the connection to update prohibition signal S _F which delay time is assigned to be supplied to supply the aND gate 52 from.

  On the other hand, in the phase in which the sub computer 20A receives the data supplied from the main computer 10, the selector 56 switches the connection so that the data signal SDA supplied via the I2C bus 302 is supplied to the filter 54. 57 switches the connection so that the data signal SDA supplied from the filter 54 is supplied to the CPU 40.

Filter 54, when the update prohibition signal S _F via the selector 56 is input, it acts to impart a delay time to update inhibiting signal S _F. On the other hand, when the data signal SDA is input through the selector 56, the filter 54 acts to remove spike noise included in the data signal SDA.

The sub computer 20 </ b> A further includes a filter 55 having the same configuration as the filter 54. The filter 55 has an input terminal connected to the terminal 205 and an output terminal connected to the CPU 40 and the like. The filter 55 plays a role of removing spike noise included in the communication clock signal SCL supplied from the main computer 10 via the I2C bus 302. In this embodiment, the filter 54 to the data signal SDA are inputted, is exemplified the configuration to be used as a delay circuit for imparting a delay time to update inhibiting signal S _F, the filter 55 of the communication clock signal SCL is input it may be configured to be used as a delay circuit for imparting a delay time to update inhibiting signal S _F. The filter 54 is an example of a delay circuit in the present invention, and the selector 56 is an example of a selection unit in the present invention.

According to the sub computer 20A according to the second embodiment of the present invention, the same effect as that of the sub computer 20 according to the first embodiment can be obtained. Further, by using a filter 54 which is provided in order to remove the spike noise contained in the signal inputted to the sub computer 20 through the I2C bus 302, since a structure which imparts a delay time to update inhibiting signal S _F It is not necessary to separately provide a delay circuit. That is, according to the sub computer 20A according to the second embodiment, it is possible to suppress an increase in circuit area due to the installation of the delay circuit.

In each of the above-described embodiments, the update prohibition signal _{SF is set} to a low level when the determination unit 25 determines that the read address and the write address match, but the present invention is limited to this mode. is not. For example, when a read address is designated in the address generator 24, the read address regardless of whether it matches the writing address, update prohibition signal S _F may be used as the low level. That is, when data is read from the input stage register 31a or 31b, the update prohibition signal _SF is set to the low level regardless of whether data is written to the same input stage register. Transition.

Further, in the above embodiment, the data update control unit 30a and 30b, when the update prohibition signal S _F is the address of the input stage register and the read address exhibited low level indicating an update prohibition data corresponding to itself In the above example, the update of data in the input stage register is prohibited, but the present invention is not limited to this mode. For example, the data update control unit 30a and 30b, when the update prohibition signal S _F exhibits a low level indicating an update prohibition data, regardless of whether or not the address of the input stage register read address corresponding to itself Instead, the update of data in the input stage register corresponding to itself may be prohibited. In this case, update prohibition signal S _F is, when exhibiting low level indicating an update prohibition data, update data is prohibited in both the input stage registers 31a and 31b.

Further, in the above embodiment, update prohibition signal S _F is prohibits updating of data in the input stage registers 31a and 31b when exhibiting low level, the input stage register if an update prohibition signal S _F exhibits a high level Although the case where the update of the data in 31a and 31b is permitted was illustrated, it is not limited to this mode. That is, the assignment of functions to the signal level of the update prohibition signal S _F may be contrary to the above.

Further, in the above embodiment, a case has been exemplified where the reset signal S _R resets the update disable register 26 when a transition to a low level, updated prohibited when the reset signal S _R is shifted to a high level register 26 May be reset.

Further, in the above embodiment, a case has been exemplified that the calculation result of the logical product of the output signal and the chip select signal SCS of the delay element 50 or the filter 54 and the reset signal S _R, the delay element 50 or the filter 54 it may be used an output signal as a reset signal S _R.

Further, in the above embodiment, in the case of prohibiting updating of the data in the input stage registers 31a and 31b, the data update control unit 30a and 30b is continuously sensing data D _A and D _B of the update prohibition previous input stage Although the case where it supplies to the registers | resistors 31a and 31b was illustrated, it is not limited to this aspect. When updating of data in the input stage registers 31a and 31b is prohibited, the output of the sensors 12a and 12b may be controlled to stop, or the supply of the clock signal C _X to the input stage registers 31a and 31b may be stopped. May be.

DESCRIPTION OF SYMBOLS 10 Main computer 12a, 12b Sensor 20 Sub computer 26 Update prohibition register 30a, 30b Data update control part 31a, 31b Input stage register 50 Delay element 52 AND gate 54 Filter 56 Selector 100 Data communication system

Claims (5)

A first storage unit in which data writing and reading are performed asynchronously;
When reading data from the first storage unit, the update of data stored in the first storage unit is prohibited, and the update of data stored in the first storage unit is prohibited Control means for performing control to cancel the prohibition of update of data stored in the storage unit after a predetermined period of time;
A semiconductor device including: The semiconductor device according to claim 1, wherein the control unit includes a circuit that defines the predetermined period from prohibiting update of data stored in the first storage unit to canceling the prohibition. The first storage unit is provided corresponding to each of a plurality of bits constituting the data, and captures and holds a value of a corresponding bit among the plurality of bits in synchronization with a first clock signal. The semiconductor device according to claim 1, further comprising: a plurality of registers. A second storage unit that captures the data stored in the first storage unit based on a second clock asynchronous with the first clock signal;
The said control means prohibits the update of the data memorize | stored in the said 1st memory | storage part, when taking in the data memorize | stored in the said 1st memory | storage part in the said 2nd memory | storage part. Semiconductor device. The semiconductor device according to claim 4, wherein the second storage unit includes a plurality of registers corresponding to each of the plurality of registers constituting the first storage unit.