JP2002093173A - Synchronous multi-port memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous multi-port memory which can prevent erroneous read-out. SOLUTION: Write-in operation of a write-in port is prohibited during read- out operation of a read-out port by giving an inversion signal of a read-out clock signal CLK-R instead of a write-in clock signal CLK-W to a NAND circuit 31 controlling a write-in word line WORD-W, a NAND circuit 33 controlling a write-in column selecting line COL-W, and write-in drivers WDL and WDR driving respectively write-in bit lines BIT-W and /BIT-W.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronous multiport memory, and more particularly, to a synchronous multiport memory having a read port and a write port that operate in synchronization with a clock signal.

[0002]

2. Description of the Related Art Multiport memories having a plurality of input / output ports are used for various purposes. For example, in graphics applications, a buffer memory is used which changes the transfer speed and bit width while reading data to be displayed from a video memory and supplies the data to a monitor control circuit. This is a dual port memory having a write port for writing data from a video memory and a read port for reading data to a monitor control circuit. This memory is
Since there is one read port (R) for reading only and one write port (W) for writing only,
-R / 1-W memory. Also, a memory called a color palette for graphics use has a read / write port (RW) for exchanging data with the MPU and a read port (R) for passing data to the monitor control circuit.
It is called 1-RW / 1-R memory. As described above, when data is transmitted and received between devices having different operation speeds and bit widths, a memory serving as a buffer is required, and the multi-port memory is used. Generally, the ports operate asynchronously, that is, operate in synchronization with different clock signals.

FIG. 9 shows a main circuit configuration of a 1-R / 1-W memory having the simplest configuration among multiport memories.
The 1-R / 1-W memory has a static memory cell MC. Here, as a read port, a read word line WORD_R and a read bit line pair BIT_R, / B
IT_R, read row decoder XDEC_R, read column select gate CSG_R, read column select line COL_R,
A read column decoder YDEC_R, a read address latch circuit ALAT_R, a sense amplifier SA, a read data latch circuit DLAT_R, and the like are provided. As write ports, a write word line WORD_W, a write row decoder XDEC_W, a write bit line pair BIT_W, / BIT_
W, write column select gate CSG_W, write column select line COL_W, write column decoder YDEC_W, write address latch circuit ALAT_W, write driver WDL
And WDR, a write data latch circuit DLAT_W, and the like.

[0004] Access from the read port is performed as follows. The read port is a read clock signal CLK_R
Works in sync with. At the rising edge of read clock signal CLK_R, read address signal ADD_R is latched by read address latch circuit ALAT_R, and read row decoder XDEC_R and read column decoder YDEC are read.
_R, thereby decoding one read word line W
ORD_R and one column selection line COL_R are selected. When the read word line WORD_R is selected, a data signal is sent from the memory cell MC to the read bit line pair BIT_R.
R and / BIT_R, and the potential difference is amplified by the sense amplifier SA. The data signal output from sense amplifier SA is latched by read data latch circuit DLAT_R at the next rising edge of read clock signal CLK_R, and output as data signal Dout.

On the other hand, access from the write port is performed as follows. The write port is the write clock signal CL
It operates in synchronization with K_W. Write clock signal CLK_
At the rising edge of W, write address signal ADD_W and data signal Din are applied to write address latch circuit ALAT_W and write data latch circuit DLAT_W, respectively.
Latched. Latched write address signal ADD
_W is decoded by a write row decoder XDEC_W and a write column decoder YDEC_W, and one write word line WORD_W and one write column selection line COL
_W is selected. Also, the latched data signal Di
Write bit line pair BIT_W, / BIT_W is driven by write drivers WDL and WDR according to n, whereby data signal Din is written to memory cell MC.

In the above-described synchronous multiport memory,
Each port takes in an address signal and performs a read or write operation when a corresponding clock signal is at an H (logic high) level. When the clock signal is at the L (logic low) level, all word lines and column select lines are deselected, and the write driver is deactivated. During this period,
The bit line pair is precharged to a power supply level by a precharge circuit (not shown) to prepare for the next operation.

[0007]

However, the above-mentioned conventional multiport memory has the following problems. As the processing dimensions of the semiconductor integrated circuit become finer, the distance between the read bit line pair BIT_R, / BIT_R and the write bit line pair BIT_W, / BIT_W also becomes smaller. Accordingly, parasitic capacitance between wirings increases. During writing, one of the write bit lines BIT_W or / BIT_W is rapidly discharged from the power supply potential to the ground potential, so that a large noise is induced in the read bit line BIT_R or / BIT_R adjacent thereto. At the time of reading, since the potential change of read bit line pair BIT_R, / BIT_R is very small, correct data is read when noise is superimposed on read bit line pair BIT_R, / BIT_R from write bit line pair BIT_W, / BIT_W. Can not be done. When data is written to a memory cell in the same or adjacent column as the memory cell MC while a certain memory cell MC is being read, the probability of erroneous reading is highest.

Generally, in a multiport memory, there is no regulation to restrict the operation between ports. Therefore, as shown in FIG. 10, the rising edge of read clock signal CLK_R may overlap the rising edge of write clock signal CLK_W even when the read port and the write port operate asynchronously with each other. In this case, the read operation R and the write operation W occur simultaneously, and an erroneous read occurs depending on the combination of the read address signal ADD_R and the write address signal ADD_W.

Japanese Patent Laid-Open Publication No. Sho 64-19581 has a read port and a write port. When the read address and the write address are the same, for example, the read operation is performed in the first half of one cycle, and the write operation is performed in the second half. A two-port memory is described in which an erroneous read is prevented by performing a read operation. This two-port memory is asynchronous,
This publication does not describe a synchronous multiport memory that performs a read operation and a write operation in synchronization with a clock signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a synchronous multiport memory capable of preventing erroneous reading.

[0011]

A multiport memory according to the present invention includes a memory cell, a read port, a write port, and write inhibit means. The read port reads a data signal from a memory cell in synchronization with a read clock signal. The write port writes a data signal to a memory cell in synchronization with a write clock signal. The write inhibit means inhibits the write operation of the write port during the read operation of the read port. Preferably, the write inhibit means is synchronized with a read clock signal.

[0012] More preferably, the write port includes a write address latch circuit and a write data latch circuit. The write address latch circuit takes in the write address signal in synchronization with the write clock signal. The write data latch circuit takes in the data signal in synchronization with the write clock signal.

In the multiport memory, the write operation of the write port is prohibited during the read operation of the read port, so that the write operation of the write port does not affect the read operation of the read port. As a result, erroneous reading can be prevented.

Preferably, a common clock signal is provided as the read clock signal and the write clock signal.

More preferably, the read port includes a read address latch circuit for taking in a read address signal in synchronization with a common clock signal. The write port includes a write address latch circuit and a write data latch circuit. The write address latch circuit takes in a write address signal in synchronization with a common clock signal. The write data latch circuit takes in a data signal in synchronization with a common clock signal.

In the multiport memory, the read port and the write port operate alternately in synchronization with a common clock signal. As a result, the write operation of the write port is inhibited during the read operation of the read port by using one clock signal, whereby erroneous read can be prevented.

Preferably, the write inhibit means inhibits the write operation of the write port for a predetermined period from the start of the read operation of the read port.

More preferably, the write port includes a write data latch circuit, a write bit line, and a write driver. The write data latch circuit takes in the data signal in synchronization with the write clock signal. The write bit line is connected to a memory cell. The write driver drives a write bit line in response to a data signal taken into a write data latch circuit. The write inhibit means inhibits the operation of the write driver for a predetermined period from the start of the read operation of the read port.

In the above multi-port memory, the write operation of the write port is prohibited for a predetermined period from the start of the read operation of the read port. Therefore, even if the frequency of the write clock signal is higher than the frequency of the read clock signal, erroneous reading is performed. Can be prevented.

Preferably, the write port is a read / write port for reading a data signal from a memory cell as well as writing a data signal to the memory cell. The write inhibit means inhibits the write operation of the read / write port only during the write operation of the read / write port.

In the above multi-port memory, the write operation of the read / write port is prohibited only during the write operation of the read / write port, so that the read operation of the read / write port is not interrupted. The read operation can be completed within a predetermined period.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] Referring to FIG. 1, a dual-port memory according to a first embodiment of the present invention has 1-R / 1-W having one read port and one write port.
Memory. This dual-port memory includes a plurality of memory cells MC arranged in a matrix and a plurality of read and write word lines WO arranged in a row (row).
RD_R and WORD_W, and a plurality of read / write bit line pairs BIT_R, / B arranged in columns
IT_R and BIT_W, / BIT_W, and read and write bit line pairs BIT_R, / BIT_R and BI
A plurality of read and write column select gates CSG_R and CSG_W corresponding to T_W, / BIT_W, a plurality of read column select lines COL_R corresponding to a plurality of read column select gates CSG_R, and a plurality of write column select gates CSG_W Write column select lines CO
L_W, a read address latch circuit ALAT_R that takes in the read address signal ADD_R in synchronization with the read clock signal CLK_R, a write address latch circuit ALAT_W that takes in the write address signal ADD_W in synchronization with the write clock signal CLK_W, Read clock signal CLK_
A read data latch circuit DLAT_R for outputting a data signal Dout in synchronization with R, and a write clock signal CLK_
A write data latch circuit DLAT_W for inputting a data signal Din in synchronization with W, and a read address latch circuit AL
A row decoder XDEC_R that decodes a part of the read address signal ADD_R taken into the AT_R and selects one read word line WORD_R, and decodes the rest of the read address signal ADD_R and one read column select line COL_R Read column decoder YDEC_
R and a part of the write address signal ADD_W taken into the write address latch circuit ALAT_W are decoded to 1
A write row decoder XDEC_W for selecting one write word line WORD_W, a write column decoder YDEC_W for decoding the rest of the write address signal ADD_W and selecting one write column select line COL_W, and a plurality of read operations A plurality of sense amplifiers SA corresponding to the bit line pairs BIT_R and / BIT_R, and a plurality of write bit lines BIT_W
And a plurality of write drivers WD corresponding to a plurality of write bit lines / BIT_W.
R.

In FIG. 1, memory cell MC, read word line WORD_R, write word line WORD_W, read column select gate CSG_R, write column select gate S
CG_W, read column select line COL_R, write column select line COL_W, sense amplifier SA, write driver WD
Although only one L and one WDR are shown, a large number is actually arranged.

Each memory cell MC is a static memory cell, and includes a latch circuit composed of inverters 10 and 11, and four access transistors 12 to 15. Access transistor 12 is an N-channel MOS transistor, and is connected between one storage node of latch circuits (10, 11) and read bit line BIT_R,
Its gate is connected to read word line WORD_R.
Access transistor 13 is formed of an N-channel MOS transistor, and is connected between the other storage node of latch circuit (10, 11) and read bit line / BIT_R, and has its gate connected to read word line WORD_R. Access transistor 14 is formed of an N-channel MOS transistor, is connected between one storage node of latch circuits (10, 11) and write bit line BIT_W, and has its gate connected to write word line WORD_W. Access transistor 15 is formed of an N-channel MOS transistor, is connected between the other storage node of latch circuit (10, 11) and write bit line / BIT_W, and has its gate connected to write word line WORD_W. .

Each of write drivers WDL and WDR includes an inverter 20, a NOR circuit (negative logic) 21,
P channel MOS transistor 22 and N channel MO
And an S transistor 23. Write data latch circuit D
The output of LAT_W is directly connected to the input of write driver WDL, and connected to the input of write driver WDR via inverter 24. Therefore, write driver WDL drives write bit line BIT_W in response to data signal Din taken into write data latch circuit DLAT_W, and write driver WDR drives write data latch circuit DLA.
The write bit line / BIT_W is driven in response to an inverted signal of the data signal Din taken into T_W.

A decode signal output from read row decoder XDEC_R is supplied to read word line W via a gate circuit formed of NAND circuit 30 and inverter 34.
It is transmitted to ORD_R. Write row decoder XDEC_
The decode signal output from W is transmitted to write word line WORD_W via a gate circuit including NAND circuit 31 and inverter 35. The decode signal output from the read column decoder YDEC_R
The signal is transmitted to read column select line COL_R via a gate circuit formed of ND circuit 32. The decode signal output from the write column decoder YDEC_W is NAND
The signal is transmitted to write column select line COL_W via a gate circuit including circuit 33 and inverter 36.

The read clock signal CLK_R is connected to the NAND
In addition to the circuits 30 and 32,
0 to 42 to NAND circuits 31 and 33 and write drivers WDL and WDR.

Here, read word line WORD_R, read bit line pair BIT_R, / BIT_R, read column select gate CSG_R, read column select line COL_R, sense amplifier SA, read data latch circuit DLAT_R,
NAND circuits 30 and 32, inverter 34, read row decoder XDEC_R, read column decoder YDEC_
R and read address latch circuit ALAT_R constitute a read port for reading a data signal from memory cell MC in synchronization with read clock signal CLK_R. Further, a write word line WORD_W, a write bit line pair BIT_W,
/ BIT_W, write column select gate CSG_W, write column select line COL_W, write drivers WDL, WD
R, inverter 24, write data latch circuit DLAT_
W, NAND circuits 31, 33, inverters 35, 36,
Write row decoder XDEC_W, write column decoder Y
DEC_W and write address latch circuit ALAT_
W constitutes a write port for writing a data signal to memory cell MC in synchronization with write clock signal CLK_W. Then, inverters 40 to 42 output read clock signal CLK.
The write operation of the write port is prohibited during the read operation of the read port in synchronization with _R.

Next, the operation of the dual port memory configured as described above will be described with reference to the timing chart of FIG.

Access from the read port is performed as follows. At the rising edge of read clock signal CLK_R, read address signal ADD_R is latched by read address latch circuit ALAT_R, a part of which is decoded by read row decoder XDEC_R, and the rest is decoded by read column decoder YDEC_R. One read word line WO by read row decoder XDEC_R
RD_R is selected and the read column decoder YDEC_R
Selects one read column select line COL_R. More specifically, since NAND circuit 30 receives read clock signal CLK_R at H level, the decode signal at H level output from read row decoder XDEC_R is transmitted to read word line WORD_R. NA
ND circuit 32 also has an H level read clock signal CLK.
_R, the read column decoder YDEC_
The H-level decode signal output from R is inverted by NAND circuit 32 and transmitted to read column select line COL_R.

When read word line WORD_R goes high, access transistors 12 and 13 are turned on, data is read from memory cell MC, and a potential difference is generated between read bit lines BIT_R and / BIT_R. Since the read column select line COL_R is at the L level, the read column select gate CSG_R is on,
The potential difference is applied to the sense amplifier SA, where it is amplified. The data signal output from sense amplifier SA is latched by read data latch circuit DLAT_R at the next rising edge of read clock signal CLK_R, and output as data signal Dout.

As described above, read clock signal CLK_
When R is at H level, read operation R is performed.

On the other hand, access from the write port is performed as follows. At the rising edge of write clock signal CLK_W, write address signal ADD_W is latched by write address latch circuit ALAT_W, a part of which is decoded by write row decoder XDEC_W, and the rest is decoded by write column decoder YDEC_W. One write word line W is provided by the write row decoder XDEC_W.
ORD_W is selected and the write column decoder YDEC_
W selects one write column selection line COL_W. More specifically, an H-level decode signal output from write row decoder XDEC_W is applied to write word line W
ORD_W. Write column decoder YDEC
The H-level decode signal output from _W is transmitted to write column select line COL_W. However, here, N
AND circuits 31 and 33 receive write clock signal CLK_
It receives an inverted signal of the read clock signal CLK_R instead of W. Therefore, when read clock signal CLK_R is at L level, an H level decode signal output from write row decoder XDEC_W is applied to write word line WOR.
The H-level decode signal transmitted to D_W and output from write column decoder YDEC_W is transmitted to write column select line COL_W. Read clock signal CLK_
When R is at the H level, decode signals output from write row decoder XDEC_W and write column decoder YDEC_W are not transmitted to write word line WORD_W and write column select line COL_W.

At the rising edge of write clock signal CLK_W, externally input data signal Din is latched by write data latch circuit DLAT_W and applied to write driver WDL, and its inverted signal is written to write driver WDR. Given to. Write drivers WDL and WDR operate in response to an inverted signal of read clock signal CLK_R instead of write clock signal CLK_W. More specifically, when read clock signal CLK_R is H
When the level is at the level, P-channel MOS transistor 22 is turned on and N-channel MOS transistor 23 is turned off in each of write drivers WDL and WDR.
Therefore, write drivers WDL and WDR maintain write bit lines BIT_W and / BIT_W at the H level, respectively, regardless of the data signal latched by write data latch circuit DLAT_W. On the other hand, when read clock signal CLK_R is at L level, P channel MOS transistor 22 is turned off in each of write drivers WDL and WDR, and N channel MOS transistor 23
Turns on or off in response to the data signal latched by write data latch circuit DLAT_W. for that reason,
When the data signal latched by write data latch circuit DLAT_W is at L level, write driver WDL drives write bit line BIT_W to L level, and the data signal latched by write data latch circuit DLAT_W is at H level. When write driver WDR sets write bit line / BIT_W
To the L level. At this time, since the write word line is at the H level, access transistors 14 and 15 of memory cell MC are turned on. Therefore, the input data signal Din is written to memory cell MC.

As described above, the read clock signal CLK_
When R is at L level, read operation W is performed.

According to the first embodiment, the inverter 4
0 to 42 inhibit the write operation of the write port during the operation of the read port in synchronization with the read clock signal CLK_R. That is, even if write clock signal CLK_W attains H level while read clock signal CLK_R is at H level, write word line WORD_W and write column select line CO
L_W does not go to H level, and write drivers WDL and WDR do not drive write bit lines BIT_W and / BIT_W. Then, the read clock signal CLK_R becomes L
For the first time, the write word line WORD_W and the write column select line COL_W become H level, and the write drivers WDL and WDR apply the write bit line BIT_
Drive W and / BIT_W. Therefore, write operation W is not performed during read operation R, and erroneous read can be prevented.

[Second Embodiment] In the first embodiment, the read port synchronizes with the read clock signal CLK_R, the write port synchronizes with another write clock signal CLK_W independent of the read clock signal CLK_R, Both ports are operating asynchronously with each other.

On the other hand, in the second embodiment, as shown in FIG. 3, a common clock signal CLK is applied to the read port and the write port. Therefore, both ports operate in synchronization with clock signal CLK. As shown in the timing chart of FIG. 4, at the rising edge of clock signal CLK, read address signal ADD_R is latched by read address latch circuit ALAT_R, and write address signal AD_R is latched.
D_W is latched by the write address latch circuit ALAT_W, and a data signal Din input from the outside is latched by the write data latch circuit DLAT_W.

While the clock signal CLK is at the H level,
Read word line WORD_R goes high, and read column select line COL_R goes low. On the other hand, while clock signal CLK is at L level, write word line WOR
D_W goes high, and the write column select line COL_W
Becomes H level.

According to the second embodiment, read operation R is performed when clock signal CLK is at H level, and write operation W is performed when clock signal CLK is at L level. Similarly, erroneous reading can be prevented.

[Third Embodiment] In the first embodiment, the write port can perform the write operation only while read clock signal CLK_R is at L level. Therefore, when the frequency of write clock signal CLK_W is at least twice the frequency of read clock signal CLK_R, write clock signal CLK_W goes high again while waiting for read clock signal CLK_R to go low. , The next write address signal ADD_W is latched by the write address latch circuit ALAT_W, and the corresponding data signal Din is further latched by the write latch circuit DLAT_W.
W will be latched. A third embodiment described below aims at preventing such a writing failure.

In the third embodiment, as shown in FIG.
Write word line WORD_W, write column select line COL_
A clock pulse control circuit 50 for controlling W and write drivers WDL and WDR is provided. Clock pulse control circuit 50 includes a delay element (DL) 51, an inverter 52, NAND circuits 53 and 54, and an inverter 55. The delay element 51 receives the read clock signal C
LK_R is delayed by a predetermined period Δt. Delay element 5
1, the inverter 52 and the NAND circuit 53 form a one-shot circuit. Therefore, clock pulse control circuit 50 delays the rise of write clock signal CLK_W by a predetermined period Δt to write clock signal CLK_W.
Generates W2.

As shown in FIG. 6, in the first write operation W1, write clock signal CLK_W changes to read clock signal C
Since the clock rises at the same time as the rise of LK_R, write clock signal CLK_W2 rises with a delay of a predetermined period Δt from the rise of read clock signal CLK_R. In the next write operation W2, write clock signal CLK_W rises with a delay of at least a predetermined period Δt from the rise of read clock signal CLK_R, and thus write clock signal CLK_W2
Rises at the same time as the rise of write clock signal CLK_W.

According to the third embodiment, clock pulse control circuit 50 inhibits the write operation of the write port Δt for a predetermined period from the start of the read operation of the read port. If the potential difference between the read bit line pair BIT_R and / BIT_R is amplified sufficiently large by the sense amplifier SA within the predetermined period Δt, an erroneous read will occur even if the write operation of the write port starts during the read operation of the read port. Can be prevented.

[Fourth Embodiment] In the third embodiment described above, when a read operation is started during a write operation, the selected write word line WORD_W and write column select line COL_W are once disabled. After the elapse of a predetermined period Δt from the selection state, an operation of returning to the selection state again is performed. The cause of the erroneous read is the write bit line pair BIT_W, / BI
Since the potential of T_W greatly changes, the operation of only the write driver Δt may be prohibited for a predetermined period from the start of the read operation of the read port. Therefore, in the fourth embodiment, as shown in FIG. 7, write clock signal CLK_W2 output from clock pulse control circuit 52 is
DL and WDR, and write clock signal CLK_W is applied to NAND circuits 31 and 33 as in the conventional case.
Is given.

According to the fourth embodiment, clock pulse control circuit 50 inhibits the operation of only write drivers WDL and WDR for a predetermined period Δt from the start of the read operation of the read port, so that write word line WORD_W and write The column selection line COL_W does not operate unnecessarily, and noise generation and increase in power consumption can be minimized.

[Embodiment 5] Embodiments 1 to 5 described above.
4 is a 1-R / 1-W memory having a read-only read port and a write-only write port. On the other hand, the dual port memory according to the fifth embodiment is a 1-RW / 1-R memory having a read / write port for both reading and writing and a read port for reading only.

In the fifth embodiment, as shown in FIG.
The read / read operation corresponding to the above-described write clock signal CLK_W
Write clock signal CLK_RW is applied to write address latch circuit ALAT_W and write data latch circuit DLAT_
W. Here, similarly to the third embodiment, write clock signal CLK_W2 output from clock pulse control circuit 50 is applied to NAND circuits 31 and 33.
And write drivers WDL and WDR. In the fifth embodiment, unlike the third and fourth embodiments, a write enable signal WE is further applied to the NAND circuit 53 of the clock pulse control circuit 50.

Write clock signal CLK_ output from clock pulse control circuit 50 as in the third embodiment.
W2 is not only the write drivers WDL and WDR but also NA
Since it is also provided to ND circuits 31 and 33, write word line WORD_W and write column select line COL_W are deselected while the read / write port is performing the read operation, and the read operation is performed. Interrupted. Generally, a read operation requires a longer time than a write operation. This is because it takes a long time to amplify the minute potential difference between the read bit line pair BIT_R and / BIT_R. If the read operation is interrupted, it may not be possible to read correct data again in the remaining time. Erroneous reading occurs in the read-only read port when a write operation is performed from the read / write port. In order not to disturb the read operation of the read / write port, the write operation may be prohibited only when the write operation is performed from the read / write port.
Therefore, in the fifth embodiment, the write enable signal WE is supplied to the NAND circuit 53 of the clock pulse control circuit 50 as shown in FIG. Write enable signal WE is a signal for controlling a read / write port, and designates a read operation at L level and designates a write operation at H level. When write enable signal WE is at L level,
Read / write clock signal CLK_RW is directly output as write clock signal CLK_W2. On the other hand, when write enable signal WE is at H level, a write operation is performed, and clock pulse control circuit 50 operates as in the third embodiment.

According to the fifth embodiment, the clock pulse control circuit 50 inhibits the write operation of the read / write port only during the write operation of the read / write port. The read operation is not interrupted during the operation, and the read operation can be completed within a predetermined period.

It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0053]

According to the present invention, since the write operation of the write port is prohibited during the read operation of the read port, erroneous read can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main configuration of a dual port memory according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the dual port memory shown in FIG.

FIG. 3 is a circuit diagram showing a main configuration of a dual port memory according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of the dual port memory shown in FIG. 3;

FIG. 5 is a circuit diagram showing a main configuration of a dual port memory according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing an operation of the dual port memory shown in FIG.

FIG. 7 is a circuit diagram showing a main configuration of a dual port memory according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a main configuration of a dual port memory according to a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a main configuration of a conventional dual port memory.

10 is a timing chart showing an operation of the dual port memory shown in FIG.

[Explanation of symbols]

MC memory cell, WORD_R read word line, WO
RD_W Write word line, BIT_R, / BIT_R
Read bit line, BIT_W, / BIT_W Write bit line, CSG_R Read column select gate, COL_R
Read column select line, CSG_W Write column select gate, COL_W Write column select line, SA sense amplifier, WDL, WDR write driver, XDEC_R Read row decoder, XDEC_W Write row decoder, Y
DEC_R read column decoder, YDEC_W write column decoder, ALAT_R read address latch circuit, ALAT_W write address latch circuit, DLAT
_W Write data latch circuit, DLAT_R Read data latch circuit, CLK_W, CLK_W2 Write clock signal, CLK_R Read clock signal, Din, Do
out data signal, CLK clock signal, 50 clock pulse control circuit, CLK_RW read / write clock signal.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yakei Morishima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term in Mitsubishi Electric Corporation (reference) 5B015 HH01 JJ18 KB35 KB43 KB92 NN01 NN03

Claims (8)

[Claims] 1. A memory cell; a read port for reading a data signal from the memory cell in synchronization with a read clock signal; and a write port for writing a data signal to the memory cell in synchronization with a write clock signal. A write-inhibiting means for inhibiting a write operation of the write port during a read operation of the read port. 2. The synchronous multiport memory according to claim 1, wherein said write inhibit means is synchronized with said read clock signal. 3. A write address latch circuit for taking in a write address signal in synchronization with the write clock signal, and a write port for taking in a data signal in synchronization with the write clock signal. 3. The synchronous multiport memory according to claim 2, comprising a data latch circuit. 4. The synchronous multiport memory according to claim 1, wherein a common clock signal is provided as said read clock signal and said write clock signal. 5. The read port includes a read address latch circuit for taking in a read address signal in synchronization with the common clock signal, and the write port includes a write address in synchronization with the common clock signal. 5. The synchronous multiport memory according to claim 4, further comprising: a write address latch circuit for taking in a signal; and a write data latch circuit for taking in a data signal in synchronization with said common clock signal. 6. The synchronous multiport memory according to claim 1, wherein said write inhibit means inhibits a write operation of said write port for a predetermined period from a start of a read operation of said read port. 7. A write data latch circuit for taking in a data signal in synchronization with the write clock signal, a write bit line connected to the memory cell, and the write data latch A write driver for driving the write bit line in response to a data signal taken into the circuit, wherein the write inhibit means operates the write driver for a predetermined period from the start of the read operation of the read port. 7. The synchronous multiport memory according to claim 6, wherein 8. The write port is a read / write port that not only writes a data signal to the memory cell but also reads a data signal from the memory cell. 7. The synchronous multiport memory according to claim 6, wherein a write operation of said read / write port is inhibited only during a write operation of said write port.