CN109346511A - A kind of lateral resistance structure applied to power semiconductor - Google Patents
A kind of lateral resistance structure applied to power semiconductor Download PDFInfo
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- CN109346511A CN109346511A CN201811193725.1A CN201811193725A CN109346511A CN 109346511 A CN109346511 A CN 109346511A CN 201811193725 A CN201811193725 A CN 201811193725A CN 109346511 A CN109346511 A CN 109346511A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 13
- 239000011810 insulating material Substances 0.000 claims abstract description 6
- 230000000694 effects Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 description 11
- 230000002829 reductive effect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 230000000670 limiting effect Effects 0.000 description 6
- 230000002441 reversible effect Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 238000004220 aggregation Methods 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000009510 drug design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of lateral resistance structures applied to power semiconductor.The lateral resistance structure is the groove structure filled with insulating materials, the main knot edge of p-type of power semiconductor is arranged in the groove structure, and electrode metal is provided with one or more layers, run through the main knot of p-type in depth of groove, and extend setting length to the drift region N-, groove is interspersed between layers, the width of groove is arranged in the first setting range, the length of groove is arranged in the second setting range, and the spacing between the groove and groove in same layer is arranged in third setting range.Lateral resistance structure provided by the invention is capable of increasing the pressure drop effect of lateral resistance, reduces the additional area of chip, improves the utilization rate of chip.
Description
Technical field
The present invention relates to power semiconductor fields, more particularly to a kind of transverse direction applied to power semiconductor
Electric resistance structure.
Background technique
Power semiconductor under high-voltage great-current environment can be sent out by taking power diode as an example in the main knot edge of p-type
Raw lateral hole injection, to store excessive carrier, i.e. excess holes in the drift region N-.This is easy for causing in height
In the snap back recovery process for pressing high current, has many excess holes and preferentially gather main knot edge from side, then lead to
Anode region is crossed to take away.This is readily formed current convergence, even electric current threading, and device is caused to burn.To alleviate this problem,
In the prior art, it will usually a lateral resistance area is introduced in main knot edge, specific practice is: will be received in positive contact hole,
Sufficiently long range is flowed out between main knot side and contact hole, the p type island region in this distance range is exactly so-called laterally electricity
Area is hindered, sees Fig. 1.For silicon materials power diode, 3.3kV device is such as manufactured using the prior art, generally transverse resistance area is wide
Degree needs up to a hundred to hundreds of microns.After introducing lateral resistance area, when diode forward conduction, the sideways sky of main knot marginal flow
Cave electric current can generate lateral pressure drop in resistance area, form self-biasing effect, and then reduce edge P-N junction bias and corresponding
(dotted arrow show forward conduction process hole path schematic diagram in Fig. 1) is injected in hole.Self-biasing effect is stronger, then laterally
Inject fewer, the excess holes of aggregation back are fewer when Reverse recovery, therefore, in main knot when can sufficiently alleviate Reverse recovery
Current convergence at edge-corner.On the other hand, in reversely restoring process, when direction and forward conduction phase are flowed through in resistance area
When anti-transient state hole current, self-biasing effect also will form, can reduce reverse biased at main knot edge-corner and corresponding
Electric field strength, see Fig. 2 (dotted arrow show reversely restoring process hole path schematic diagram in Fig. 2).Likewise, for exhausted
Edge grid bipolar junction transistor (Insulated Gate Bipolar Transistor, IGBT), due to IGBT under conducting state not
There are the lateral injections of excess carriers, so there is no laterally inject excess carriers to lateral resistance for IGBT device
Inhibiting effect.But in IGBT turn off process, a large amount of excess holes for being stored in the drift region N- of main knot adjacent edges will
The main knot of p-type is first gathered, is then extracted by emitter electrode, and the automatic bias that lateral resistance is formed can be very good to inhibit p-type
The aggregation of the excess holes at main junction edge reduces reverse biased and corresponding electric field strength at the main knot edge-corner of p-type,
Turn off process mechanism is similar with the diode reverse recovery process discussed before, repeats no more.So lateral resistance area is in main knot
Edge not only reduces current density, but also reduces electric field strength, is very beneficial for improving the overcurrent of device under severe conditions
Turn-off capacity improves its robustness and reliability.So the rational design in lateral resistance area is very crucial.If the area Zhu Jie P is mixed
Miscellaneous concentration is higher, to realize sufficiently large lateral resistance, it is necessary to obtain the width design in lateral resistance area very big, ultimately cause
The waste of chip area.
Summary of the invention
The object of the present invention is to provide a kind of lateral resistance structures applied to power semiconductor, are capable of increasing transverse direction
The pressure drop effect of resistance inhibits the main knot edge current concentration phenomenon of power semiconductor reversely restoring process, reduces chip
Additional area, improves the utilization rate of chip.
To achieve the above object, the present invention provides following schemes:
A kind of lateral resistance structure applied to power semiconductor, the lateral resistance structure setting is in the power
The main knot edge of the p-type of semiconductor devices, the lateral resistance structure are groove structure.
Optionally, the main knot of p-type is run through in the depth of groove of the lateral resistance structure.
Optionally, the main knot of p-type is run through in the depth of groove of the lateral resistance structure, and extends setting length to the drift region N-
Degree.
Optionally, the length that sets is 0.8-1.5 μm.
Optionally, insulating materials is filled in the groove of the lateral resistance structure.
Optionally, the groove structure is provided with one or more layers around electrode metal, and every layer includes one or more recessed
Slot.
Optionally, the width of the groove is arranged in the first setting range, and the length setting of the groove is set second
Determine in range.
Optionally, the spacing between the groove and groove in same layer is arranged in third setting range.
Optionally, the groove between adjacent layer is interspersed.
The specific embodiment provided according to the present invention, the invention discloses following technical effects: application provided by the invention
In the lateral resistance structure of power semiconductor, the main knot etching edge of p-type formed it is multiple in depth through the main knot
Groove structure with insulating materials filling, and these grooves are interspersed.Due to depositing for multiple groove structures being interspersed
When electric current flows through the region the main knot electricity of p-type will be reached from the main knot edge of p-type along the passage flow between groove, electric current
The distance that pole metal flows through is increased, and due to electric current can the gap location between slot and slot assemble to form biggish electric current,
To produce bigger lateral pressure drop, therefore achieve the effect that increase lateral resistance.It realizes in identical lateral resistance area
Under width conditions, has the effect of bigger lateral resistance value, and under identical lateral resistance value, lateral resistance area can be with
It is made narrower effect, the additional area of chip is reduced, improves the utilization rate of chip.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without any creative labor, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the power diode forward conduction process hole path schematic diagram of prior art manufacture；
Fig. 2 is the power diode reversed turn off process hole path schematic diagram of prior art manufacture；
Fig. 3 is main view of the lateral resistance structure of the present invention in power semiconductor；
Fig. 4 is the first top view of lateral resistance structure in power semiconductor of the invention；
Fig. 5 is top view of second of the lateral resistance structure of the invention in power semiconductor；
Fig. 6 is 3-D view of second of the lateral resistance structure of the invention in power semiconductor；
Fig. 7 is main view of the lateral resistance structure of the present invention in high voltage power diode；
Fig. 8 is main view of the lateral resistance structure of the present invention in punch IGBT；
Fig. 9 is main view of the lateral resistance structure of the present invention in non-punch through IGBT.
1- lateral resistance area, 2- electrode metal, 3- oxide layer, 4- groove, the main knot edge 5-, in 701- diode structure
The drift region N-, the field oxide in 702- diode structure, the field limiting ring in 703- diode structure, in 704- diode structure
Groove, the DOPOS doped polycrystalline silicon for doing field plate in 705- diode structure, in 706- diode structure for isolation dioxy
SiClx layer, the anode metal in 707- diode structure, the passivation layer in 708- diode structure, 709- diode p type anode,
The cathodic region 710- diode N+, 711- diode cathode electrode, the active area in 712- diode structure, 713- diode structure
In lateral resistance area, the termination environment in 714- diode structure, the drift region N- in 801- punch IGBT, 802- punch
Gate oxide in IGBT, the field oxide in 803- punch IGBT, the p-type base area in 804- punch IGBT, 805- are worn
Field limiting ring in flow-through IGBT, the N+ emitter region in 806- punch IGBT, the groove in 807- punch IGBT, 808- break-through
The DOPOS doped polycrystalline silicon for doing gate electrode in type IGBT, the DOPOS doped polycrystalline silicon for doing field plate in 809- punch IGBT, 810- are worn
The silicon dioxide layer for isolation in flow-through IGBT, the emitter electrode metal in 811- punch IGBT, 812- punch
Passivation layer in IGBT, the N buffer layer in 813- punch IGBT, the P+ collector in 814- punch IGBT, 815- break-through
Collector electrode metal in type IGBT, the active area in 816- punch IGBT, the lateral resistance in 817- punch IGBT
Area, the termination environment in 818- punch IGBT, the drift region N- in 901- non-punch through IGBT, in 902- non-punch through IGBT
Gate oxide, the field oxide in 903- non-punch through IGBT, the p-type base area in 904- non-punch through IGBT, the non-break-through of 905-
The N+ emitter region in field limiting ring, 906- non-punch through IGBT in type IGBT, the groove in 907- non-punch through IGBT, 908- are non-
The DOPOS doped polycrystalline silicon for doing field plate in the DOPOS doped polycrystalline silicon for doing gate electrode, 909- non-punch through IGBT in punch IGBT,
In 910- non-punch through IGBT for isolation silicon dioxide layer, the emitter electrode metal in 911- non-punch through IGBT,
The P+ collector in passivation layer, 913- non-punch through IGBT in 912- non-punch through IGBT, in 914- non-punch through IGBT
Collector electrode metal, the active area in 915- non-punch through IGBT, the lateral resistance area in 916- non-punch through IGBT, 917-
Termination environment in non-punch through IGBT.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The object of the present invention is to provide a kind of lateral resistance structures applied to power semiconductor, are capable of increasing transverse direction
The pressure drop effect of resistance inhibits the main knot edge current concentration phenomenon of power semiconductor reversely restoring process, reduces chip
Additional area, improves the utilization rate of chip.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
As shown in figure 3, lateral resistance structure of the invention is groove structure, run through the main knot of p-type in depth of groove, and to N-
Drift region extends setting length, and setting length can be 0.8-1.5 μm, and groove is filled with insulating materials.As shown in Figure 4,5, 6,
For lateral resistance structure setting at the main knot edge of p-type of the power semiconductor, lateral resistance structure is around electrode metal
One or more layers groove being arranged is interspersed between the groove in layer and layer, moreover, the spacing between the groove in same layer is set
It sets in the first setting range, the width of groove is arranged in the second setting range, and the length setting of groove sets model in third
In enclosing.Lateral resistance value size is determined by groove in the width length that the position distribution and groove of the main knot of p-type are set.
According to actual needs, the size that the lateral resistance value is set around the settable multi-layer groove of electrode metal, can also
Lateral resistance size is adjusted by the setting wide length of groove.Based on above-mentioned high-voltage power device structure type, the present invention provides
The embodiment of one power diode structure and two IGBT.
Embodiment one:
As shown in fig. 7,701 doping concentration of the drift region N- of the present embodiment mesohigh power diode structure is 1e13-
5e13, thickness 200-250um (of different sizes according to pressure resistance).P type anode 709 main junction depth 5-6um, surface dopant concentration 1e18-
5e18, 704 constructional depth of groove need to through the main knot 709 of entire p type anode and extending downwardly 0.8-1.5um, terminal structure be with
The p-type field limiting ring 703 of floating field plate 705.Simulation result shows in the case where obtaining lateral resistance value same as the prior art, this
The lateral resistance sector width of invention can be reduced to original 55-75%.The structure is greatly reduced lateral resistance sector width.
Embodiment two:
As shown in figure 8,814 surface dopant concentration of P+ collecting zone of punch IGBT structure is 5e in the present embodiment18-
1e19, 813 doping concentration of the buffer area N is 1e15-5e15, 801 doping concentration of the drift region thickness 15-25um, N- is 1e13-5e13, thick
Spend 300-350um (root is of different sizes in pressure resistance), 802 thickness 0.08-0.12um of gate oxide, 804 junction depth 4- of P+ type base area
6um, surface dopant concentration 1e17-5e18.807 depth of groove need to run through entire P+ type base area 804 and extend downwardly 0.8-1.5um,
For DOPOS doped polycrystalline silicon as gate electrode 808, terminal structure is the p-type field limiting ring 805 with contact field plate 809.Simulation result table
Bright, in the case where obtaining lateral resistance value same as the prior art, lateral resistance sector width of the invention can be reduced to original
25-85%, which is greatly reduced lateral resistance sector width.
Embodiment three:
As shown in figure 9,901 doping concentration of the drift region N- of non-punch through IGBT structure is 1e in the present embodiment13-5e13,
Thickness 350-450um (root is of different sizes in pressure resistance).902 thickness 0.08-0.12um of gate oxide, 904 surface doping of p-type base area
Concentration 8e17-1e19, 906 surface dopant concentration 1e of N+ emitter20-6e20, 907 depth of groove structure need to run through the entire base area P+
904 and 0.8-1.5um is extended downwardly, DOPOS doped polycrystalline silicon emits collector 911,913 table of P+ collecting zone as gate electrode 908
Face doping concentration is 1e18-5e18, terminal structure is the p-type field limiting ring 905 with contact field plate 909.Simulation result shows
It obtains under lateral resistance value same as the prior art, lateral resistance sector width of the invention can be reduced to original 25-
85%, which is greatly reduced lateral resistance sector width.
Lateral resistance structure provided by the invention applied to power semiconductor is formed more in the main knot etching edge of P
A groove structure for running through the main knot in longitudinal direction, and these grooves are filled and are interspersed by insulating materials.Due to multiple
The presence for the groove structure being interspersed, electric current will be along the passage flows between slot when flowing through the region, and electric current is from the main knot of P
Edge reaches the distance that flows through of the main junction electrode metal of P and is increased, and since electric current can gap location aggregation between slot and slot
Biggish electric current is formed, to generate bigger lateral pressure drop, therefore achievees the effect that increase lateral resistance.It realizes identical
Lateral resistance sector width under the conditions of, have the effect of bigger lateral resistance value, and under identical lateral resistance value, it is horizontal
It can be made narrower effect to resistance area, the additional area of chip is reduced, improve the utilization rate of chip.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
Used herein a specific example illustrates the principle and implementation of the invention, and above embodiments are said
It is bright to be merely used to help understand method and its core concept of the invention；At the same time, for those skilled in the art, foundation
Thought of the invention, there will be changes in the specific implementation manner and application range.In conclusion the content of the present specification is not
It is interpreted as limitation of the present invention.
Claims (9)
1. a kind of lateral resistance structure applied to power semiconductor, which is characterized in that the lateral resistance structure setting
At the main knot edge of the p-type of the power semiconductor, the lateral resistance structure is groove structure.
2. lateral resistance structure according to claim 1, which is characterized in that in the depth of groove of the lateral resistance structure
Through the main knot of p-type.
3. lateral resistance structure according to claim 2, which is characterized in that in the depth of groove of the lateral resistance structure
Extend setting length through the main knot of p-type, and to the drift region N-.
4. lateral resistance structure according to claim 3, which is characterized in that the length that sets is 0.8-1.5 μm.
5. lateral resistance structure according to claim 1, which is characterized in that filled in the groove of the lateral resistance structure
There is insulating materials.
6. lateral resistance structure according to claim 1-5, which is characterized in that the groove structure surrounds electrode
Metal is provided with one or more layers, and every layer includes one or more grooves.
7. lateral resistance structure according to claim 6, which is characterized in that the width setting of the groove is in the first setting
In range, the length of the groove is arranged in the second setting range.
8. lateral resistance structure according to claim 6, which is characterized in that the spacing between groove and groove in same layer
It is arranged in third setting range.
9. lateral resistance structure according to claim 6, which is characterized in that the groove between adjacent layer is interspersed.
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| CN201811193725.1A CN109346511A (en) | 2018-10-15 | 2018-10-15 | A kind of lateral resistance structure applied to power semiconductor |
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| CN201811193725.1A CN109346511A (en) | 2018-10-15 | 2018-10-15 | A kind of lateral resistance structure applied to power semiconductor |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100230745A1 (en) * | 2009-03-16 | 2010-09-16 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN105981173A (en) * | 2014-02-10 | 2016-09-28 | 丰田自动车株式会社 | Semiconductor device and manufacturing method for semiconductor device |
| CN108133965A (en) * | 2018-01-30 | 2018-06-08 | 无锡新洁能股份有限公司 | A kind of power semiconductor of deep trench and preparation method thereof |
-
2018
- 2018-10-15 CN CN201811193725.1A patent/CN109346511A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100230745A1 (en) * | 2009-03-16 | 2010-09-16 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN105981173A (en) * | 2014-02-10 | 2016-09-28 | 丰田自动车株式会社 | Semiconductor device and manufacturing method for semiconductor device |
| CN108133965A (en) * | 2018-01-30 | 2018-06-08 | 无锡新洁能股份有限公司 | A kind of power semiconductor of deep trench and preparation method thereof |
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Application publication date: 20190215 |