CN109326645B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN109326645B
CN109326645B CN201810837206.8A CN201810837206A CN109326645B CN 109326645 B CN109326645 B CN 109326645B CN 201810837206 A CN201810837206 A CN 201810837206A CN 109326645 B CN109326645 B CN 109326645B
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CN109326645A (zh
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廖志腾
陈志山
邱意为
郑志玄
翁子展
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括在衬底上形成鳍结构，其中鳍结构包括第一鳍有源区；第二鳍有源区；以及将第一鳍有源区与第二鳍有源区分隔开的隔离部件；在第一鳍有源区上形成第一栅极堆叠件，并且在第二鳍有源区上形成第二栅极堆叠件；以及通过第一干蚀刻对第一鳍有源区的第一源极/漏极区实施第一凹进工艺；实施第一外延生长以在第一源极/漏极区上形成第一源极/漏极部件；实施鳍侧壁拉回(FSWPB)工艺以去除第二鳍有源区上的介电层；以及实施第二外延生长以在第二鳍有源区的第二源极/漏极区上形成第二源极/漏极部件。本发明的实施例还涉及半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及半导体器件及其制造方法。
背景技术
半导体集成电路(IC)行业经历了指数式增长。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代都具有比上一代更小和更复杂的电路。在IC演化过程中，功能密度(即，每芯片面积的互连器件的数量)通常增加，而几何尺寸(即，使用制造工艺可以创建的最小部件(或线))减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小也增加了处理和制造IC的复杂性。
为了通过增加栅极沟道耦合，减小截止状态电流和减小短沟道效应(SCE)来改进栅极控制，已经引入了多栅极器件。已经引入的一种这样的多栅极器件是鳍式场效应晶体管(FinFET)。FinFET的名称来源于从衬底延伸的鳍状结构，鳍状结构形成在衬底上并且用于形成FET沟道。FinFET与传统的互补金属氧化物半导体(CMOS)工艺兼容，并且它们的三维结构允许它们被积极地缩放，同时保持栅极控制和减轻SCE。通过实例的方式，FinFET制造工艺可以包括通过蚀刻和选择性外延生长形成外延生长的源极和漏极部件以具有应变效应。通过现有的方法形成的源极和漏极部件可以引起缺陷问题，诸如位错变化，并且降低器件性能。在一些情况下，由于相应的特定需求，不同地设计源极/漏极部件。现有的方法不能有效地形成具有相应的特性的各个源极和漏极部件。其它问题可以包括接触电阻。因此，需要的是解决上述问题的结构及其制造方法。
发明内容
本发明的实施例提供了一种制造半导体器件的方法，包括：在衬底上形成鳍结构，其中，所述鳍结构包括：第一鳍有源区；第二鳍有源区；以及将所述第一鳍有源区与所述第二鳍有源区分隔开的隔离部件；在所述第一鳍有源区上形成第一栅极堆叠件，并且在所述第二鳍有源区上形成第二栅极堆叠件；通过第一干蚀刻对所述第一鳍有源区的第一源极/漏极区实施第一凹进工艺；实施第一外延生长以在所述第一源极/漏极区上形成第一源极/漏极部件；实施鳍侧壁拉回(FSWPB)工艺以去除所述第二鳍有源区上的介电层；以及实施第二外延生长以在所述第二鳍有源区的第二源极/漏极区上形成第二源极/漏极部件。
本发明的另一实施例提供了一种半导体器件，包括：半导体衬底；第一鳍有源区和第二鳍有源区，从所述半导体衬底延伸；第一场效应晶体管，位于所述第一鳍有源区上；以及第二场效应晶体管，位于所述第二鳍有源区上，其中，所述第一场效应晶体管包括设置在所述第一鳍有源区的第一沟道区上的第一栅极堆叠件，以及设置在所述第一沟道区的相对侧上的第一外延生长的源极/漏极部件，所述第二场效应晶体管包括设置在所述第二鳍有源区的第二沟道区上的第二栅极堆叠件，以及设置在所述第二沟道区的相对侧上的第二外延生长的源极/漏极部件，以及所述第一外延生长的源极/漏极部件的底面低于所述第二外延生长的源极/漏极部件的底面。
本发明的又一实施例提供了一种制造半导体器件的方法，包括：在衬底上形成鳍结构，其中，所述鳍结构包括：第一鳍有源区；第二鳍有源区；以及将所述第一鳍有源区和所述第二鳍有源区分隔开的隔离部件；在所述第一鳍有源区上形成第一栅极堆叠件，并且在所述第二鳍有源区上形成第二栅极堆叠件；在所述第一栅极堆叠件和所述第二栅极堆叠件上形成介电层；通过第一干蚀刻对所述第一鳍有源区的第一源极/漏极区实施第一凹进工艺；实施第一外延生长以在所述第一源极/漏极区上形成第一源极/漏极部件；通过第二干蚀刻对所述第二鳍有源区的第二源极/漏极区实施第二凹进工艺；实施鳍侧壁拉回(FSWPB)工艺以去除所述第二鳍有源区上的所述介电层的部分；以及实施第二外延生长以在所述第二源极/漏极区上形成第二源极/漏极部件，其中，所述第一干蚀刻将所述第一鳍有源区凹进至第一深度；所述第二干蚀刻将所述第二鳍有源区凹进至第二深度；并且所述第二深度小于所述第一深度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1和图2是根据本发明的各个方面的制造工件的方法的流程图。
图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A和图13A是根据本发明的各个方面的制造工件的方法的各个制造阶段处的工件的顶视图。
图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B、图11B、图12B和图13B是根据本发明的各个方面的制造工件的方法的各个制造阶段处的沿着虚线AA’截取的工件的截面图。
图5C、图6C、图7C、图8C、图9C、图10C、图11C、图12C和图13C是根据本发明的各个方面的制造工件的方法的各个制造阶段处的沿着虚线BB’截取的工件的截面图。
图5D、图6D、图7D、图8D、图9D、图10D、图11D、图12D和图13D是根据本发明的各个方面的制造工件的方法的各个制造阶段处的沿着虚线CC’截取的工件的截面图。
图14A是根据本发明的各个方面的制造工件的方法的一个阶段处的工件的顶视图。
图14B、图14C、图14D、图14E和图14F是根据本发明的各个方面的分别沿着虚线AA’、BB’、CC’、DD’和EE’截取的图14A的工件的部分的截面图。
具体实施方式
以下发明内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不表示所讨论的各个实施例和/或配置之间的关系。
此外，在下面的本发明中形成另一部件上的、连接到另一部件和/或耦合到另一部件的部件可以包括其中部件形成为直接接触的实施例，并且还可以包括其中附加的部件可以形成在部件之间而使得部件可以不直接接触的实施例。此外，使用例如“下部”、“上部”、“水平”、“垂直”、“上面”、“上方”、“下方”、“之下”、“向上”、“向下”、“顶部”、“底部”等以及它们的衍生词(例如，“水平地”、“向下”、“向上地”等的空间相对术语以便于本发明描述一个部件与另一部件的关系。空间相对术语旨在覆盖包括部件的器件的不同定向。
应当注意的是，本发明呈现为多栅极晶体管或鳍式多栅极晶体管(在本文中称为FinFET器件)的形式。这样的器件可以包括P型金属氧化物半导体FinFET器件或N型金属氧化物半导体FinFET器件。FinFET器件可以是双栅极器件、三栅极器件、体器件、绝缘体上硅(SOI)器件和/或其它配置，本领域普通技术人员可认识到可以从本发明的各方面中受益的半导体器件的其它实施例。例如，如本文中所描述的一些实施例也可以应用于全环栅(GAA)器件、Omega-栅极(Ω栅)器件或Pi-栅极(Π栅极)器件。
本发明通常涉及半导体器件和制造。更具体地，一些实施例涉及形成源极和漏极部件，例如与器件鳍有源区一起。此外，公开的方法提供了形成具有增大的应变效应、减小的接触电阻的源极和漏极部件，并且还具有额外的自由来形成具有相应的特性的源极和漏极部件。在一些实例中，这些源极和漏极部件通过包括两步蚀刻的过程形成：第一蚀刻步骤蚀刻鳍以使源极和漏极区凹进；以及第二蚀刻步骤去除鳍有源区的侧壁上的介电层。
本发明的实施例提供了多种优势。但是应该理解，其它实施例可以提供其它优势，不是所有优势都需要在本文中讨论，并且没有特定优势是所有实施例都需要的。在至少一些实施例中，通过形成外延生长的源极和漏极部件，增大了载流子迁移率并且提高了器件性能。
图1是用于制造具有各种FET的工件(也称为半导体结构)300的方法200的流程图。图2是用于制造半导体结构300的源极/漏极部件的方法214的流程图。图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A和图13A是各个制造阶段处的工件300的顶视图。图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B、图11B、图12B和图13B是各个制造阶段处的沿着虚线AA’截取的工件300的截面图。图5C、图6C、图7C、图8C、图9C、图10C、图11C、图12C和图13C是各个制造阶段处的沿着虚线BB’截取的工件300的截面图。图5D、图6D、图7D、图8D、图9D、图10D、图11D、图12D和图13D是各个制造阶段处的沿着虚线CC’截取的工件300的截面图。图14A是制造阶段处的半导体结构300的顶视图。图14B、图14C、图14D、图14E和图14F是根据一些实施例的分别沿着虚线AA’、BB’、CC’、DD’和EE’截取的图14A的半导体结构300的截面图。
下面结合图1至图14F描述方法200。可以在方法200之前、期间和之后提供额外的步骤，并且对于方法200的其它实施例，可以替换或消除所描述的一些步骤。
首先参照图1的框202和图3A至图3B，接收工件300，工件300包括衬底102。在各种实例中，衬底102包括元素(单种元素)半导体，诸如晶体结构的硅或锗；化合物半导体，诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；非半导体材料，诸如钠钙玻璃、熔融硅石、熔融石英和/或氟化钙(CaF2)；和/或它们的组合。
衬底102的组成可以是均匀的或可以包括各种层。这些层可以具有类似或不同的组成，并且在各种实施例中，一些衬底层具有非均匀的组成，以引起器件应变并且由此调节器件性能。层状衬底的实例包括绝缘体上硅(SOI)衬底102。在一些这样的实例中，衬底102的层可以包括绝缘体，诸如氧化硅、氮化硅、碳化硅、氮氧化硅、碳化硅和/或其它合适的绝缘体材料。
仍然参照图1的框204和图3A至图3B，方法200包括在半导体衬底102中形成隔离部件104的操作，从而限定了由隔离部件104彼此分隔开的第一有源区106。隔离部件的形成可以包括：通过光刻形成图案化的掩模；通过图案化的掩模的开口蚀刻衬底102以形成沟槽；用一种或多种介电材料填充沟槽；以及实施CMP工艺。衬底102可以包括用于在其上形成不同器件的各种区。作为用于说明的实例，衬底102包括四个示例性的区102A、102B、102C和102D，第一区102A和第三区102C被设计用于在其上形成的逻辑器件，第二区102B和第四区102D被设计用于在其上形成的存储器器件，诸如静态随机存取存储器(SRAM)器件。此外，在第一区102A中，用于逻辑器件的n型FET(nFET)形成在其上；在第二区102B中，用于存储器器件的nFET形成在其上；在第三区102C中，用于逻辑器件的p型FET(pFET)形成在其上；并且在第四区102D中，用于存储器器件的pFET形成在其上。为了简单起见，方法200的以下详细描述仅针对第一区102A和第二区102B中的FET。
在一些实施例中，有源区是三维的，诸如鳍有源区。形成在那些鳍有源区上的那些FET因此称为FinFET。参照图1的框206和图4A和图4B，方法200还包括操作206，以形成突出于隔离部件104之上的鳍有源区108。这些鳍有源区也统称为鳍结构108。在一些实施例中，可以通过选择性蚀刻以使隔离部件104凹进来形成鳍有源区108。在其它实施例中，可以通过用一种或多种半导体材料在有源区中选择性外延生长来形成鳍有源区108。在又一些实施例中，鳍有源区108可以由混合步骤来形成，同时具有选择性蚀刻以凹进和选择性外延生长。在又一些实施例中，操作204和206可以由不同的步骤替换，以形成鳍有源区108和隔离部件104。例如，通过图案化衬底102以及然后通过沉积和CMP形成隔离部件104来形成鳍有源区108。
该鳍有源区108可以具有沿着X方向定向的伸长的形状。外延生长的半导体材料可以包括硅、锗、硅锗、碳化硅或其它合适的半导体材料。选择性蚀刻工艺可以包括湿蚀刻、干蚀刻、其它合适的蚀刻或它们的组合。
仍参照图1的框208和图4A与图4B，方法200可以进一步包括操作208以在鳍有源区108上形成一个或多个掺杂阱(诸如110A和110B)。掺杂阱沿着X方向延伸穿过鳍有源区108(诸如从左侧隔离部件104延伸至右侧隔离部件104)，使得鳍有源区108被围绕在对应的掺杂阱内。掺杂阱通过离子注入或其它合适的技术形成。在一些实例中，掺杂阱是n型掺杂的，用于在其上形成的一个或多个p型场效应晶体管(FET)。在一些实例中，掺杂阱是p型掺杂的，用于在其上形成的一个或多个n型FET。在一些实例中，半导体结构300包括如图4B所示的p型掺杂阱110A和n型掺杂阱110B。
参照图1的框210和图5A至图5D，方法200包括在衬底102上形成诸如112和114的一个或多个栅极堆叠件的操作。在本实施例中，栅极堆叠件是伪栅极堆叠件并且将在之后阶段由金属栅极堆叠件替换。每个栅极堆叠件可以包括栅极介电层(诸如氧化硅)以及位于鳍有源区上的栅极介电层上的栅电极(诸如多晶硅)。栅极堆叠件的形成包括：形成各个栅极材料层(诸如热氧化以形成氧化硅和沉积多晶硅)以及使用光刻工艺和蚀刻来图案化栅极材料层。硬掩模120可以用于图案化栅极材料层。例如，硬掩模120沉积在栅极材料层上，并且通过光刻工艺和蚀刻将硬掩模120图案化以具有各个开口。然后将在硬掩模上限定的图案通过蚀刻转印到栅极材料层。在一些实例中，硬掩模120包括氮化硅、氧化硅、其它合适的材料或它们的组合。在一些实例中，硬掩模120可以包括多个膜，诸如氮化硅层和氮化硅层上的氧化硅层。
为了图案化硬掩模120，操作210可以包括诸如光刻和蚀刻的各种工艺。光刻工艺可以包括在衬底102上方形成光刻胶(未示出)。示例性光刻胶包括对诸如UV光、深紫外(DUV)辐射和/或EUV辐射的辐射敏感的光敏材料。对工件300实施光刻曝光，将光刻胶的选定区域暴露于辐射。曝光在光刻胶的曝光区域中引起化学反应。在曝光后，将显影剂施加到光刻胶。显影剂溶解或以其它方式去除曝光区域(在正性光刻胶显影工艺的情况下)或未曝光区域(在负性光刻胶显影工艺的情况下)。合适的正性显影剂可以包括TMAH(四甲基氢氧化铵)、KOH和NaOH，以及合适的负性显影剂可以包括诸如乙酸正丁酯、乙醇、己烷、苯和甲苯的溶剂。在显影光刻胶之后，可以通过诸如湿蚀刻、干蚀刻、反应离子蚀刻(RIE)、灰化和/或其它蚀刻方法的蚀刻工艺去除硬掩模120的暴露部分，产生图案化的硬掩模120。在蚀刻之后，可以通过湿剥离或等离子体灰化去除光刻胶。
在一些实施例中，栅极间隔件122可以形成在栅极堆叠件的侧壁上。栅极间隔件122包括一种或多种介电材料，诸如氧化硅、氮化硅、氮氧化硅、其它合适的介电材料或它们的组合。间隔件122可以具有多层结构，并且可以通过沉积介电材料以及然后进行各向异性蚀刻(诸如等离子体蚀刻)来形成。在一些实施例中，栅极隔离件122可以用于偏移随后形成的源极/漏极部件，并且可以用于设计或修改源极/漏极轮廓。
伪栅极堆叠件形成在鳍108上方的沟道区124上方，其中沟道区124可以是相应FET的部分。金属栅极堆叠件的形成可以包括后栅极工艺、后高k工艺或其它合适的过程，这将在稍后阶段进行描述。
参照图1的框121和图6A至图6D，方法200B进行在工件300上形成介电层126的操作。介电层126可以通过合适的方法沉积，诸如CVD或其它适当的技术。介电层126可以在制造工艺期间提供适当的功能，诸如蚀刻停止/保护。介电层126可以包括多个膜。在本实施例中，介电层126包括氮氧化硅膜、位于氮氧化硅膜上的氮化硅膜和位于氮化硅膜上的低k介电膜。可以通过CVD沉积具有适当的厚度的每个膜。
方法200进行至框214以形成外延源极和漏极部件。参照图2进一步详细描述操作214。
参照图2的框222和图7A至图7D，方法200进行至形成具有开口的图案化的光刻胶层130的操作，以暴露工件300的第一区内的第一源极/漏极区。源极/漏极区是指鳍有源区的用于形成在其上的相应的源极/漏极部件的区。在一些实施例中，第一区包括待形成的各种器件，诸如逻辑器件。如图7A所示，通过光刻工艺形成图案化的光刻胶层130，图案化的光刻胶层130具有限定第一区的开口。在本实施例中，光刻胶层130是三层光刻胶，其包括底层130A、中间层130B和光敏层130C以增强具有高分辨率和耐蚀刻性的光刻工艺，如图7B所示。
参照图2的框224和图8A至图8D，方法200进行至对工件300的第一区内的第一源极/漏极区实施干蚀刻工艺的操作。干蚀刻工艺可以包括一个或多个蚀刻步骤，蚀刻步骤打开介电层126并且使第一区中的源极/漏极区凹进。具体地，干蚀刻工艺使第一源极/漏极区凹进以形成具有第一深度D1的沟槽，第一深度D1诸如在从55nm至65nm的范围内。在一些实例中，干蚀刻工艺包括施加包含碳氧化物和氢氟化碳的蚀刻剂。
参照图2的框226和图9A至图9D，实施外延工艺以在第一区中的衬底102上形成第一源极/漏极部件132。在外延工艺期间，伪栅极堆叠件和/或图案化的光刻胶层130将源极/漏极部件132限制于第一区中的源极/漏极区。合适的外延工艺包括CVD沉积技术(例如气相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其它合适的工艺。外延工艺可以使用气体和/或液体前体，气体和/或液体前体与衬底102的组成相互作用。源极/漏极部件132可以在外延工艺期间通过引入掺杂物质而被原位掺杂，掺杂物质包括p型掺杂剂，诸如硼或BF2；n型掺杂剂，诸如磷或砷；和/或包括它们的组合的其它合适的掺杂剂。如果未原位掺杂源极/漏极部件132，实施注入工艺(即，结注入工艺)以掺杂源极/漏极部件132。在示例性实施例中，NMOS器件中的源极/漏极部件132包括SiP，而PMOS器件中的源极/漏极部件132包括GeSnB(锡可以用于调节晶格常数)和/或SiGeSnB。可以实施一个或多个退火工艺以活化源极/漏极部件132。合适的退火工艺包括快速热退火(RTA)和/或激光退火工艺。在形成第一源极/漏极部件132之后，通过适当的技术去除图案化的光刻胶层130。
参照图2的框228和图10A至图10D，方法200进行至形成具有开口的图案化的光刻胶层134的操作，以暴露工件300的第二区内的第二源极/漏极区。在一些实施例中，第二区包括待形成的各个器件，诸如存储器器件。例如，存储器器件可以包括静态随机存取存储器器件。如图10A所示，通过光刻工艺形成具有限定第二区的开口的图案化的光刻胶层134。在本实施例中，光刻胶层134是与光刻胶层130类似的三层光刻胶。例如，图案化的光刻胶层134包括底层134A、中间层134B和光敏层134C以增强具有高分辨率和耐蚀刻性的光刻工艺，如图10B所示。
参照图2的框230与图11A至图11D，方法200可以包括对工件300的第二区内的第二源极/漏极区实施浅凹进工艺的操作。在本实施例中，浅凹进工艺包括干蚀刻工艺，干蚀刻工艺可以包括一个或多个蚀刻步骤，蚀刻步骤打开介电层126并且使第二源极/漏极区凹进。具体地，干蚀刻工艺使第二源极/漏极区凹进以形成具有第二深度D2的沟槽，第二深度D2小于第一深度D1。在一些实例中，第二深度在从45nm至55nm的范围内。在一些实例中，干法蚀刻工艺包括施加包含碳氧化物和氢氟化碳的蚀刻剂。
参照图2的框232和图12A至图12D，方法200进行至实施鳍侧壁拉回(FSWPB)工艺的操作。该FSWPB工艺232去除或拉回第二区中的鳍侧壁上的介电层126。在本实施例中，FSWPB工艺包括湿蚀刻工艺以去除第二区中的鳍侧壁上的介电层126。湿蚀刻工艺可以包括相应的蚀刻剂的一个或多个蚀刻步骤，以去除介电层126的各个膜。在FSWPB工艺之后，第二区的第二源极/漏极区内的相邻鳍不被介电层126分开，并且可以在随后的外延生长期间合并在一起。
参照图2的框234和图13A至图13D，实施外延工艺以在第二区的衬底102上形成第二源极/漏极部件136。在外延工艺期间，伪栅极堆叠件和/或图案化的光刻胶层134将源极/漏极部件136限制于第二区中的源极/漏极区。合适的外延工艺包括CVD沉积技术(例如VPE和/或UHV-CVD)、分子束外延和/或其它合适的工艺。外延工艺可以使用气体和/或液体前体，气体和/或液体前体与衬底102的组成相互作用。源极/漏极部件136可以在外延工艺期间通过引入掺杂物质而被原位掺杂，掺杂物质包括p型掺杂剂，诸如硼或BF2；n型掺杂剂，诸如磷或砷；和/或包括它们的组合的其它合适的掺杂剂。如果未原位掺杂源极/漏极部件136，实施注入工艺(即，结注入工艺)以掺杂源极/漏极部件136。在示例性实施例中，NMOS器件中的源极/漏极部件136包括SiP，而PMOS器件中的源极/漏极部件136包括GeSnB(锡可以用于调节晶格常数)和/或SiGeSnB。可以实施一个或多个退火工艺以活化源极/漏极部件136。合适的退火工艺包括快速热退火(RTA)和/或激光退火工艺。
特别地，相邻鳍上的源极/漏极部件136在外延生长期间合并在一起，这增强了对沟道区124的应变效应，并且增加了与源极/漏极接触件的接触区。在一些实施例中，如图13D所示，在外延生长的源极/漏极部件136和位于相邻鳍108之间的隔离部件104之间形成气隙138。气隙138为第二区中的源极/漏极部件136提供额外的隔离功能。在形成源极/漏极部件136之后，通过与用于图案化的光刻胶层130类似的合适的步骤去除图案化的光刻胶层134。由于深度D1和D2不同，第一源极/漏极部件132的底面低于第二源极/漏极部件136的底面。第一源极/漏极部件132是第一FET 152的部分，并且第二源极/漏极部件136是第二FET154的部分。
参照图1的框216和图14A至图14F，方法200进行至形成金属栅极堆叠件以替换伪栅极堆叠件。图14A是工件300的顶视图，并且图14B至图14F是根据一些实施例的分别沿着虚线AA’、BB’、CC’、DD’和EE’截取的工件300的部分的截面图。例如，操作216形成金属栅极堆叠件142以替换伪栅极堆叠件112(如图14B所示)，并且形成金属栅极堆叠件144以替换伪栅极堆叠件114(如图14C所示)。金属栅极堆叠件142是第一FET152的部分，并且金属栅极堆叠件144是第二FET154的部分。下面进一步描述金属栅极堆叠件的形成。
通过沉积和诸如化学机械抛光(CMP)的抛光在工件300上形成层间介电(ILD)层146。注意，为了示出的目的，ILD层146在图14A的顶视图中绘制为透明的，使得各个鳍108和源极/漏极部件(132和136)是可见的。ILD层146用作支撑和隔离导电迹线的绝缘体。ILD层146可以包括任何合适的介电材料，诸如氧化硅、掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃、氟化硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅酸盐玻璃(BSG))、氮化硅、氮氧化硅、碳化硅、低k介电材料、其它合适的材料和/或它们的组合。ILD层146可以通过PECVD工艺、可流动CVD(FCVD)工艺或其它合适的沉积技术来沉积。随后可以进行CMP工艺以去除过量的介电材料并且平坦化顶面。可以通过CMP去除硬掩模120。可选地，硬掩模120可以用作抛光停止层并且在CMP之后通过额外的蚀刻工艺被去除。
通过蚀刻分别或共同地去除伪栅极堆叠件(诸如112和114)或部分。施加选择性蚀刻工艺以去除伪栅极材料，诸如多晶硅，产生栅极沟槽。蚀刻工艺可以包括任何合适的蚀刻技术，诸如湿蚀刻、干蚀刻、RIE、灰化和/或其它蚀刻方法。在一个实例中，蚀刻工艺是使用基于氟的蚀刻剂(例如，CF4、CHF3、CH2F2等)的干蚀刻工艺。在一些实施例中，蚀刻包括具有不同蚀刻化学物的多个蚀刻步骤，每个均以伪栅极层的特定材料为目标。
栅极沟槽由栅极材料(诸如栅极介电层和栅电极)填充，每个均包括一个或多个材料层。在一些这样的实施例中，通过任何合适的技术(诸如ALD、CVD、金属有机CVD(MOCVD)、PVD、热氧化、它们的组合和/或其它合适的技术)在工件300上沉积栅极介电层。栅极介电层可以包括高k介电材料，诸如金属氧化物(例如，LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3等)、金属硅酸盐(例如，HfSiO、LaSiO，AlSiO等)、金属或半导体氮化物、金属或半导体氧氮化物、它们的组合和/或其它合适的材料。同样，栅电极沉积在栅极介电层上。特别地，栅电极是导电的。在各个实例中，栅电极可以包括单层或多个层，诸如金属层、衬垫层、润湿层和/或粘附层。栅电极层还可以包括功函金属层和金属填充层。功函数金属层可以包括p型功函金属层或n型功函金属层。p型功函金属层包括选自但不限于以下的金属：氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或它们的组合。n型功函金属层包括选自但不限于以下的金属：钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)或它们的组合。p型或n型功函金属层还可以包括多个层，并且可以通过CVD、PVD和/或其它合适的工艺来沉积。金属填充层可以包括铝(Al)、钨(W)或铜(Cu)和/或其它合适的材料。金属填充层可以通过CVD、PVD、镀和/或其它合适的工艺形成。在沉积金属栅极材料之后，实施CMP工艺以产生金属栅极堆叠件的基本上平坦的顶面。
因此，利用相应的结构和步骤在衬底12上形成包括各个FET的各个器件。具体地，第一和第二源极/漏极部件通过不同工艺形成，并且产生如上所述的相应的结构，并且分别在图14D和图14E中示出。例如，如图14E所示，直接在具有增强的载流子迁移率的相应的鳍的侧壁上形成源极/漏极部件136。来自相邻鳍的源极/漏极部件136合并在一起以形成具有减小的接触电阻的共同源极/漏极部件。如图14F所示，由于不同的深度D1和D2，源极/漏极部件136的底面高于源极/漏极部件132的底面。
方法200可以继续进行进一步工艺以完成工件300的制造。例如，该方法可以进行至操作218以形成互连结构以将各个器件耦合到集成电路。互连结构包括用于水平耦合的多个金属层中的金属线以及用于相邻金属层之间或底部金属层和衬底102上的器件部件(诸如源极/漏极部件和栅极堆叠件)之间的垂直耦合的通孔/接触件。互连结构包括一种或多种合适的导电材料，诸如铜、铝合金、钨、硅化物或其它合适的导电材料。互连结构可以通过镶嵌工艺形成，诸如单镶嵌工艺或双镶嵌工艺，其包括光刻图案化、蚀刻沉积和CMP。例如，导电材料可以使用适当的工艺沉积，诸如CVD、PVD、镀和/或其它合适的工艺。所示出的工件300仅仅是方法200的一些方法的实例。方法200可以具有各种其它实施例，而不背离本发明的范围。
此外，如上文所示的半导体结构300可以是IC或其部分的处理期间制造的中间器件，IC或其部分可以包括静态随机存取存储器(SRBM)和/或逻辑电路、诸如电阻器、电容器和电感器的无源元件，以及有源器件，诸如p型场效应晶体管(PFET)、n型FET(NFET)、多栅极FET(诸如FinFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其它存储器单元以及它们的组合。
本发明提供了半导体结构及其制造方法。该方法包括不同的步骤，以形成用于各个器件的外延生长的源极/漏极部件。尽管不旨在限制，本发明的一个或多个实施例为半导体器件(包括FinFET)及其形成提供了许多益处。例如，两种类型的FET是由不同步骤形成的。第一种类型可以是逻辑器件，而第二种类型可以是存储器器件。特别地，用于第二类型FET的第二源极/漏极部件通过包括FSWPB工艺的步骤形成，这降低了接触电阻，并且提高了载流子迁移率。公开的方法提供了不同且独立地处理不同的FET的自由，以满足相应的规格。然而，第一类型FET和第二类型FET不限于逻辑器件和存储器器件，并且可以是具有不同规格的其它类型的器件。例如，根据设计考虑，第一类型FET是p型FET，而第二类型FET是n型FET，或反之亦然。
因此，本发明提供了制造半导体结构的方法的实例。该方法包括在衬底上形成鳍结构，其中鳍结构包括第一鳍有源区；第二鳍有源区；以及将第一鳍有源区与第二鳍有源区分隔开的隔离部件；在第一鳍有源区上形成第一栅极堆叠件，并且在第二鳍有源区上形成第二栅极堆叠件；以及通过第一干蚀刻对第一鳍有源区的第一源极/漏极区实施第一凹进工艺；实施第一外延生长以在第一源极/漏极区上形成第一源极/漏极部件；实施鳍侧壁拉回(FSWPB)工艺以去除第二鳍有源区上的介电层；以及实施第二外延生长以在第二鳍有源区的第二源极/漏极区上形成第二源极/漏极部件。
在上述方法中，还包括：在实施所述鳍侧壁拉回工艺以去除所述第二鳍有源区上的所述介电层之前，通过第二干蚀刻对所述第二鳍有源区的所述第二源极/漏极区实施第二凹进工艺，其中，所述第一干蚀刻使所述第一鳍有源区凹进至第一深度；所述第二干蚀刻使所述第二鳍有源区凹进至第二深度；并且所述第二深度小于所述第一深度。
在上述方法中，还包括：在实施所述鳍侧壁拉回工艺以去除所述第二鳍有源区上的所述介电层之前，通过第二干蚀刻对所述第二鳍有源区的所述第二源极/漏极区实施第二凹进工艺，其中，所述第一干蚀刻使所述第一鳍有源区凹进至第一深度；所述第二干蚀刻使所述第二鳍有源区凹进至第二深度；并且所述第二深度小于所述第一深度，其中，所述第一深度在55nm和65nm之间的范围内，并且所述第二深度在45nm和55nm之间的范围内。
在上述方法中，其中，所述鳍侧壁拉回工艺包括湿蚀刻工艺以选择性地去除所述第二鳍有源区的侧壁上的所述介电层。
在上述方法中，其中，所述鳍侧壁拉回工艺包括湿蚀刻工艺以选择性地去除所述第二鳍有源区的侧壁上的所述介电层，其中，实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括直接在所述第二鳍有源区的侧壁上形成所述第二源极/漏极部件。
在上述方法中，其中，所述鳍侧壁拉回工艺包括湿蚀刻工艺以选择性地去除所述第二鳍有源区的侧壁上的所述介电层，其中，实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括形成所述第二源极/漏极部件，在所述第二源极/漏极部件和所述隔离部件之间产生气隙。
在上述方法中，其中，所述鳍侧壁拉回工艺包括湿蚀刻工艺以选择性地去除所述第二鳍有源区的侧壁上的所述介电层，其中，实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括在鳍有源区和相邻的鳍有源区上形成合并的源极/漏极部件。
在上述方法中，还包括：在所述第一鳍有源区和所述第二鳍有源区上沉积所述介电层，其中，实施所述鳍侧壁拉回工艺以去除所述第二鳍有源区上的所述介电层包括：形成图案化的掩模以覆盖所述第一鳍有源区；以及施加湿蚀刻以选择性地去除所述第二鳍有源区上的所述介电层。
在上述方法中，还包括：在所述第一鳍有源区和所述第二鳍有源区上沉积所述介电层，其中，实施所述鳍侧壁拉回工艺以去除所述第二鳍有源区上的所述介电层包括：形成图案化的掩模以覆盖所述第一鳍有源区；以及施加湿蚀刻以选择性地去除所述第二鳍有源区上的所述介电层，其中，实施所述第一外延生长以在所述第一源极/漏极区上形成所述第一源极/漏极部件包括在所述第一鳍有源区的侧壁上形成所述第一源极/漏极部件，所述介电层插入在所述第一鳍有源区和所述第一源极/漏极部件之间。
在上述方法中，其中，所述第一栅极堆叠件和所述第一源极/漏极部件配置为第一场效应晶体管的部分，并且所述第二栅极堆叠件和所述第二源极/漏极部件配置为第二场效应晶体管的部分。
在上述方法中，其中，所述第一栅极堆叠件和所述第一源极/漏极部件配置为第一场效应晶体管的部分，并且所述第二栅极堆叠件和所述第二源极/漏极部件配置为第二场效应晶体管的部分，其中，所述第一场效应晶体管是第一导电类型的场效应晶体管，所述第二场效应晶体管是与第一导电类型相反的第二导电类型的场效应晶体管。
在上述方法中，其中，所述第一栅极堆叠件和所述第一源极/漏极部件配置为第一场效应晶体管的部分，并且所述第二栅极堆叠件和所述第二源极/漏极部件配置为第二场效应晶体管的部分，其中，所述第一场效应晶体管是逻辑器件，并且所述第二场效应晶体管是存储器器件。
在上述方法中，其中，所述第一干蚀刻和所述第二干蚀刻的每个均包括包含碳氧化物和氢氟化碳的蚀刻剂。
本发明还提供了半导体结构的实例。半导体结构包括：半导体衬底；从半导体衬底延伸的第一鳍有源区和第二鳍有源区；位于第一鳍有源区上的第一场效应晶体管；以及位于第二鳍有源区上的第二场效应晶体管。第一场效应晶体管包括设置在第一鳍有源区的第一沟道区上的第一栅极堆叠件，以及设置在第一沟道区的相对侧上的第一外延生长的源极/漏极部件。第二场效应晶体管包括设置在第二鳍有源区的第二沟道区上的第二栅极堆叠件，以及设置在第二沟道区的相对侧上的第二外延生长的源极/漏极部件。第一外延生长的源极/漏极部件的底面低于第二外延生长的源极/漏极部件的底面。
在上述半导体结构中，其中，所述第一场效应晶体管是第一导电类型的场效应晶体管，所述第二场效应晶体管是与第一导电类型相反的第二导电类型的场效应晶体管。
在上述半导体结构中，其中，所述第一场效应晶体管是逻辑器件，并且所述第二场效应晶体管是存储器器件。
在上述半导体结构中，还包括位于所述第一鳍有源区的侧壁上的介电层，其中，所述第一外延生长的源极/漏极部件通过所述介电层彼此分隔开；并且所述第二外延生长的源极/漏极部件直接形成在所述第二鳍有源区的侧壁上。
在上述半导体结构中，还包括位于所述第一鳍有源区的侧壁上的介电层，其中，所述第一外延生长的源极/漏极部件通过所述介电层彼此分隔开；并且所述第二外延生长的源极/漏极部件直接形成在所述第二鳍有源区的侧壁上，其中，所述第二外延生长的源极/漏极部件包括合并成共同的源极/漏极部件的两个相邻的源极/漏极部件，在所述共同的源极/漏极部件和浅沟槽隔离(STI)部件之间垂直地限定气隙。
本发明提供制造半导体结构的方法的其它实例。该方法包括在衬底上形成鳍结构，其中鳍结构包括：第一鳍有源区；第二鳍有源区；以及将第一鳍有源区和第二鳍有源区分隔开的隔离部件；在第一鳍有源区上形成第一栅极堆叠件，并且在第二鳍有源区上形成第二栅极堆叠件；以及对第一鳍有源区上的第一源极/漏极区实施第一凹进工艺，其中，第一凹进工艺包括第一干蚀刻以使第一鳍有源区凹进；实施第一外延生长以在第一源极/漏极区上形成第一源极/漏极部件；对第二鳍有源区上的第二源极/漏极区实施第二凹进工艺，其中，第二凹进工艺包括第二干蚀刻以使第二鳍有源区凹进，并且实施鳍侧壁拉回(FSWPB)工艺以去除第二鳍有源区上的介电层；以及实施第二外延生长以在第二源极/漏极区上形成第二源极/漏极部件。第一干蚀刻将第一鳍有源区凹进至第一深度；第二干蚀刻将第二鳍有源区凹进至第二深度；并且第二深度小于第一深度。
在上述方法中，其中，所述鳍侧壁拉回工艺包括湿蚀刻工艺以选择性地去除所述第二鳍有源区的侧壁上的所述介电层；并且实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括直接在所述第二鳍有源区的侧壁上形成所述第二源极/漏极部件。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种制造半导体器件的方法，包括：
在衬底上形成鳍结构，其中，所述鳍结构包括：第一鳍有源区；第二鳍有源区；以及将所述第一鳍有源区与所述第二鳍有源区分隔开的隔离部件；
在所述第一鳍有源区上形成第一栅极堆叠件，并且在所述第二鳍有源区上形成第二栅极堆叠件；
通过第一干蚀刻对所述第一鳍有源区的第一源极/漏极区实施第一凹进工艺；
实施第一外延生长以在所述第一源极/漏极区上形成第一源极/漏极部件；
实施鳍侧壁拉回(FSWPB)工艺以去除所述第二鳍有源区上的介电层；以及
实施第二外延生长以在所述第二鳍有源区的第二源极/漏极区上形成第二源极/漏极部件，
所述第二鳍有源区的高出所述隔离部件的部分所具有的表面被所述第二外延生长形成的所述第二源极/漏极部件包裹，并且所述表面在实施所述包裹之前被所述鳍侧壁拉回(FSWPB)工艺去除之前的所述介电层覆盖。
2.根据权利要求1所述的方法，还包括：在实施所述鳍侧壁拉回工艺以去除所述第二鳍有源区上的所述介电层之前，通过第二干蚀刻对所述第二鳍有源区的所述第二源极/漏极区实施第二凹进工艺，其中，
所述第一干蚀刻使所述第一鳍有源区凹进至第一深度；
所述第二干蚀刻使所述第二鳍有源区凹进至第二深度；并且
所述第二深度小于所述第一深度。
3.根据权利要求2所述的方法，其中，所述第一深度在55nm和65nm之间的范围内，并且所述第二深度在45nm和55nm之间的范围内。
4.根据权利要求1所述的方法，其中，所述鳍侧壁拉回工艺包括湿蚀刻工艺以选择性地去除所述第二鳍有源区的侧壁上的所述介电层。
5.根据权利要求4所述的方法，其中，实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括直接在所述第二鳍有源区的侧壁上形成所述第二源极/漏极部件。
6.根据权利要求4所述的方法，其中，实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括形成所述第二源极/漏极部件，在所述第二源极/漏极部件和所述隔离部件之间产生气隙。
7.根据权利要求4所述的方法，其中，实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括在鳍有源区和相邻的鳍有源区上形成合并的源极/漏极部件。
8.根据权利要求1所述的方法，还包括：在所述第一鳍有源区和所述第二鳍有源区上沉积所述介电层，其中，实施所述鳍侧壁拉回工艺以去除所述第二鳍有源区上的所述介电层包括：
形成图案化的掩模以覆盖所述第一鳍有源区；以及
施加湿蚀刻以选择性地去除所述第二鳍有源区上的所述介电层。
9.根据权利要求8所述的方法，其中，实施所述第一外延生长以在所述第一源极/漏极区上形成所述第一源极/漏极部件包括在所述第一鳍有源区的侧壁上形成所述第一源极/漏极部件，所述介电层插入在所述第一鳍有源区和所述第一源极/漏极部件之间。
10.根据权利要求1所述的方法，其中，所述第一栅极堆叠件和所述第一源极/漏极部件配置为第一场效应晶体管的部分，并且所述第二栅极堆叠件和所述第二源极/漏极部件配置为第二场效应晶体管的部分。
11.根据权利要求10所述的方法，其中，所述第一场效应晶体管是第一导电类型的场效应晶体管，所述第二场效应晶体管是与第一导电类型相反的第二导电类型的场效应晶体管。
12.根据权利要求10所述的方法，其中，所述第一场效应晶体管是逻辑器件，并且所述第二场效应晶体管是存储器器件。
13.根据权利要求2所述的方法，其中，所述第一干蚀刻和所述第二干蚀刻的每个均包括包含碳氧化物和氢氟化碳的蚀刻剂。
14.一种半导体器件，包括：
半导体衬底；
第一鳍有源区和第二鳍有源区，从所述半导体衬底延伸；
第一场效应晶体管，位于所述第一鳍有源区上；以及
第二场效应晶体管，位于所述第二鳍有源区上，其中，
所述第一场效应晶体管包括设置在所述第一鳍有源区的第一沟道区上的第一栅极堆叠件，以及设置在所述第一沟道区的左右两侧上的第一外延生长的源极/漏极部件，
所述第二场效应晶体管包括设置在所述第二鳍有源区的第二沟道区上的第二栅极堆叠件，以及设置在所述第二沟道区的左右两侧上的第二外延生长的源极/漏极部件，以及
所述第一外延生长的源极/漏极部件的底面低于所述第二外延生长的源极/漏极部件的底面，
其中，所述第二外延生长的源极/漏极部件包括合并成共同的源极/漏极部件的两个相邻的源极/漏极部件，在所述共同的源极/漏极部件和浅沟槽隔离(STI)部件之间垂直地限定气隙。
15.根据权利要求14所述的半导体器件，其中，所述第一场效应晶体管是第一导电类型的场效应晶体管，所述第二场效应晶体管是与第一导电类型相反的第二导电类型的场效应晶体管。
16.根据权利要求14所述的半导体器件，其中，所述第一场效应晶体管是逻辑器件，并且所述第二场效应晶体管是存储器器件。
17.根据权利要求14所述的半导体器件，还包括位于所述第一鳍有源区的侧壁上的介电层，其中，
所述第一外延生长的源极/漏极部件通过所述介电层彼此分隔开；并且
所述第二外延生长的源极/漏极部件直接形成在所述第二鳍有源区的侧壁上。
18.根据权利要求17所述的半导体器件，还包括，
隔离部件，位于所述第一场效应晶体管和所述第二场效应晶体管之间，
所述第二外延生长的源极/漏极部件的顶面高于所述隔离部件的顶面。
19.一种制造半导体器件的方法，包括：
在衬底上形成鳍结构，其中，所述鳍结构包括：第一鳍有源区；第二鳍有源区；以及将所述第一鳍有源区和所述第二鳍有源区分隔开的隔离部件；
在所述第一鳍有源区上形成第一栅极堆叠件，并且在所述第二鳍有源区上形成第二栅极堆叠件；
在所述第一栅极堆叠件和所述第二栅极堆叠件上形成介电层；
通过第一干蚀刻对所述第一鳍有源区的第一源极/漏极区实施第一凹进工艺；
实施第一外延生长以在所述第一源极/漏极区上形成第一源极/漏极部件；
通过第二干蚀刻对所述第二鳍有源区的第二源极/漏极区实施第二凹进工艺；
实施鳍侧壁拉回(FSWPB)工艺以去除所述第二鳍有源区上的所述介电层的部分；以及
实施第二外延生长以在所述第二源极/漏极区上形成第二源极/漏极部件，其中，所述第一干蚀刻将所述第一鳍有源区凹进至第一深度；所述第二干蚀刻将所述第二鳍有源区凹进至第二深度；并且所述第二深度小于所述第一深度，
所述第二鳍有源区的高出所述隔离部件的部分所具有的表面被所述第二外延生长形成的所述第二源极/漏极部件包裹，并且所述表面在实施所述包裹之前被所述鳍侧壁拉回(FSWPB)工艺去除之前的所述介电层的部分覆盖。
20.根据权利要求19所述的方法，其中，
所述鳍侧壁拉回工艺包括湿蚀刻工艺以选择性地去除所述第二鳍有源区的侧壁上的所述介电层；并且
实施所述第二外延生长以在所述第二源极/漏极区上形成所述第二源极/漏极部件包括直接在所述第二鳍有源区的侧壁上形成所述第二源极/漏极部件。
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