CN109308996A - A kind of negative pressure diffusion technique of silicon wafer - Google Patents
A kind of negative pressure diffusion technique of silicon wafer Download PDFInfo
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- CN109308996A CN109308996A CN201710615675.0A CN201710615675A CN109308996A CN 109308996 A CN109308996 A CN 109308996A CN 201710615675 A CN201710615675 A CN 201710615675A CN 109308996 A CN109308996 A CN 109308996A
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 123
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 110
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 107
- 239000010703 silicon Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 46
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims abstract description 22
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052796 boron Inorganic materials 0.000 claims abstract description 20
- 238000007639 printing Methods 0.000 claims abstract description 17
- 238000003475 lamination Methods 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 238000012805 post-processing Methods 0.000 claims abstract description 10
- FGUJWQZQKHUJMW-UHFFFAOYSA-N [AlH3].[B] Chemical compound [AlH3].[B] FGUJWQZQKHUJMW-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 239000002253 acid Substances 0.000 claims description 17
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims description 15
- 239000011574 phosphorus Substances 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000003892 spreading Methods 0.000 claims description 5
- 230000007480 spreading Effects 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 3
- 239000000843 powder Substances 0.000 claims description 3
- 239000011863 silicon-based powder Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 claims 19
- 239000007788 liquid Substances 0.000 abstract description 18
- 230000008569 process Effects 0.000 abstract description 10
- 238000012545 processing Methods 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000007650 screen-printing Methods 0.000 abstract description 6
- 238000002203 pretreatment Methods 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 32
- 238000004140 cleaning Methods 0.000 description 25
- 239000003513 alkali Substances 0.000 description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 238000003763 carbonization Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229960000583 acetic acid Drugs 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000012362 glacial acetic acid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000006396 nitration reaction Methods 0.000 description 2
- 230000008092 positive effect Effects 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920006351 engineering plastic Polymers 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000010436 fluorite Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- GVVPGTZRZFNKDS-JXMROGBWSA-N geranyl diphosphate Chemical compound CC(C)=CCC\C(C)=C\CO[P@](O)(=O)OP(O)(O)=O GVVPGTZRZFNKDS-JXMROGBWSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 230000002000 scavenging effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The present invention provides a kind of negative pressure diffusion technique of silicon wafer, include the following steps: to it is two-sided be thinned after be put into silicon wafer diffusion pre-treatment, treated, and silicon wafer carries out printing diffusion source, using silk-screen printing technique, to treated, silicon wafer one side prints phosphorous diffusion source, and another side prints boron diffusion source or boron aluminum extension dissipates source；The opposite lamination that carries out in the face in the identical diffusion source of silicon wafer is filled into boat；Low pressure diffusion is carried out in diffusion furnace and is diffused post-processing.The beneficial effects of the invention are as follows printing phosphorous diffusion source, boron diffusion source or boron aluminum extension respectively on silicon wafer two sides using silk-screen printing technique to dissipate source, so that the coating process of silicon wafer liquid source is simplified, and the process-cycle is reduced；A negative pressure diffusion technique is used after liquid source coating, mitigates silicon chip edge and returns source situation, and the diffusion process steps simplify, and improve diffuser efficiency；Silicon wafer liquid source One Diffusion Process is carried out using the process, so that the PN junction of production is uniform, so that the processing cost of silicon wafer reduces.
Description
Technical field
The invention belongs to the manufacturing process areas of silicon wafer, more particularly, to a kind of negative pressure diffusion technique of silicon wafer.
Background technique
With the development of semiconductor technology, the requirement to semiconductor surface passivation is higher and higher, as passivating material, should have
Standby good electric property, reliability, good chemical stability, operability and economy.According to above-mentioned requirements, partly lead
Body is passivated special glass and starts to apply in semicon industry as a kind of ideal semiconductor passivation material.Using partly leading
The chip of body passivation special glass production is known as glassivation chip (Glass passivation process Chip), i.e.,
GPP chip.
Currently, the production of silicon wafer can use diffusion technique formation PN junction, diffusion work commonly used in the trade at present mostly in industry
Skill is generally used phosphorus paper source, a boron paper source perfect diffusion or is spread twice using phosphorus, boron, and there is can not for these diffusion ways
The defect avoided: 1) due to paper source after sintering silicon wafer between gap increase, cause volatilization phosphorus source to diffuse to boron face and cause to return source；2)
The mode technique production spread twice is cumbersome, and after one side phosphorus diffusion, another side needs sandblasting or chemical reduction to remove anti-source
Amount, then boron diffusion is carried out, at high cost, diffuser efficiency is low, and be easy to cause fragment.
Summary of the invention
In view of the above problems, the problem to be solved in the present invention is to provide a kind of negative pressure diffusion techniques of silicon wafer, using silk
Wire mark brush phosphorous diffusion source, boron diffusion source or boron aluminum extension dissipate source, and use a negative pressure diffusion technique, make uniform PN junction, mitigate
Source situation is returned, diffuser efficiency is improved.
In order to solve the above technical problems, the technical solution adopted by the present invention is that: a kind of negative pressure diffusion technique of silicon wafer, packet
Include following steps:
1) low pressure is spread: the silicon wafer behind coating diffusion source is carried out low pressure diffusion in diffusion furnace.
Further, the low pressure in step 1) spreads specific steps are as follows:
A. the silicon wafer behind coating diffusion source is placed in diffusion furnace, and air pressure in diffusion furnace is evacuated to negative pressure.
Further, further comprising the steps of after step a:
B. diffusion furnace temperature is risen into 1250 DEG C of -1300 DEG C of progress constant temperature diffusions, constant temperature time 10-30h；
C. after spreading, diffusion furnace temperature is down to 550 DEG C -650 DEG C and is come out of the stove.
It further, further include printing diffusion source before step 1) negative pressure diffusing step.
Further, printing diffusion source uses screen printing technique, specifically includes the following steps:
A. in the silicon wafer one side printing phosphorous diffusion source by being handled before spreading: phosphorous diffusion source being sprayed on halftone, silicon wafer
It is placed in below the halftone, is printed phosphorous diffusion source to silicon chip surface with scraper；
B. the silicon wafer for printing phosphorous diffusion source is placed in baking oven, phosphorous diffusion source is dried；
C. boron diffusion source or boron aluminum extension are dissipated source by the technique of step B, step C to print to silicon wafer another side, and is dried
It is roasting；
D. upper Al is sprayed on silicon wafer two sides2O3Powder or silicon powder.
Further, the drying time in step B is determined according to the number to be printed in diffusion source.
It further, further include lamination dress boat behind printing diffusion source.
Further, the step of lamination dress boat are as follows: by silicon wafer boron source face or boron silicon source face and boron source face or boron silicon source face phase
It is right, phosphorus source face progress lamination opposite with phosphorus source face is filled into boat.
Further, further include diffusion post-processing after diffusion, specially the silicon wafer after diffusion is placed in acid and is diffused
Post-processing.
Further, the acid in diffusion post-processing is hydrofluoric acid.
The advantages and positive effects of the present invention are: due to the adoption of the above technical scheme, being existed using silk-screen printing technique
Silicon wafer two sides prints phosphorous diffusion source, boron diffusion source or boron aluminum extension respectively and dissipates source, so that the coating process of silicon wafer liquid source obtains letter
Change, and the process-cycle is reduced；A negative pressure diffusion technique is used after liquid source coating, mitigates silicon chip edge and returns source situation,
And the diffusion process steps simplify, and improve diffuser efficiency；Silicon wafer liquid source One Diffusion Process is carried out using the process, so that
The PN junction of production is uniform, so that the processing cost of silicon wafer reduces.
Detailed description of the invention
Fig. 1 is flow chart of the invention.
Specific embodiment
The present invention is described further in the following with reference to the drawings and specific embodiments.
As shown in Figure 1, including the following steps: the present invention relates to a kind of negative pressure diffusion technique of silicon wafer
1) silicon wafer is two-sided is thinned: two-sided corrosion is carried out to silicon wafer using corrosive liquid, removes surface damage layer, specifically include as
Lower step:
A. thermometer measure corrosive liquid temperature is used, which is generally 0-15 DEG C, and sets silicon wafer according to corrosive liquid temperature
Etching time, the etching time are generally 9-50s, determine etching time according to corrosive liquid temperature, silicon wafer is placed in corrosive liquid
Middle carry out corrosion thinning, the thickness of silicon wafer thinning single surface is determined according to corrosive liquid temperature, which is generally 10-20 μm；
B. after corroding, silicon wafer is cleaned, is to be put into silicon wafer in pure water rinse bath to clean here, cleaned
Fall the corrosive liquid during corrosion thinning, the time of cleaning is 10-20min；
C. measure silicon wafer subduction amount: whether the subduction amount that Wafer Cleaning completely measures silicon wafer afterwards complies with standard, inner to use
Measuring instrument is spiral micrometer, can also be the instrument of other measurement thickness, that is, the measurement two-sided thinned thickness of silicon wafer, it should
Thickness is generally 10-20 μm；
D. spilling water cleaning is carried out to silicon wafer after measuring and is dried, the purpose of spilling water cleaning is silicon after removal is thinned
The impurity on piece surface.
Wherein, above-mentioned corrosive liquid is the nitric acid being mixed in a certain ratio, hydrofluoric acid, glacial acetic acid and pure water, the corrosive liquid
It can be good at carrying out corrosion thinning to silicon wafer, mixed proportion here is that example is mixed by volume, according to volume ratio
It is mixed for the ratio of 10-20:5-10:1-10:1-10.
2) it spreads pre-treatment: alkali process successively being carried out to the silicon wafer after being thinned, spilling water cleaning, acid cleaning, spilling water cleaning, is got rid of
It is dry, it is therefore an objective to which that the surface mechanical damage for removing silicon wafer removes the impurity such as metal ion and the organic solvent of silicon chip surface, that is,
A. the silicon wafer after being thinned is placed in lye and handles, which is potassium hydroxide solution, and the hydroxide
The temperature of potassium solution is 40-80 DEG C, and the alkali process time is in 5-20min, and alkali process here is level-one alkali process, it is,
Carry out an alkali process；
B. silicon wafer is put into progress spilling water cleaning in pure water after the completion of alkali process, removes the lye of silicon chip surface, here
Cleaning includes three steps, is first cleaned using spilling water, and spilling water cleaning here is cleaned using two-stage spilling water, that is, carries out spilling water twice
Cleaning, using ultrasonic spilling water cleaning after the cleaning of two-stage spilling water, ultrasonic spilling water cleaning is using primary ultrasonic spilling water cleaning, ultrasonic spilling water
It is cleaned after cleaning using spilling water, is cleaned here using two-stage spilling water, the time of every step cleaning is in 5-20min, here here
The cleaning of two-stage spilling water refer to that silicon wafer carries out water twice and cleans, sufficiently remove other solution impurities of silicon chip surface, level-one is super
The cleaning of sound spilling water refers to carrying out primary ultrasonic spilling water cleaning；
C. the silicon wafer cleaned up is placed in acid solution and carries out sour processing, acid solution used is nitric acid solution, temperature one
As be 60-100 DEG C, acid processing the time be 5-20min in, here acid processing be three-level acid handle, it is, carry out three hypo acids
The time of processing, every hypo acid processing is all identical；
D. after the completion of acid processing, silicon wafer is put into pure water and carries out spilling water cleaning and dries, removes the acid solution of silicon chip surface,
Here spilling water scavenging period is in 5-20min, and spilling water cleaning here is that level Four spilling water cleans, and is overflow it is, carrying out four times
The time of water cleaning, each spilling water cleaning is identical；
E. the silicon wafer cleaned up is dried, so that there is no the impurity such as water for silicon chip surface.
3) print diffusion source: using silk-screen printing technique, to treated, silicon wafer one side prints phosphorous diffusion source, another side print
Brush boron diffusion source or boron aluminum extension dissipate source, specifically includes the following steps:
A. in silicon wafer one side printing phosphorous diffusion source: phosphorous diffusion source being sprayed on halftone, which is woven by engineering plastics
It forms, silicon wafer is placed in below halftone, applies pressure at a certain angle above halftone with scraper, phosphorous diffusion source is printed to silicon
Piece surface, the angle of scraper here are 45 ° -75 °, printing pressure 30N-120N, and version spacing is 1-3mm, and print speed printing speed is
50-300mm/S, scraper height are 1-3mm, and scraper hardness is 40-80HRC；
B. the silicon wafer for printing phosphorous diffusion source is placed in baking oven, phosphorous diffusion source is dried, the drying time according to
The number to be printed of phosphorous diffusion source determines that time for generally toasting is 5-25min, and temperature is 90-180 DEG C；
C. boron diffusion source or boron aluminum extension are dissipated source by the processing step of step B, step C to print to silicon wafer another side, is gone forward side by side
Row baking, temperature are 90-180 DEG C, baking time 5-15min；
D. after the completion of toasting, upper Al is sprayed on silicon wafer two sides2O3Powder or silicon powder.
4) lamination fills boat: by silicon wafer, opposite lamination fills boat two-by-two, i.e., by silicon wafer boron source face or boron silicon source face and boron source face or
Boron silicon source face is opposite, carries out lamination for phosphorus source face is opposite with phosphorus source face, is put into silicon carbide boat after lamination, and before and after being carbonized boat
Baffle is placed in position, and silicon wafer is compressed, and can make full use of the space in diffusion furnace after carrying out low pressure diffusion in this way, and work
It is high-efficient, multiple batches of silicon wafer can be once diffused；
5) low pressure is spread: will be carried out low pressure diffusion in diffusion furnace mounted in the silicon wafer of carbonization boat, is made uniform PN junction；Its
In, the step mesolow diffusion the specific steps are；
A. the carbonization boat equipped with silicon wafer is placed in diffusion furnace, is placed in the flat-temperature zone of the diffusion furnace, used after closing fire door
Air pressure in diffusion furnace is evacuated to negative pressure, generally 10-101Kpa by vacuum pump；
B. diffusion furnace temperature is risen into 1250 DEG C of -1300 DEG C of progress constant temperature diffusions by 550 DEG C -650 DEG C, constant temperature time is
10-30h；
C. after spreading, diffusion furnace temperature is down to 550 DEG C -650 DEG C, and the carbonization boat of containing silicon slice is pulled out diffusion furnace.
6) diffusion post-processing: the silicon wafer after diffusion being placed in acid and is diffused post-processing, and silicon wafer is washed by water and made after separating
With nitration mixture clean the surface, silicon chip surface phosphorus, Pyrex after diffusion are removed.The acid for being used as diffusion post-processing in the step is hydrogen
Fluorspar acid solution is the nitric acid, hydrofluoric acid and glacial acetic acid being mixed in a certain ratio to the nitration mixture that silicon chip surface carries out cleaning, here
One be set to according to volume ratio be 6-15:10-20:30-40 ratio mixed.
Negative pressure diffusion technique of silicon wafer is that the techniques such as subsequent silicon wafer glass is blunt are prepared.
Using the PN junction result of an above-mentioned negative pressure diffusion technique are as follows: 40-60 μm of boron knot, 90-120 μm of aluminium knot, phosphorus knot
40-60μm.Make the resistance to electric discharge result of sample are as follows: 800-1500V.
Experiment proves that result it is found that using a negative pressure diffusion technique make silicon wafer, PN junction is uniform, and consistency is good,
Negative-pressure operation is carried out in the warming-up section of phosphorus source volatilization, the phosphorus source volatilized is discharged, which as early as possible, reduces the effect that phosphorus source returns source, silicon wafer
It is small that edge returns source amount.
The advantages and positive effects of the present invention are: due to the adoption of the above technical scheme, being existed using silk-screen printing technique
Silicon wafer two sides prints phosphorous diffusion source, boron diffusion source or boron aluminum extension respectively and dissipates source, so that the coating process of silicon wafer liquid source obtains letter
Change, and the process-cycle is reduced；A negative pressure diffusion technique is used after liquid source coating, mitigates silicon chip edge and returns source situation,
And the diffusion process steps simplify, and improve diffuser efficiency；Silicon wafer liquid source One Diffusion Process is carried out using the process, so that
The PN junction of production is uniform, so that the processing cost of silicon wafer reduces.
One embodiment of the present invention has been described in detail above, but the content is only preferable implementation of the invention
Example, should not be considered as limiting the scope of the invention.It is all according to all the changes and improvements made by the present patent application range
Deng should still be within the scope of the patent of the present invention.
Claims (10)
1. a kind of negative pressure diffusion technique of silicon wafer, characterized by the following steps:
1) low pressure is spread: the silicon wafer behind coating diffusion source is carried out low pressure diffusion in diffusion furnace.
2. negative pressure diffusion technique of silicon wafer according to claim 1, it is characterised in that: the low pressure in the step 1) expands
Dissipate specific steps are as follows:
A. the silicon wafer behind the coating diffusion source is placed in the diffusion furnace, and air pressure in the diffusion furnace is evacuated to negative pressure.
3. negative pressure diffusion technique of silicon wafer according to claim 2, it is characterised in that: further include after the step a
Following steps:
B. the diffusion furnace temperature is risen into 1250 DEG C of -1300 DEG C of progress constant temperature diffusions, constant temperature time 10-30h；
C. after spreading, the diffusion furnace temperature is down to 550 DEG C -650 DEG C and is come out of the stove.
4. negative pressure diffusion technique of silicon wafer according to claim 1-3, it is characterised in that: the step 1) is negative
It further include printing diffusion source before pressure diffusing step.
5. negative pressure diffusion technique of silicon wafer according to claim 4, it is characterised in that: the printing diffusion source uses silk
Net printing technology, specifically includes the following steps:
A. in the silicon wafer one side printing phosphorous diffusion source by being handled before spreading: the phosphorous diffusion source is sprayed on halftone, it is described
Silicon wafer is placed in below the halftone, is printed the phosphorous diffusion source to the silicon chip surface with scraper；
B. the silicon wafer for printing the phosphorous diffusion source is placed in baking oven, the phosphorous diffusion source is dried；
C. boron diffusion source or boron aluminum extension are dissipated source by the technique of step B, step C to print to the silicon wafer another side, and is dried
It is roasting；
D. upper Al is sprayed on the silicon wafer two sides2O3Powder or silicon powder.
6. negative pressure diffusion technique of silicon wafer according to claim 5, it is characterised in that: when drying in the step B
Between according to diffusion source number to be printed determine.
7. according to claim 4-6 negative pressure diffusion technique of described in any item silicon wafers, it is characterised in that: the printing diffusion
It further include lamination dress boat behind source.
8. according to claim 7 negative pressure diffusion technique of described in any item silicon wafers, it is characterised in that: the lamination fills boat
The step of are as follows: silicon wafer boron source face or boron silicon source face is opposite with boron source face or boron silicon source face, by phosphorus source face and phosphorus source face phase
Boat is filled to lamination is carried out.
9. negative pressure diffusion technique of silicon wafer according to claim 1-8, it is characterised in that: further include after diffusion
Silicon wafer after diffusion, is specially placed in acid and is diffused post-processing by diffusion post-processing.
10. negative pressure diffusion technique of silicon wafer according to claim 8, it is characterised in that: in the diffusion post-processing
Acid is hydrofluoric acid.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111710597A (en) * | 2020-06-30 | 2020-09-25 | 山东宝乘电子有限公司 | Method for manufacturing silicon rectifying chip substrate by utilizing boron-phosphorus one-step diffusion |
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| CN101944554A (en) * | 2010-09-16 | 2011-01-12 | 浙江大学 | Boron-aluminum common gettering method for silicon slice |
| CN104091857A (en) * | 2014-06-30 | 2014-10-08 | 欧贝黎新能源科技股份有限公司 | Low-pressure variable-temperature diffusion method of nanometer textured polycrystalline silicon solar cell |
| CN105261670A (en) * | 2015-08-31 | 2016-01-20 | 湖南红太阳光电科技有限公司 | Low-pressure diffusion technology for crystalline silicon cell |
| CN205347629U (en) * | 2015-12-07 | 2016-06-29 | 广东爱康太阳能科技有限公司 | Low pressure high temperature diffusion stove |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111710597A (en) * | 2020-06-30 | 2020-09-25 | 山东宝乘电子有限公司 | Method for manufacturing silicon rectifying chip substrate by utilizing boron-phosphorus one-step diffusion |
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