CN109307831B - TDDB test method for gate oxide layer in integrated circuit - Google Patents

TDDB test method for gate oxide layer in integrated circuit Download PDF

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CN109307831B
CN109307831B CN201811114610.9A CN201811114610A CN109307831B CN 109307831 B CN109307831 B CN 109307831B CN 201811114610 A CN201811114610 A CN 201811114610A CN 109307831 B CN109307831 B CN 109307831B
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breakdown
electric field
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CN109307831A (en
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杨盛玮
韩坤
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Yangtze Memory Technologies Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
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Abstract

The invention relates to a TDDB testing method of a gate oxide layer in an integrated circuit. The test method comprises the following steps: obtaining the breakdown field strength determined by performing a slope voltage test on the grid oxide layer; performing TDDB test on the grid oxide layer under a test electric field to obtain breakdown time; determining an electric field acceleration factor according to the ramp rate of the ramp voltage test, the breakdown field strength, the breakdown time and the test electric field strength; and calculating the service life of the grid oxide layer by using the electric field acceleration factor.

Description

TDDB test method for gate oxide layer in integrated circuit
Technical Field
The present invention relates to reliability testing of semiconductor devices, and more particularly, to a Time-Dependent Dielectric Breakdown (TDDB) testing method for a gate oxide layer in an integrated circuit.
Background
In the manufacture of integrated circuits, a Gate Oxide (Gate Oxide) is the most important part of a basic unit device, and the quality of the Gate Oxide determines the performance of the device.
Methods for reliability estimation of a gate oxide layer include a Voltage ramp (Voltage ramp) test and a Time Dependent Dielectric Breakdown (TDDB) test, hereinafter referred to as Vramp test and TDDB test. An assessment of the reliability of the gate oxide layer can be made by the Vramp test and the TDDB test. However, some methods to obtain gate oxide lifetime in integrated circuits require 3 sets of TDDB tests (3E) using 3 different electric field strengths, which requires a significant amount of time.
Disclosure of Invention
The invention aims to provide a TDDB testing method of a grid oxide layer in an integrated circuit, which can obviously shorten the testing time.
The invention adopts a technical scheme for solving the technical problems and provides a method for testing the TDDB of a grid oxide layer in an integrated circuit, which comprises the following steps: obtaining the breakdown field strength determined by performing a slope voltage test on the grid oxide layer; performing TDDB test on the grid oxide layer under a test electric field to obtain breakdown time; determining an electric field acceleration factor according to the ramp rate of the ramp voltage test, the breakdown field strength, the breakdown time and the test electric field strength; and calculating the service life of the grid oxide layer by using the electric field acceleration factor.
In an embodiment of the present invention, the breakdown field strength is an average breakdown field strength determined according to a breakdown field strength distribution.
In an embodiment of the present invention, the step of performing a TDDB test on the gate oxide layer under a test electric field to obtain a breakdown time includes: obtaining a breakdown time distribution under the test electric field; and determining the breakdown time according to the breakdown time distribution.
In an embodiment of the invention, in the step of obtaining the breakdown time distribution under the test electric field, the breakdown time distribution under a single test electric field strength is obtained.
In an embodiment of the invention, the breakdown time distribution is a weber distribution.
In an embodiment of the present invention, a formula for determining the electric field acceleration factor according to the ramp rate of the ramp voltage test, the breakdown field strength, the breakdown time, and the test electric field strength is as follows: TF ═ γ · R · exp [ γ (E)bd-E)]Wherein TF is the breakdown time, γ is the electric field acceleration factor, R is the ramp rate, EbdAnd E is the breakdown field strength and the test electric field strength.
By adopting the technical scheme, the electric field acceleration factor gamma can be determined only by 1 group of TDDB tests, so that the test time is greatly shortened. In contrast, some of the referenced methods require 3 sets of TDDB tests (3E) with 3 different electric field strengths to determine the electric field acceleration factor γ. In particular, the invention can select the electric field strength with shorter test time to test, thereby shortening the test time more obviously.
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In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a schematic diagram of an apparatus for TDDB testing of a gate oxide layer in an integrated circuit according to an embodiment of the invention.
FIG. 2 is a flowchart illustrating a TDDB testing method for a gate oxide layer in an integrated circuit according to an embodiment of the invention.
Fig. 3 is a graph of breakdown voltage distribution obtained from Vramp testing in accordance with one embodiment of the present invention.
Fig. 4 is a distribution graph of breakdown time obtained from a TDDB test according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below. As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
It will be understood that when an element or module is described as "connected" to other elements, modules or blocks, it can be directly connected or in communication with the other elements, modules or blocks or intervening elements, modules or blocks may be present unless the context clearly dictates otherwise. As used herein, the term "and/or" can include any and all combinations of one or more of the associated listed items.
Embodiments of the present invention describe semiconductor devices, such as methods for reliability testing of gate oxide layers, and in particular methods for TDDB testing of gate oxide layers. Reliability tests typically include Vramp tests and TDDB tests. The Vramp test method is as follows: selecting a group of samples, and applying a slope voltage on a grid oxide layer until the grid is oxidized and broken down, wherein the voltage applied on the grid oxide layer is the breakdown voltage of the grid oxide layer; comparing such a set of breakdown voltages to industry standards (a common industry standard is 2.3 times the operating voltage) to determine whether the measured gate oxide layer is affected by extrinsic factors (e.g., particle contamination, etc.); if the breakdown voltage is greater than the industrial standard, the tested grid oxide layer meets the reliability requirement of the ramp voltage test, and the service life characteristic of the tested grid oxide layer can be determined by utilizing the TDDB test.
The TDDB testing method comprises the following steps: applying TDDB test voltage on a grid oxide layer to be tested of a semiconductor device test structure, breaking down the grid oxide layer after time t, and calculating time-dependent dielectric breakdown time of the grid oxide layer by using a corresponding life model and an area-dependent life scaling formula.
FIG. 1 is a schematic diagram of an apparatus for TDDB testing of a gate oxide layer in an integrated circuit according to an embodiment of the invention. Referring to fig. 1, the testing apparatus 100 of the present embodiment may include a power supply 110, a plurality of connection terminals 120, and a control device 130. The power supply 110 may be used to apply a test voltage. The connection terminal 120 connects the power source 110 and the gate oxide layer 11 of the semiconductor device under test 10 for applying a voltage to the gate oxide layer 11 to constitute a test electric field. Although only 2 connection terminals are shown in the drawings, it is understood that the number of connection terminals 120 may be determined according to the number of semiconductor devices 10 that need to be simultaneously tested. In embodiments of the present invention, semiconductor device 10 may be a memory, a processor, a hybrid device, or other device.
The control device 130 is connected to a power source for controlling the performance of the test procedure. For example, the test voltage output by the power supply 110 is variable and is controlled by the control device 130. The control device 130 may have a Microprocessor (MPU)131 and a memory 132. MPU131 may execute a series of computer instructions to implement the control process. A memory 132 may be connected to the MPU131 for storing the aforementioned computer instructions, as well as intermediate data and/or result data during the test. In one example, the control device 130 may be a computer, such as a personal computer, a workstation, or a server.
In an embodiment of the present invention, the test apparatus 100 may be used to perform reliability tests of semiconductor devices, such as Vramp tests and/or TDDB tests, depending on the configuration of the control device 130.
In the Vramp test, a Ramp voltage with a certain Ramp Rate (Ramp Rate) R may be applied to the gate oxide layer 11 until the gate oxide layer 11 is broken down, and the voltage applied to the gate oxide layer 11 is the breakdown voltage of the gate oxide layer. Fig. 3 is a graph of breakdown voltage distribution obtained from Vramp testing in accordance with one embodiment of the present invention. To facilitate subsequent calculations, the breakdown voltage may be converted into a series of breakdown field strengths EbdThe distribution of these breakdown field strengths typically follows a weibull distribution (weibull distribution). The mean breakdown field strength (E) can be determined from the breakdown field strength distributionbd63)。
The average breakdown field strength obtained in the Vramp test will be used for lifetime calculations in the TDDB test.
FIG. 2 is a flowchart illustrating a TDDB testing method for a gate oxide layer in an integrated circuit according to an embodiment of the invention. The method shown in fig. 2 can be performed in the testing apparatus 100 shown in fig. 1, but is not limited thereto. The method shown in fig. 2 may also be performed in other test devices. In some embodiments, some of the steps in the method shown in FIG. 2 may be performed manually. The TDDB test method of the present embodiment is described below with reference to fig. 2.
At step 202, the breakdown field strength determined by performing a Vramp test on the gate oxide layer is obtained.
In this step, the breakdown field strength of the gate oxide layer determined after the Vramp test can be obtained. The breakdown field strength is, for example, an average breakdown field strength Ebd63 determined from the breakdown field strength distribution.
Taking the test apparatus 100 of fig. 1 as an example, the control device 130 may perform Vramp test in advance to determine the average breakdown field strength Ebd63And then stored in the memory 132. In this step, the average breakdown field strength E may be obtained from the memory 132bd63。
In step 204, a TDDB test is performed on the gate oxide layer under the test electric field to obtain a breakdown time.
FIG. 4 is a distribution of breakdown times obtained from TDDB testing according to one embodiment of the invention, the distribution of these breakdown times typically conforms to a Weibull distribution (Weibull distribution). the average breakdown time (Tbd63) can be determined from the breakdown time distribution, and other parameters related to lifetime calculations can be determined, such as the value of Tbd0.1 at a probability of 0.1% for a Weibull distribution, and the degree of Weibull dispersion (Weibull Slope) β.
Taking the test apparatus 100 of fig. 1 as an example, the control device 130 can control the power supply 110 to perform TDDB test and determine the breakdown time distribution, the microprocessor 131 in the control device 130 can obtain the average breakdown time Tbd63 through operation and then store the obtained average breakdown time Tbd63 in the memory 132, and the microprocessor 131 can also obtain Tbd0.1 and β and store the obtained average breakdown time Tbd in the memory 132.
At step 206, an electric field acceleration factor is determined based on the ramp rate, the breakdown field strength, the breakdown time, and the test electric field strength of the ramp voltage test.
In this step, various parameters, such as ramp rate R of the ramp voltage test, breakdown field strength (in terms of average breakdown field strength E), can be obtained according to the foregoingbd63Representative), breakdown time (in average breakdown time T)bd63Representative) and the test electric field strength E to determine the electric field acceleration factor gamma.
Taking the test apparatus 100 of fig. 1 as an example, the microprocessor 131 in the control device 130 may calculate the electric field acceleration factor γ according to various parameters that have been obtained, and may store it in the memory 132.
At step 208, the lifetime of the gate oxide layer is calculated using the electric field acceleration factor.
In this step, the lifetime of the gate oxide layer can be calculated using the electric field acceleration factor γ.
Taking the test apparatus 100 of fig. 1 as an example, the microprocessor 131 in the control device 130 may calculate the lifetime of the gate oxide layer according to various obtained parameters, including the electric field acceleration factor γ, and may store the calculation result in the memory 132. An exemplary calculation formula is:
Figure BDA0001810187740000051
wherein Tbd0.1 is the corresponding Tbd value at 0.1% of the Weber distribution probability, β Weber discrete degree (Weibull slope), EstrTo test the field strength of the electric field, EopFor the field strength of the operating electric field, RatioareaIs the area ratio of the chip and the test structure.
Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. For example, step 202 described above may be performed after step 204. Meanwhile, other operations are added to or removed from these processes.
In this embodiment, only a single test voltage needs to be applied to the gate oxide layer to form a single test electric field strength, and then the breakdown time distribution under the single test electric field strength is detected in step 204. At step 206, an electric field acceleration factor γ may be calculated based on the ramp rate, the breakdown field strength, the breakdown time, and the test electric field strength of the ramp voltage test. An exemplary calculation formula is:
TF＝γ·R·exp[γ(Ebd-E)](2)
wherein TF is the breakdown time, gamma is the electric field acceleration factor, R is the ramp rate, EbdFor breakdown field strength, E is the test electric field strength.
The principle of using equation (2) is that the TDDB for gate oxide layers with a thickness (Tox) > 4nm all satisfy the following E-model:
TF＝A0·exp(-γE0x) (3)
TF represents the breakdown time, A0The coefficient is gamma, which represents the electric field acceleration factor, the natural logarithm of the time is in a linear relationship with the electric field, the slope of the time is the electric field acceleration factor gamma, and Eox is the electric field strength of the gate oxide layer.
If the Vramp test procedure is considered as a plurality of short TDDB stress with gradually increasing applied electric fields, the Vramp test can be associated with the TDDB test to obtain the above equation (2).
The electric field acceleration factor γ is a key parameter obtained in the TDDB test. Some reference methods require 3 sets of TDDB tests (3E) with 3 different electric field strengths to determine the electric field acceleration factor γ. In contrast, the present embodiment can determine the electric field acceleration factor γ only by 1 set of TDDB test (1E), which greatly shortens the test time. In particular, the present embodiment can select an electric field strength with a shorter test time to perform the test, so that the test time can be shortened more significantly. For example, this embodiment can reduce the test time from 38 hours to 4 hours, which is about 10% of the original time.
In an embodiment of the present invention, the control device 130 is configured to implement step 202-208. For example, the microprocessor 131 may execute a series of computer instructions to implement step 202-208. These computer instructions may be stored in memory 132 and loaded into microprocessor 131 when needed.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims (5)

1. A TDDB testing method of a gate oxide layer in an integrated circuit comprises the following steps:
obtaining the breakdown field strength determined by performing a slope voltage test on the grid oxide layer;
performing TDDB test on the grid oxide layer under a test electric field to obtain breakdown time;
determining an electric field acceleration factor according to the ramp rate of the ramp voltage test, the breakdown field strength, the breakdown time and the test electric field strength; and
calculating the service life of the grid oxide layer by using the electric field acceleration factor;
wherein, the formula for determining the electric field acceleration factor according to the ramp rate of the ramp voltage test, the breakdown field strength, the breakdown time and the test electric field strength is as follows:
TF＝γ·R·exp[γ(Ebd-E)]
wherein TF is the breakdown time, γ is the electric field acceleration factor, R is the ramp rate, EbdAnd E is the breakdown field strength and the test electric field strength.
2. The TDDB testing method of claim 1, wherein the breakdown field strength is an average breakdown field strength determined from a breakdown field strength distribution.
3. The TDDB testing method of claim 1, wherein performing TDDB testing on the gate oxide layer under a test electric field to obtain a breakdown time comprises:
obtaining a breakdown time distribution under the test electric field; and
and determining the breakdown time according to the breakdown time distribution.
4. The TDDB testing method of claim 3, wherein in the step of obtaining the breakdown time distribution under the test electric field, the breakdown time distribution under a single test electric field strength is obtained.
5. The TDDB testing method of claim 3, wherein the breakdown time distribution is a weber distribution.
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