CN109274401B - Spread spectrum signal source - Google Patents

Spread spectrum signal source Download PDF

Info

Publication number
CN109274401B
CN109274401B CN201811320992.0A CN201811320992A CN109274401B CN 109274401 B CN109274401 B CN 109274401B CN 201811320992 A CN201811320992 A CN 201811320992A CN 109274401 B CN109274401 B CN 109274401B
Authority
CN
China
Prior art keywords
spread spectrum
signal
frequency
signal source
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811320992.0A
Other languages
Chinese (zh)
Other versions
CN109274401A (en
Inventor
方聆郦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Tianmao Technology Co ltd
Original Assignee
Chengdu Tianmao Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Tianmao Technology Co ltd filed Critical Chengdu Tianmao Technology Co ltd
Priority to CN201811320992.0A priority Critical patent/CN109274401B/en
Publication of CN109274401A publication Critical patent/CN109274401A/en
Application granted granted Critical
Publication of CN109274401B publication Critical patent/CN109274401B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits

Abstract

The invention discloses a spread spectrum signal source which is mainly divided into spread spectrum modulation and carrier modulation in principle, and a singlechip plays a roleUnder the action of core control, the singlechip is connected with four peripherals in total: the system comprises a keyboard, a liquid crystal display, a clock generator and an FPGA, wherein the clock generator is connected with the FPGA, and the FPGA is further connected with a carrier modulation. The output signal of the spread spectrum signal source provided by the invention has high carrier and code rate clock rejection ratio, and the frequency stability is more than or equal to 106And the output is stable, good data is provided for the research of the spread spectrum signal detection and acquisition technology algorithm at the back end, and meanwhile, the signal source has the advantage of multi-parameter adjustability, and can conveniently simulate various signals in the real environment, thereby greatly facilitating the research, verification and improvement of the algorithm.

Description

Spread spectrum signal source
Technical Field
The invention relates to the technical field of measurement and control communication, in particular to a spread spectrum signal source.
Background
Spread spectrum communication is a novel communication system, has the advantages of strong anti-interference capability, low interception rate, code division multiple access, signal concealment, confidentiality, easy ranging and the like, and is an important development direction in the communication field. Because of these advantages, spread spectrum communications have received great attention from military. In order to cooperate with the research on the estimation of important parameters such as code rate, carrier frequency, pseudo code sequence and the like of a spread spectrum signal, a signal source capable of accurately simulating a direct sequence spread spectrum signal in a real environment is urgently needed, the signal source needs to be capable of generating a BPSK spread spectrum signal modulated by a direct sequence and adding the BPSK spread spectrum signal to white noise to form a continuous output signal with adjustable signal-to-noise ratio, and parameters such as the carrier frequency, the pseudo code rate, the pseudo code length, the pseudo code sequence and the like can be respectively modulated.
Disclosure of Invention
In order to solve the problems in the prior art, the invention aims to provide a spread spectrum signal source which has the advantages of high error precision and capability of completing switching of different code rates.
In order to achieve the purpose, the invention adopts the technical scheme that: a spread spectrum signal source is mainly divided into spread spectrum modulation and carrier modulation in principle, a single chip microcomputer plays a role in core control, and the single chip microcomputer is connected with four peripheral devices in total: the system comprises a keyboard, a liquid crystal display, a clock generator and an FPGA, wherein the clock generator is connected with the FPGA, and the FPGA is further connected with a carrier modulation.
Preferably, the spread spectrum modulation is mainly completed by a programmable logic device FPGA, five groups of PCM codes and eight groups of PN codes are respectively stored in two EPROMs, a liquid crystal display screen provides an interface for a user to prompt the user to input various parameters, and the singlechip generates addresses according to the groups input by the user from a keyboard; the FPGA extracts data from the EPROM according to the address provided by the singlechip and the clock generated by the clock generator, completes spread spectrum modulation in the FPGA, and then sends the data out for carrier modulation.
The spread spectrum modulation adopts direct sequence spread spectrum modulation, and the output signal waveform is as follows:
Figure GDA0002949943300000021
in the formula:
Figure GDA0002949943300000022
Tcis the pseudo-code chip width and,
Figure GDA0002949943300000023
nTn≤t≤(n+1)Tnn is an integer, Tn is a clock period; the clock generator is a generator with model number AD9850, AD9850 uses advanced direct digital frequency synthesis (DDS) technology, and AD9850 generates a clock signal of 5.23264 MHz.
Preferably, the carrier modulation uses Binary Phase Shift Keying (BPSK), and the expression of the BPSK signal is:
Figure GDA0002949943300000024
in the formula:
Figure GDA0002949943300000025
s is the power of the carrier signal, omega0Representing angular frequency, a direct spread BPSK signal can be represented as:
Figure GDA0002949943300000026
in the formula: c (u, t) is an m sequence; d (u, t) is signal data; u is a random variable.
The carrier is generated by a phase-locked loop circuit, BPSK modulation is realized by a programmable frequency synthesizer, and the change of the output signal-to-noise ratio is realized by adjusting the gain of the AD 9854.
The AD9854 is a device which adopts DDS technology and high integration, and is matched with two high-speed and high-performance orthogonal digital-to-analog converters and a comparator in the AD9854 to complete the I, Q two-path frequency synthesis function which is digitally programmable, the AD9854 can complete the modulation functions of SINGIE-TONE, FSK, RANPED FSK, CHIRP, BPSK and the like, the high-speed DDS kernel innovative by the AD9854 provides 48-bit frequency resolution, the circuit structure of the AD9854 allows two-path orthogonal outputs up to 150MHz to be generated simultaneously, the output frequency can jump at the speed of 100 Mm new frequency points per second under the digital adjustment, two 12-bit multipliers can realize programmable amplitude modulation, output shaping keying and accurate orthogonal output amplitude control, a programmable 4-20 times reference clock multiplier circuit of the AD9854 can internally generate a clock up to 300MHz by using a lower-frequency external reference clock two, when the AD9854 works in a parallel working mode, 8 data lines and 6 address lines are connected with the single chip microcomputer, and the frequency control word FTW of the AD9854 is Fout×248the/CLKIN finishes the simulation of Doppler effect by continuously changing the frequency conversion word (FTW) of the AD9854 through the singlechip, and finishes the control of output amplitude by writing an internal register of the AD9854 through the singlechip.
Preferably, the phase-locked loop circuit is composed of a phase-locked loop MC145151 and a voltage-controlled oscillator MC1648, and both a code rate clock and a carrier frequency are generated by the phase-locked loop circuit; the MC145151 is a low power consumption phase locked loop based on CMOS technology, and the frequency division number range is as follows: the reference frequency can be provided by an external crystal or an external clock, the signal source is used for increasing the stability of the frequency, the high-stability crystal is used as the reference clock, the voltage-controlled oscillator is provided by an external circuit MC1648 and provides a peripheral adjusting circuit, the MC1648 outputs square waves or sine waves, and the highest frequency reaches 225 MHz.
The center frequency of a pseudo code rate clock is 2MHz, the adjusting range is 1-3 MHz, the step length is 100KHz, a peripheral circuit of an MC1648 is adjusted to enable an output signal to be a square wave, the data signal code rate is 1/N of the pseudo code rate, wherein N is the length of an m sequence, a serial output clock of the data signal is 1/N of the m sequence, the center frequency of a carrier is 6MHz, the adjusting range is 3-9 MHz, the step length is 100KHz, and the peripheral circuit of the MC1648 is adjusted to enable the output signal to be a sine wave.
Preferably, in order to ensure the sampling and transmission of the subsequent circuit, the phase-modulated sinusoidal signal needs to be filtered and shaped, and the band-pass filter is realized by using an operational amplifier; the white noise generation principle is that a Zener diode with avalanche effect is used to generate noise, and then the noise is amplified by a broadband amplifier and added with a spread spectrum signal.
Preferably, data transmission is realized by using the IDT7205 as a buffer interface, the IDT7205 is a FIFO type asynchronous read-write memory chip, the capacity is 8192 × 9bit, the access time is 12ns, three flag bits of empty, half full and full are provided, the maximum power consumption is 660mW, the operating voltage is +5V, the IDT7205 writes data transmitted from a PC into the IDT7205 in an interrupt mode, and the EMP7128 continuously reads the data from the IDT7205 through a read port to perform parallel-serial conversion and spread spectrum modulation.
Preferably, the control part realizes the control of the whole signal source by LPC2104, including the setting of carrier frequency, pseudo code rate and pseudo code sequence, and simultaneously performs data transmission between PC and the signal source through a serial port, the LPC2104 has an ARM7TDM1-S processor, the working frequency of the CPU can reach 60MHz, and 32-bit ARM instructions and 16-bit THUMB instructions are supported; the ARM7TDM1-S processor uses a three-stage pipeline to increase the speed of the processor instruction stream, so that several operations can be performed simultaneously, the processing and memory system can operate continuously, the instruction execution speed of 0.9MIPs/MHz can be provided, and the on-chip RAM of 16Kbit is convenient for data processing and caching.
Preferably, the autocorrelation function of the pseudo-random sequence has an autocorrelation function similar to white noise, and is expressed by:
Figure GDA0002949943300000041
on the graph is a triangle: amplitude is high as A2Time of-TcTo TcT represents a time period, f represents a crystal oscillation frequency,
the power spectrum of the pseudorandom sequence can be obtained by Fourier transform of the autocorrelation function:
Figure GDA0002949943300000042
the power spectrum is a [ sinx/x ]]2Pseudo noise spectrum of type 2/T bandwidthcI.e. 2RcTwice the pseudo code rate; the power spectrum of the spread spectrum signal obtained after the exclusive or of the pseudo-random code and the signal is the convolution result of the power spectrum of the pseudo-random sequence and the power spectrum of the signal, and as the signal code rate of the signal source is very low, the code period of the signal source is just equal to the time of one pseudo-code period length, the power spectrum of the signal is very narrow, and the power spectrum of the signal is just moved to each period spectrum line of the pseudo-power spectrum in a dressing mode during the convolution.
The output signal of the spread spectrum signal source provided by the invention has high carrier and code rate clock rejection ratio, and the frequency stability is more than or equal to 106And the output is stable, good data is provided for the research of the spread spectrum signal detection and acquisition technology algorithm at the back end, and meanwhile, the signal source has the advantage of multi-parameter adjustability, and can conveniently simulate various signals in the real environment, thereby greatly facilitating the research, verification and improvement of the algorithm.
Drawings
FIG. 1 is a schematic block diagram of a spread spectrum signal source according to an embodiment of the present invention;
fig. 2 is a flowchart of a main procedure of a spread spectrum signal source according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Example 1:
as shown in fig. 1-2, a spread spectrum signal source is mainly divided into spread spectrum modulation and carrier modulation in principle, and a single chip plays a role of core control, and the single chip is connected with four peripheral devices in total: the system comprises a keyboard, a liquid crystal display, a clock generator and an FPGA, wherein the clock generator is connected with the FPGA, and the FPGA is further connected with a carrier modulation.
The spread spectrum modulation is mainly completed by a programmable logic device FPGA, five groups of PCM codes and eight groups of PN codes are respectively stored in two EPROMs, a liquid crystal display screen provides an interface for a user to prompt the user to input various parameters, and a singlechip generates addresses according to groups input by the user from a keyboard; the FPGA extracts data from the EPROM according to an address provided by the singlechip and a clock generated by a clock generator, completes spread spectrum modulation in the FPGA, and then sends the data out for carrier modulation;
the spread spectrum modulation adopts direct sequence spread spectrum modulation, and the output signal waveform is as follows:
Figure GDA0002949943300000061
in the formula:
Figure GDA0002949943300000062
Tcis the pseudo-code chip width and,
Figure GDA0002949943300000063
nTn≤t≤(n+1)Tnn is an integer, Tn is a clock period; the clock generator is a generator with model number AD9850, AD9850 uses advanced direct digital frequency synthesis (DDS) technology, and AD9850 generates a clock signal of 5.23264 MHz.
The carrier modulation uses Binary Phase Shift Keying (BPSK), and the expression of the BPSK signal is:
Figure GDA0002949943300000064
in the formula:
Figure GDA0002949943300000065
s is the power of the carrier signal, omega0Representing angular frequency, a direct spread BPSK signal can be represented as:
Figure GDA0002949943300000066
in the formula: c (u, t) is an m sequence; d (u, t) is signal data; u is a random variable;
the carrier is generated by a phase-locked loop circuit, BPSK modulation is realized by a programmable frequency synthesizer, and the change of the output signal-to-noise ratio is realized by adjusting the gain of the AD 9854.
The AD9854 is a device which adopts DDS technology and high integration, and is matched with two high-speed and high-performance orthogonal digital-to-analog converters and a comparator in the AD9854 to complete the I, Q two-path frequency synthesis function which is digitally programmable, the AD9854 can complete the modulation functions of SINGIE-TONE, FSK, RANPED FSK, CHIRP, BPSK and the like, the high-speed DDS kernel innovative by the AD9854 provides 48-bit frequency resolution, the circuit structure of the AD9854 allows two-path orthogonal outputs up to 150MHz to be generated simultaneously, the output frequency can jump at the speed of 100 Mm new frequency points per second under the digital adjustment, two 12-bit multipliers can realize programmable amplitude modulation, output shaping keying and accurate orthogonal output amplitude control, a programmable 4-20 times reference clock multiplier circuit of the AD9854 can internally generate a clock up to 300MHz by using a lower-frequency external reference clock two, when the AD9854 works in a parallel working mode, 8 data lines and 6 address lines are connected with the single chip microcomputer, and the frequency control word FTW of the AD9854 is Fout×248The frequency conversion word (FTW) of the AD9854 is continuously changed by the singlechip to complete the simulation of Doppler effect, and the output amplitude is controlled by writing the output amplitude into the AD9854 by the singlechipPartial registers.
The phase-locked loop circuit is composed of a phase-locked loop MC145151 and a voltage-controlled oscillator MC1648, and a code rate clock and a carrier frequency are both generated by the phase-locked loop circuit; the MC145151 is a low power consumption phase locked loop based on CMOS technology, and the frequency division number range is as follows: the reference frequency can be provided by an external crystal or an external clock, the signal source is used for increasing the stability of the frequency, the high-stability crystal is used as the reference clock, the voltage-controlled oscillator is provided by an external circuit MC1648 and provides a peripheral adjusting circuit, the MC1648 outputs square waves or sine waves, and the highest frequency reaches 225 MHz.
The center frequency of a pseudo code rate clock is 2MHz, the adjusting range is 1-3 MHz, the step length is 100KHz, a peripheral circuit of an MC1648 is adjusted to enable an output signal to be a square wave, the data signal code rate is 1/N of the pseudo code rate, wherein N is the length of an m sequence, a serial output clock of the data signal is 1/N of the m sequence, the center frequency of a carrier is 6MHz, the adjusting range is 3-9 MHz, the step length is 100KHz, and the peripheral circuit of the MC1648 is adjusted to enable the output signal to be a sine wave.
In order to ensure the sampling and transmission of the subsequent circuit, the phase-modulated sinusoidal signal needs to be filtered and shaped, and the band-pass filter is realized by using an operational amplifier; the white noise generation principle is that a Zener diode with avalanche effect is used to generate noise, and then the noise is amplified by a broadband amplifier and added with a spread spectrum signal.
The data transmission is realized by using an IDT7205 as a buffer interface, the IDT7205 is a FIFO type asynchronous read-write memory chip, the capacity is 8192 × 9bit, the access time is 12ns, three flag bits of empty, half full and full are provided, the maximum power consumption is 660mW, the working voltage is +5V, the IDT7205 writes data transmitted by an interrupt mode PC into the IDT7205, and EMP7128 continuously reads the data from the IDT7205 through a read-out port for parallel-serial conversion and spread spectrum modulation.
The control part is that LPC2104 realizes the control of the whole signal source, including the setting of carrier frequency, pseudo code rate and pseudo code sequence, and at the same time, data transmission between PC and the signal source is carried out through a serial port, LPC2104 has an ARM7TDM1-S processor, the CPU working frequency can reach 60MHz, and 32-bit ARM instruction and 16-bit THUMB instruction are supported; the ARM7TDM1-S processor uses a three-stage pipeline to increase the speed of the processor instruction stream, so that several operations can be performed simultaneously, the processing and memory system can operate continuously, the instruction execution speed of 0.9MIPs/MHz can be provided, and the on-chip RAM of 16Kbit is convenient for data processing and caching.
The autocorrelation function of the pseudo-random sequence has an autocorrelation function similar to white noise, and is expressed as:
Figure GDA0002949943300000081
on the coordinate diagram is a triangle: amplitude is high as A2Time of-TcTo TcT represents a time period, f represents a crystal oscillator frequency, and a power spectrum of a pseudo-random sequence can be obtained by Fourier transform of the autocorrelation function:
Figure GDA0002949943300000082
the power spectrum is a [ sinx/x ]]2Pseudo noise spectrum of type 2/T bandwidthcI.e. 2RcTwice the pseudo code rate; the power spectrum of the spread spectrum signal obtained after the exclusive or of the pseudo-random code and the signal is the convolution result of the power spectrum of the pseudo-random sequence and the power spectrum of the signal, and as the signal code rate of the signal source is very low, the code period of the signal source is just equal to the time of one pseudo-code period length, the power spectrum of the signal is very narrow, and the power spectrum of the signal is just moved to each period spectrum line of the pseudo-power spectrum in a dressing mode during the convolution.
Example 2:
as shown in fig. 1-3, this embodiment is improved on the basis of embodiment 1, the program initialization includes resetting of AD9850 and AD9854, setting default values of AD9850 and AD9854, setting initial values of group of data and pseudo code, the lcd displays eight display frames in total, the second to seventh screens prompt the user to input various parameters, and the parameters to be set include: the single chip computer works in interruption and inquiry mode simultaneously, if the inquiry shows that the reset key is pressed, the interruption is forbidden, the parameters are input again, and then the signal under the condition of simulating new parameters is switched on.
The output signal of the spread spectrum signal source provided by the invention has high carrier and code rate clock rejection ratio, and the frequency stability is more than or equal to 106And the output is stable, good data is provided for the research of the spread spectrum signal detection and acquisition technology algorithm at the back end, and meanwhile, the signal source has the advantage of multi-parameter adjustability, and can conveniently simulate various signals in the real environment, thereby greatly facilitating the research, verification and improvement of the algorithm.
Embodiment 2 the rest of the structure and the operation principle are the same as those of embodiment 1.
The above-mentioned embodiments only express the specific embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Claims (6)

1. A spread spectrum signal source is mainly divided into spread spectrum modulation and carrier modulation in principle, and a single chip microcomputer plays a role in core control, and is characterized in that the single chip microcomputer is connected with four peripheral devices in total: the system comprises a keyboard, a liquid crystal display, a clock generator and an FPGA (field programmable gate array), wherein the clock generator is connected with the FPGA, and the FPGA is further connected with a carrier modulation; the spread spectrum modulation is mainly completed by a programmable logic device FPGA, five groups of PCM codes and eight groups of PN codes are respectively stored in two EPROMs, a liquid crystal display screen provides an interface for a user to prompt the user to input various parameters, and a singlechip generates addresses according to groups input by the user from a keyboard; the FPGA extracts data from the EPROM according to an address provided by the singlechip and a clock generated by a clock generator, completes spread spectrum modulation in the FPGA, and then sends the data out for carrier modulation;
the spread spectrum modulation adopts direct sequence spread spectrum modulation, and the output signal waveform is as follows:
Figure FDA0002949943290000014
in the formula:
Figure FDA0002949943290000015
Tcis the pseudo-code chip width and,
Figure FDA0002949943290000016
nTn≤t≤(n+1)Tnn is an integer, Tn is a clock period; the clock generator is a generator with the model number AD9850, the AD9850 uses the advanced direct digital frequency synthesis (DDS), and the AD9850 generates a clock signal of 5.23264 MHz;
the carrier modulation adopts Binary Phase Shift Keying (BPSK), and the expression of the BPSK signal is as follows:
Figure FDA0002949943290000011
in the formula:
Figure FDA0002949943290000012
s is the power of the carrier signal, omega0Representing angular frequency, a direct spread BPSK signal can be represented as:
Figure FDA0002949943290000013
in the formula: c (u, t) is an m sequence; d (u, t) is signal data; u is a random variable;
the carrier is generated by a phase-locked loop circuit, BPSK modulation is realized by a programmable frequency synthesizer, and the change of the output signal-to-noise ratio is realized by adjusting the gain of the AD 9854.
2. The spread spectrum signal source of claim 1, wherein the pll circuit comprises a pll MC145151 and a vco MC1648, and the rate clock and the carrier frequency are generated by the pll circuit; the MC145151 is a low power consumption phase locked loop based on CMOS technology, and the frequency division number range is as follows: the signal source is used for increasing the stability of the frequency, the high-stability crystal is used as the reference clock, the voltage-controlled oscillator is provided by an external circuit MC1648 and provides a peripheral adjusting circuit, the MC1648 outputs square waves or sine waves, and the highest frequency reaches 225 MHz;
the center frequency of a pseudo code rate clock is 2MHz, the adjusting range is 1-3 MHz, the step length is 100KHz, a peripheral circuit of an MC1648 is adjusted to enable an output signal to be a square wave, the data signal code rate is 1/N of the pseudo code rate, wherein N is the length of an m sequence, a serial output clock of the data signal is 1/N of the m sequence, the center frequency of a carrier is 6MHz, the adjusting range is 3-9 MHz, the step length is 100KHz, and the peripheral circuit of the MC1648 is adjusted to enable the output signal to be a sine wave.
3. A spread spectrum signal source as claimed in claim 2, wherein the phase modulated sinusoidal signal is filtered and shaped to ensure sampling and transmission in subsequent circuits, and the band pass filter is implemented by using an operational amplifier; the white noise generation principle is that a Zener diode with avalanche effect is used to generate noise, and then the noise is amplified by a broadband amplifier and added with a spread spectrum signal.
4. The spread spectrum signal source according to claim 1, wherein data transmission is realized by using IDT7205 as a buffer interface, IDT7205 is a FIFO type asynchronous read-write memory chip, the capacity is 8192 × 9bit, the access time is 12ns, three flag bits of empty, half full and full are available, the maximum power consumption is 660mW, the operating voltage is +5V, IDT7205 writes data transmitted from PC into IDT7205 by an interrupt mode, and EMP7128 continuously reads data from IDT7205 by a read port for parallel-serial conversion and spread spectrum modulation.
5. The spread spectrum signal source of claim 2, wherein the control part is a LPC2104 for controlling the whole signal source, including setting the carrier frequency, the code rate of the pseudo code and the sequence of the pseudo code, and simultaneously performing data transmission between the PC and the signal source through the serial port, the LPC2104 has an ARM7TDM1-S processor, the CPU operating frequency can reach 60MHz, and supports 32-bit ARM instruction and 16-bit THUMB instruction; the ARM7TDM1-S processor uses a three-stage pipeline to increase the speed of the processor instruction stream, so that several operations can be performed simultaneously, the processing and memory system can operate continuously, the instruction execution speed of 0.9MIPs/MHz can be provided, and the on-chip RAM of 16Kbit is convenient for data processing and caching.
6. A spread spectrum signal source as claimed in claim 2, wherein the autocorrelation function of the pseudo-random sequence has an autocorrelation function similar to that of white noise, expressed as:
Figure FDA0002949943290000031
on the graph is a triangle: amplitude is high as A2Time of-TcTo TcT represents a time period, f represents a crystal oscillation frequency,
the power spectrum of the pseudorandom sequence can be obtained by Fourier transform of the autocorrelation function:
Figure FDA0002949943290000032
the power spectrum is a [ sinx/x ]]2Pseudo noise spectrum of type 2/T bandwidthcTwice the pseudo code rate.
CN201811320992.0A 2018-11-07 2018-11-07 Spread spectrum signal source Active CN109274401B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811320992.0A CN109274401B (en) 2018-11-07 2018-11-07 Spread spectrum signal source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811320992.0A CN109274401B (en) 2018-11-07 2018-11-07 Spread spectrum signal source

Publications (2)

Publication Number Publication Date
CN109274401A CN109274401A (en) 2019-01-25
CN109274401B true CN109274401B (en) 2021-05-04

Family

ID=65193104

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811320992.0A Active CN109274401B (en) 2018-11-07 2018-11-07 Spread spectrum signal source

Country Status (1)

Country Link
CN (1) CN109274401B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116155275B (en) * 2023-04-19 2023-07-28 成都世源频控技术股份有限公司 Broadband fine stepping phase-locked source with repeatable phase

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202217425U (en) * 2011-09-30 2012-05-09 北京化工大学 General modulation-demodulation experimental facility based on software radio
US20140241727A1 (en) * 2013-02-27 2014-08-28 Hock Gin Lim Communication between transceivers using in-band subcarrier tones
CN104679925A (en) * 2013-11-29 2015-06-03 哈尔滨功成科技创业投资有限公司 FPGA (Field Programmable Gate Array)-based spread spectrum signal generator
CN104569908A (en) * 2014-11-26 2015-04-29 哈尔滨金都太阳能科技有限公司 Radio navigation receiver digital signal processing platform based on DSP/FPGA
CN104570861A (en) * 2014-12-23 2015-04-29 天津光电通信技术有限公司 FPGA-based radio frequency signal source circuit

Also Published As

Publication number Publication date
CN109274401A (en) 2019-01-25

Similar Documents

Publication Publication Date Title
Murphy et al. Ask the application engineer—33 all about direct digital synthesis
CN101435862A (en) Up converter and signal processing method thereof
CN109274401B (en) Spread spectrum signal source
CN103227637A (en) Dither control circuit and devices having the same
CN109445514A (en) A kind of high-precision random frequency hopping DDS frequency synthesizer
CN104270148A (en) Broadband digital fixed-amplitude multi-system radio frequency signal source module
CN107247252A (en) Produce the device of multichannel coherent analog signal
WO2019148480A1 (en) Touch controller, demodulation method and touch control system
CN103701459A (en) Method for generating modulated signal and demodulated local oscillator signals
CN107436619B (en) High-precision low-cost digital sine wave generating device
CN111398796A (en) ADC performance test circuit, chip and equipment
CN208689465U (en) A kind of high-precision frequency synthesizer
CN104660218A (en) Arbitrary waveform synthesizer
Liu Design of typical waveform generator based on DDS/SOPC
Du et al. DDS phase-locked swept source and study design
CN206149246U (en) Portable two frequency signal beacon system
Tsai et al. FPGA-based reconfigurable measurement instruments with functionality defined by user
CN212301773U (en) ADC performance test circuit, chip and equipment
CN104104363A (en) Function signal generator
Bodong et al. The design and implement of broad band white noise signal generator based on AD9957
CN212569746U (en) M sequence generator based on FPGA
CN103884370A (en) Axial angle conversion testing system based on programmable DRC
Wang et al. Design of the high-precision signal generator based on ARM
Matic et al. The waveform generator based on digital signal processing
CN109218238B (en) Real signal Doppler frequency shift method based on Hilbert transform

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant