CN109273454B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109273454B CN109273454B CN201810971377.XA CN201810971377A CN109273454B CN 109273454 B CN109273454 B CN 109273454B CN 201810971377 A CN201810971377 A CN 201810971377A CN 109273454 B CN109273454 B CN 109273454B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention relates to a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with a stacked structure, and the stacked structure comprises an insulating layer and a sacrificial layer which are stacked with each other along the direction vertical to the surface of the substrate; forming a trench hole through the stacked structure; forming a material layer on the inner wall surface of the channel hole, wherein the thickness of the material layer is gradually increased along the direction from the bottom of the channel hole to the top of the channel hole; forming a hydrophilic film on the surface of the material layer; and carrying out wet etching on the material layer, removing the material layer at the bottom of the channel hole, exposing the substrate surface at the bottom of the channel hole, and reserving the material layer with partial thickness on the surface of the side wall of the channel hole. The semiconductor structure can protect the side wall of the channel hole from being damaged in the subsequent process.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed.
In the process of forming the 3D NAND memory, a stacked structure formed by stacking a sacrificial layer and an insulating layer is required to be formed on the surface of a substrate, then, the stacked structure is etched to form a channel hole, and a channel hole structure is formed in the channel hole to serve as a storage string. In the process of forming the channel hole structure, the substrate at the bottom of the channel hole needs to be subjected to plasma etching to form a recessed opening, and then an epitaxial layer is formed in the opening. In the process of etching the substrate, the side wall of the channel hole is easily damaged, so that the characteristic size of the channel hole is influenced, impurity deposition is easily caused at the bottom of the channel hole, the quality of a subsequently formed epitaxial layer is influenced, and the performance of a formed memory is influenced.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of a memory.
In order to solve the above problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the surface of the substrate is provided with a stacked structure; forming a trench hole through the stacked structure; forming a material layer on the inner wall surface of the channel hole, wherein the thickness of the material layer is gradually increased along the direction from the bottom of the channel hole to the top of the channel hole; forming a hydrophilic film on the surface of the material layer; and carrying out wet etching on the material layer, at least partially removing the material layer at the bottom of the channel hole, exposing the substrate surface at the bottom of the channel hole, and reserving the material layer with partial thickness on the surface of the side wall of the channel hole.
Optionally, the maximum thickness of the material layer is 1.5 to 2 times of the minimum thickness.
Optionally, the material layer is formed by an atomic layer deposition process, and in the process of forming the material layer, the substrate is rotated, and the rotation speed of the substrate is set to 2000 rpm/s to 3500 rpm/s.
Optionally, during the forming of the material layer, a deposition gas is sprayed onto the substrate from above the substrate.
Optionally, the hydrophilic membrane is a water membrane.
Optionally, the method for forming the water film includes: water is sprayed from the substrate to the surface of the wafer while the substrate is rotated.
Optionally, in the wet etching process, an etching solution is sprayed from the substrate to the substrate, and the substrate is rotated at the same time.
Optionally, the wet etching uses a hydrophobic etching solution.
Optionally, in the wet etching process, the rotation speed of the substrate is 500 rpm/s to 1000 rpm/s.
Optionally, in the wet etching process, the ratio of the etching rate of the material layer at the top of the channel hole to the etching rate of the material layer at the bottom of the channel hole is (0.5-2): 1.
optionally, the material of the material layer includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.
Optionally, the method further includes: after the material layer at the bottom of the channel hole is removed, etching the substrate at the bottom of the channel hole; removing the residual material layer on the surface of the side wall of the channel hole; and forming a channel hole structure in the channel hole.
Optionally, the channel hole structure includes: the epitaxial semiconductor layer is positioned on the surface of the substrate at the bottom of the channel hole; the semiconductor epitaxial layer is arranged on the surface of the channel hole, and the channel layer is filled in the channel hole.
To solve the above problems, the present invention provides a memory structure formed by the above method, including: a substrate, the substrate surface having a stacked structure; a trench hole through the stacked structure; and the thickness of the side wall is gradually increased along the upward direction of the bottom of the channel hole.
Optionally, the maximum thickness of the side wall is 1.5-2 times of the minimum thickness.
Optionally, the material of the material layer includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.
According to the forming method of the semiconductor structure, the material layer with the thickness gradually increasing from the bottom to the top of the channel hole is formed on the surface of the side wall of the channel hole, and after the hydrophilic film is formed on the surface of the material layer, the material layer is subjected to wet etching, so that the etching rate of the wet etching on the material layer at the bottom of the channel hole is improved. After the material layer at the bottom of the channel hole is removed, the surface of the side wall of the channel hole is provided with the material layer with partial thickness as the side wall, so that the side wall of the channel hole is protected in the subsequent process, and the characteristic dimension of the channel hole is prevented from being influenced in the subsequent process.
Drawings
Fig. 1 to 6 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention;
FIG. 7 is a schematic view of a method for forming a hydrophilic film on a surface of a material layer according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the semiconductor structure and the method for forming the same according to the present invention will be made with reference to the accompanying drawings.
Fig. 1 to fig. 4 are schematic structural diagrams illustrating a semiconductor structure forming process according to the present invention.
Referring to fig. 1, a substrate 100 is provided, wherein a surface of the substrate 100 has a stacked structure 110; a channel hole 130 is formed through the stacked structure 110.
The substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like; according to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited herein. In this embodiment, the substrate 100 is a single crystal silicon wafer.
The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other in a direction perpendicular to the surface of the substrate 100. In one embodiment, the material of the insulating layer 111 is silicon oxide, and the material of the sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials for the insulating layer 111 and the sacrificial layer 112 may be used. In another embodiment, the stacked structure 110 includes a control gate and an insulating layer stacked on each other.
The stack structure 110 also has a cap layer 120 on top. In this embodiment, the cap layer 120 includes an ONO structure layer composed of a silicon oxide layer 121 and a silicon nitride layer 122. The cap layer 120 is used to protect the stack structure 110, and may also be used as a mask layer for etching the stack structure 110 to form the trench hole 130. In other embodiments, the cap layer 120 may not be formed on top of the stacked structure 110.
The cap layer 120 and the stack structure 110 are etched to the surface of the substrate 100 by a dry etching process to form a channel hole 130. In an actual etching process, since the channel hole top 130 is first contacted with an etching gas, the etching rate is high, and thus the channel hole 130 is formed to have an inclined sidewall. In other embodiments, the trench hole 130 with vertical sidewall may be formed by adjusting the etching process parameters or by using a high aspect ratio etching process.
Due to the over-etching phenomenon, the substrate 100 at the bottom of the channel hole 130 is etched to a partial depth. In other embodiments, the substrate 100 may not be over-etched by controlling etching parameters and the like, and the bottom of the channel hole 130 is located right on the surface of the substrate 100.
Referring to fig. 2, a material layer 200 is formed on the inner wall surface of the trench hole 130, and the thickness of the material layer 200 gradually increases from the bottom of the trench hole 130 to the top of the trench hole 130.
The material of the material layer 200 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride. The material layer 200 may be formed by an atomic layer deposition process, a chemical vapor deposition process, or the like, and during the deposition of the material layer 200, the substrate 100 is rotated so that the concentration of the gas entering the channel hole 130 is gradually increased from the bottom of the channel hole 130 upwards, thereby forming a material layer gradually thickened from the bottom of the channel hole 130. The greater the rotation speed of the substrate 100, the greater the difference between the maximum thickness and the minimum thickness of the material layer 200. In a specific embodiment, the maximum thickness of the material layer 200 is 1.5 to 2 times of the minimum thickness, so that in the subsequent process of etching the material layer 200, after the material layer 200 at the bottom of the channel hole 130 is removed, the sidewall of the channel hole 130 can also retain a part of the thickness of the material layer 200
In this embodiment, the material of the material layer 200 is silicon oxide, and the material layer 200 is formed by an atomic layer deposition process. In the process of forming the material layer, the substrate 100 is placed on the surface of a wafer base station of a deposition chamber, deposition gas is sprayed to the substrate 100 from above the substrate 100, and the substrate 100 is driven by the wafer base station to rotate. The rotation speed of the substrate 100 may be set to 2000 rpm/s to 3500 rpm/s so that the material layer 200 at the top and bottom of the channel hole 130 has a sufficient thickness difference.
In this embodiment, the thickness d1 of the material layer 200 on the side wall of the sacrificial layer 112 at the top of the stacked structure 110 is 1.7 times the thickness dn of the material layer 200 on the side wall of the sacrificial layer 112 at the bottom of the stacked structure 110.
Referring to fig. 3, a hydrophilic film 300 is formed on the surface of the material layer 200.
In this embodiment, the hydrophilic membrane 300 is a water membrane. On one hand, the water film has hydrophilicity, and on the other hand, the subsequent process cannot be polluted. In other embodiments, the hydrophilic membrane 300 can also be other membrane layers, such as ethanol, propanol, etc.
In this embodiment, the method for forming the hydrophilic film 300 includes: water is sprayed from above the substrate 100 toward the surface of the substrate 100 while the substrate 100 is rotated. Referring to fig. 7, the substrate 100 is placed on the surface of the wafer pedestal 701 in the chamber, deionized water is sprayed onto the surface of the substrate 100 through the nozzle 702 above the wafer pedestal 701, and the wafer pedestal 701 drives the substrate 100 to rotate, so that the thickness of the water-based film 300 formed on the material layer 200 is uniform. In fig. 7, the structure shown in fig. 3 is represented by a substrate 100 only. The thickness of the hydrophilic film 300 formed on the surface of the material layer 200 is controlled by controlling the flow rate of the deionized water sprayed from the nozzle 702 and the rotation speed of the wafer stage 701. In this embodiment, the hydrophilic film 300 formed on the surface of the material layer 200 has a thickness of 1 μm to 10 μm.
Referring to fig. 4, the material layer 200 (see fig. 3) is wet etched to remove the material layer at the bottom of the channel hole 130, expose the surface of the substrate 100 at the bottom of the channel hole 130, and leave the material layer with a partial thickness on the sidewall surface of the channel hole 130 as a sidewall 201.
Since the surface of the material layer 200 has the hydrophilic film 300 (refer to fig. 3), the etching solution does not directly contact the surface of the material layer 200 after contacting the hydrophilic film 300, and more easily flows to the bottom of the channel hole 130 along the hydrophilic film 300, so that more etching solution is in the channel hole 130, and the etching rate is increased.
Further, the etching may be performed using a hydrophobic etching solution, such as an HF solution or the like. Since the hydrophilic film 300 has hydrophilicity and the hydrophobic etching solution is less likely to infiltrate into the hydrophilic film 300, the etching solution can flow into the bottom of the channel hole 130 more easily, thereby increasing the etching rate of the material layer 200 at the bottom of the channel hole 130. The hydrophilic film 300 is mixed with the etching solution as the etching process proceeds during the wet etching process without an additional process for removal.
If the hydrophilic film is not formed, the material layer 200 is directly etched using a wet etching process. Since the etching solution first contacts the material layer 2000 at the top of the channel hole 130, the etching rate to the top material layer 200 is greater than the etching rate to the material layer 200 at the bottom of the channel hole 130. In a specific embodiment of the present invention, the hydrophilic film 300 is formed to allow more etching solution to enter the bottom of the channel hole 130, thereby increasing the etching rate of the material layer 200 at the bottom of the channel hole 130. Finally, after the material layer 200 at the bottom of the channel hole 130 is removed to expose the surface of the substrate 100, the sidewall surface of the channel hole 130 further has a material layer with a partial thickness as a sidewall 201, and the stacked structures 110 on both sides are protected in a subsequent process. The sidewall 201 may completely cover the sidewall of the channel 130, or may expose a portion of the sidewall near the bottom surface of the channel hole 130.
In this embodiment, the etching solution used in the wet etching process is an HF solution, and the substrate 100 is sprayed with the etching solution from above the substrate 100 while the substrate 100 rotates. Specifically, the substrate 100 is placed on the surface of a wafer base in the chamber, deionized water is sprayed onto the surface of the substrate through a nozzle above the wafer base, and the wafer base drives the substrate to rotate, so that the etching solution is uniformly distributed. Since the substrate 100 is horizontally disposed, the etching solution is more easily flowed into the bottom of the channel hole 130. Further, the rotation speed of the substrate 100 may be controlled to reduce the rotation speed of the substrate 100, which is more favorable for the etching solution to enter the channel hole 130. In one embodiment, the substrate 100 is rotated at a speed of 500 rpm/sec to 1000 rpm/sec.
The etching rate of the material layer 200 in the wet etching process can be adjusted by controlling parameters such as the concentration of the etching solution, the rotation speed of the substrate 100, the thickness of the hydrophilic film 300, and the like. In one embodiment, the ratio of the etching rate of the material layer 300 at the top of the channel hole 130 to the etching rate of the material layer 300 at the bottom of the channel hole 130 is (0.5-2): 1.
in the method, the hydrophilic film is formed on the surface of the material layer 200, so that the etching rate of the material layer 200 at the bottom of the channel hole 130 is increased, and after the material layer 200 at the bottom of the channel hole 130 is removed, the side wall is reserved on the surface of the side wall of the channel hole 130, so that the side wall of the channel hole 130 can be protected in the subsequent process.
Referring to fig. 5, in this embodiment, the method further includes: after removing the material layer 200 at the bottom of the channel hole 130, the substrate 100 at the bottom of the channel hole 130 is etched to form a recess 500 in the substrate 100.
A plasma etch process may be used to etch the substrate 100 along the channel hole 130. Since the sidewall 201 is disposed on the sidewall surface of the channel hole 130, the sidewall of the channel hole 130 is not damaged and the characteristic dimension of the channel hole 130 is not affected during the etching process of the substrate 100.
Referring to fig. 6, the sidewall 201 (see fig. 5) on the sidewall surface of the trench 130 is removed; a channel hole structure is formed in the channel hole 130 (see fig. 5).
The trench hole structure includes: an epitaxial semiconductor layer 601 on the substrate surface at the bottom of the channel hole 130; the semiconductor device comprises a functional side wall 602 covering the surface of the side wall of the channel hole, a channel layer 603 covering the functional side wall 602 and the semiconductor epitaxial layer 601, and a channel medium layer 604 located on the surface of the channel layer 603 and filled with the channel hole 130. The functional side wall comprises a silicon oxide blocking layer, a silicon nitride charge capturing layer and a silicon oxide tunneling layer.
Referring to fig. 4, an embodiment of the invention further provides a memory structure formed by the above method, including: a substrate 100, wherein the surface of the substrate 100 is provided with a stacked structure 110; a channel hole 130 penetrating the stack structure 110; the side wall 201 is located on the surface of the side wall of the channel hole 130, and the thickness of the side wall 210 is gradually increased along the upward direction of the bottom of the channel hole 130.
The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other in a direction perpendicular to the surface of the substrate 100. The stack structure 110 also has a cap layer 120 on top. In this embodiment, the cap layer 120 includes an ONO structure layer composed of a silicon oxide layer 121 and a silicon nitride layer 122. In other embodiments, the cap layer 120 may be absent from the top of the stacked structure 110.
The sidewall 201 may completely cover the sidewall of the channel 130, or may expose a portion of the sidewall near the bottom surface of the channel hole 130.
The maximum thickness of the side wall 201 is 1.5-2 times of the minimum thickness.
The material of the sidewall 201 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.
The sidewall 201 is used for including the sidewall of the channel hole 130 in the subsequent process of etching the substrate 100, so as to prevent the sidewall of the channel hole 130 from being worn to affect the feature size of the channel hole 130.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the surface of the substrate is provided with a stacked structure;
forming a trench hole through the stacked structure;
forming a material layer on the inner wall surface of the channel hole, wherein the thickness of the material layer is gradually increased along the direction from the bottom of the channel hole to the top of the channel hole;
forming a hydrophilic film on the surface of the material layer, wherein the hydrophilic film is used for not directly contacting the surface of the material layer after an etching solution contacts the hydrophilic film when the material layer is subjected to wet etching in the subsequent process, and the etching solution can more easily flow to the bottom of the channel hole along the hydrophilic film, so that more etching solution is in the channel hole, and the etching rate is improved;
performing wet etching on the material layer, at least partially removing the material layer at the bottom of the channel hole, exposing the substrate surface at the bottom of the channel hole, and reserving the material layer with partial thickness on the surface of the side wall of the channel hole as a side wall;
and after the side wall is formed, etching the substrate at the bottom of the channel hole to form a recess in the substrate, wherein the side wall protects the side wall of the channel hole in the process of etching the substrate at the bottom of the channel hole.
2. The method as claimed in claim 1, wherein the maximum thickness of the material layer is 1.5-2 times the minimum thickness.
3. The method of claim 1, wherein the material layer is formed by an atomic layer deposition process, and the substrate is rotated during the forming of the material layer, and the rotation speed of the substrate is set to 2000 rpm/s to 3500 rpm/s.
4. The method of claim 3, wherein a deposition gas is injected toward the substrate from above the substrate during the forming of the material layer.
5. The method of claim 1, wherein the hydrophilic film is a water film.
6. The method of claim 5, wherein the forming of the water film comprises: water is sprayed from the substrate to the surface of the wafer while the substrate is rotated.
7. The method of claim 1, wherein during the wet etching, the etching solution is sprayed from the substrate to the substrate while the substrate is rotating.
8. The method of claim 1, wherein the wet etching uses a hydrophobic etching solution.
9. The method as claimed in claim 7, wherein the substrate rotates at a speed of 500 rpm/s to 1000 rpm/s during the wet etching.
10. The method for forming the semiconductor structure according to claim 1, wherein in the wet etching process, the ratio of the etching rate of the material layer at the top of the channel hole to the etching rate of the material layer at the bottom of the channel hole is (0.5-2): 1.
11. the method of claim 1, wherein the material of the material layer comprises at least one of silicon oxide, silicon oxynitride, and silicon nitride.
12. The method of forming a semiconductor structure of claim 1, further comprising: after the material layer at the bottom of the channel hole is removed, etching the substrate at the bottom of the channel hole; removing the residual material layer on the surface of the side wall of the channel hole; and forming a channel hole structure in the channel hole.
13. The method of claim 12, wherein the channel hole structure comprises: the epitaxial semiconductor layer is positioned on the surface of the substrate at the bottom of the channel hole; the semiconductor epitaxial layer is arranged on the surface of the channel hole, and the channel layer is filled in the channel hole.
14. A semiconductor structure formed by the formation method of any one of claims 1 to 13, comprising:
a substrate, the substrate surface having a stacked structure;
a trench hole through the stacked structure;
and the thickness of the side wall is gradually increased along the upward direction of the bottom of the channel hole.
15. The semiconductor structure of claim 14, wherein the maximum thickness of the sidewall spacers is 1.5 to 2 times the minimum thickness.
16. The semiconductor structure of claim 14, wherein the material of the material layer comprises at least one of silicon oxide, silicon oxynitride, and silicon nitride.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020168811A1 (en) * | 2001-05-11 | 2002-11-14 | Chien-Wei Chen | Method of fabricating an insulating layer |
| CN102543697A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing tunnel oxide layer window in electrically erasable programmable read only memory (EEPROM) |
| CN107611128A (en) * | 2017-08-31 | 2018-01-19 | 长江存储科技有限责任公司 | A kind of three-dimensional computer flash memory device and preparation method thereof and buffering layer manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020168811A1 (en) * | 2001-05-11 | 2002-11-14 | Chien-Wei Chen | Method of fabricating an insulating layer |
| CN102543697A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing tunnel oxide layer window in electrically erasable programmable read only memory (EEPROM) |
| CN107611128A (en) * | 2017-08-31 | 2018-01-19 | 长江存储科技有限责任公司 | A kind of three-dimensional computer flash memory device and preparation method thereof and buffering layer manufacturing method thereof |
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