CN109273454A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109273454A CN109273454A CN201810971377.XA CN201810971377A CN109273454A CN 109273454 A CN109273454 A CN 109273454A CN 201810971377 A CN201810971377 A CN 201810971377A CN 109273454 A CN109273454 A CN 109273454A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The present invention relates to a kind of semiconductor structures and forming method thereof, the forming method of the semiconductor structure includes: to provide a substrate, the substrate surface has stacked structure, and the stacked structure includes the insulating layer and sacrificial layer being stacked with along vertical substrates surface direction；Form the channel hole for running through the stacked structure；Inner wall surface in the channel hole forms a material layer, and the thickness of the material layer is gradually increased along channel hole bottom to channel hole top-direction；A hydrophilic film is formed in the material surface；Wet etching is carried out to the material layer, the material layer of channel hole bottom is removed, exposes the substrate surface of channel hole bottom, retain the material layer of the channel hole sidewall surface portions thickness.The semiconductor structure can protect channel hole side wall injury-free in the subsequent process.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
During forming 3D nand memory, need to form in substrate surface formation sacrificial layer with stacked dielectric layer
Stacked structure, then etch the stacked structure and form channel hole, form channel pore structure in the channel hole, as depositing
Storage string.During forming channel pore structure, needs to carry out plasma etching to the substrate of channel hole bottom, form recess
Opening, then epitaxial layer is formed in the opening.During performing etching the substrate, it is easy to make the side wall in channel hole
At damage, so that the characteristic size in channel hole is affected, and is easy to cause impurity to deposit in channel hole bottom, influence subsequent
The epitaxial layer quality of formation, to influence the performance of memory to be formed.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of semiconductor structures and forming method thereof, improve memory
Performance.
To solve the above-mentioned problems, the present invention provides a kind of forming methods of semiconductor structure, comprising: provides a lining
Bottom, the substrate surface have stacked structure；Form the channel hole for running through the stacked structure；Inner wall table in the channel hole
Face forms a material layer, and the thickness of the material layer is gradually increased along channel hole bottom to channel hole top-direction；In the material
Bed of material surface forms a hydrophilic film；Wet etching is carried out to the material layer, at least partly removes channel hole bottom
Material layer exposes the substrate surface of channel hole bottom, retains the material layer of the channel hole sidewall surface portions thickness.
Optionally, the maximum gauge of the material layer is 1.5~2 times of minimum thickness.
Optionally, the material layer is formed using atom layer deposition process, and during forming the material layer, served as a contrast
Bottom is rotated, and sets 2000 revolutions per seconds~3500 revolutions per seconds for the revolving speed of substrate.
Optionally, during forming the material layer, deposition gases are sprayed to the substrate from above substrate.
Optionally, the hydrophilic film is moisture film.
Optionally, the forming method of the moisture film includes: the direction crystal column surface water spray from substrate, while substrate is revolved
Turn.
Optionally, during wet etching, from substrate, direction substrate sprays etching solution, while substrate is rotated.
Optionally, the wet etching uses hydrophobicity etching solution.
Optionally, during the wet etching, the revolving speed of the substrate is 500 revolutions per seconds~1000 revolutions per seconds.
Optionally, during the wet etching, the etch rate and channel bottom hole of the material layer at the top of the channel hole
The etch rate ratio of the material layer in portion is (0.5~2): 1.
Optionally, the material of the material layer includes at least one of silica, silicon oxynitride, silicon nitride.
Optionally, further includes: after the material layer for removing channel hole bottom, etch the lining of channel hole bottom
Bottom；Remove the remaining material layer of channel hole sidewall surfaces；Channel pore structure is formed in the channel hole.
Optionally, the channel pore structure includes: the epitaxial semiconductor layer positioned at the substrate surface of channel hole bottom；
Cover the function side wall of channel hole sidewall surfaces, the channel layer of the covering function side wall and semiconductor epitaxial layers, with
And the channel dielectric layer in the full channel hole is filled positioned at the channel layer surface.
To solve the above problems, a specific embodiment of the invention also provided a kind of memory construction, using above-mentioned side
Method is formed, comprising: substrate, the substrate surface have stacked structure；Through the channel hole of the stacked structure；Positioned at described
The thickness of the side wall of channel hole sidewall surfaces, the side wall is gradually increased along channel hole bottom upwardly direction.
Optionally, the maximum gauge of the side wall is 1.5~2 times of minimum thickness.
Optionally, the material of the material layer includes at least one of silica, silicon oxynitride, silicon nitride.
The forming method of semiconductor structure of the invention, channel hole sidewall surfaces formed thickness with from channel hole bottom to
The material layer that top is gradually increased, and after material surface forms a hydrophilic film, wet process is carried out to the material layer
Etching, improves the wet etching to the etch rate of the material layer of channel hole bottom.So that the material layer quilt of channel hole bottom
After removal, channel hole sidewall surfaces also have the material layer of segment thickness as side wall, protect institute in the subsequent process
The side wall for stating channel hole avoids the characteristic size in channel hole from being affected in the subsequent process.
Detailed description of the invention
Fig. 1 to Fig. 6 is the structural schematic diagram of the forming process of the semiconductor structure of the embodiment of the invention；
Fig. 7 is the method schematic diagram in material surface formation hydrophilic film of the embodiment of the invention.
Specific embodiment
The specific embodiment of semiconductor structure provided by the invention and forming method thereof is done in detail with reference to the accompanying drawing
Explanation.
Please refer to figs. 1 to 4, is the structural schematic diagram of the forming process of semiconductor structure of the present invention.
Referring to FIG. 1, providing a substrate 100,100 surface of substrate has stacked structure 110；It is formed and runs through the heap
The channel hole 130 of stack structure 110.
The substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to the reality of device
Demand can choose suitable semiconductor material as the substrate 100, be not limited thereto.In the specific embodiment, institute
Stating substrate 100 is monocrystalline silicon wafer crystal.
The stacked structure 110 includes the insulating layer 111 and sacrificial layer being stacked with along 100 surface direction of vertical substrates
112.In a specific embodiment, the material of the insulating layer 111 is silica, and the material of the sacrificial layer 112 is nitrogen
SiClx；In other specific embodiments, the insulating layer 111 and sacrificial layer 112 can also use other suitable materials.
In another specific embodiment, the stacked structure 110 includes the control grid and insulating layer being stacked with.
110 top of stacked structure also has a cap layer 120.In the specific embodiment, the cap layer 120 is wrapped
Include the ONO structure layer that silicon oxide layer 121 and silicon nitride layer 122 are constituted.The cap layer 120 is for protecting the stacked structure
110, it can also be used as the mask layer that etching stacked structure 110 forms channel hole 130.It is described in other specific embodiments
The cap layer 120 can not also be formed at the top of stacked structure 110.
The cap layer 120 and stacked structure 110 are etched to 100 surface of substrate by dry etch process, form channel
Hole 130.In practical etching technics, due to the channel hole top 130 contact etching gas first, etch rate is higher, because
This described channel hole 130 formed has sloped sidewall.It, can also be by adjusting etching technics in other specific embodiments
Parameter or use high aspect ratio technique etc. form the vertical channel hole 130 of side wall.
Since the substrate 100 with over etching phenomenon, 130 bottom of channel hole is etched partial depth.In other tools
In body embodiment, can by control etching parameters etc., so that the substrate 100 is by over etching, the channel hole 130
Bottom is placed exactly in 100 surface of substrate.
Referring to FIG. 2, the inner wall surface in the channel hole 130 forms a material layer 200, the thickness of the material layer 200
Degree is gradually increased along 130 bottom of channel hole to channel hole, 130 top-direction.
The material of the material layer 200 includes at least one of silica, silicon oxynitride, silicon nitride.It can be using original
Sublayer depositing operation, chemical vapor deposition process etc. form the material layer 200, during depositing material layer 200,
Rotate substrate 100, so that gradually becoming upwards into the gas concentration in the channel hole 130 from 130 bottom of channel hole
Greatly, thus the mutually material layer that gradually thickens is formed from 130 bottom of channel hole.The revolving speed of the substrate 100 is bigger, material layer
The difference of 200 maximum gauge and minimum thickness is bigger.In a specific embodiment, the maximum gauge of the material layer 200
It is 1.5~2 times of minimum thickness, so that during subsequent etching material layer 200,200 quilt of material layer of 130 bottom of channel hole
After removal, 130 side wall of channel hole can also retain the material layer 200 of segment thickness
In the specific embodiment, the material of the material layer 200 is silica, forms institute using atom layer deposition process
State material layer 200.During forming the material layer, substrate 100 is placed in the wafer base station surface of deposition chambers, will deposit
Gas sprays to the substrate 100 from above substrate 100, and the substrate 100 is rotated by the drive of wafer base station.It can will serve as a contrast
The revolving speed at bottom 100 is set as 2000 revolutions per seconds~3500 revolutions per seconds, so that the material layer 200 of 130 top and bottom of channel hole
With enough difference in thickness.
In this specific embodiment, 200 thickness of material layer of 112 side wall of sacrificial layer at 110 top of stacked structure
D1 is 1.7 times of the 200 thickness d n of material layer of 112 side wall of sacrificial layer of 110 bottom of stacked structure.
Referring to FIG. 3, forming hydrophilic film 300 on 200 surface of material layer.
In the specific embodiment, the hydrophilic film 300 is moisture film.On the one hand, moisture film has hydrophily, on the other hand
Subsequent technique will not be polluted.In other specific embodiments, the hydrophilic film 300 can also be other films
Layer, such as ethyl alcohol, propyl alcohol film etc..
In the specific embodiment, the forming method of the hydrophilic film 300 includes: from direction substrate 100 on substrate 100
Surface water spray, while substrate 100 is rotated.Referring to FIG. 7, substrate 100 is placed in indoor 701 surface of wafer base station of chamber,
By the nozzle 702 of 701 top of wafer base station, deionized water is sprayed to 100 surface of substrate, while wafer base station 701 drives institute
It states substrate 100 to be rotated, so that 300 thickness of aqueous film formed in material layer 200 is uniform.In Fig. 7, only with 100 generation of substrate
Structure shown in table Fig. 3.By the revolving speed of de-ionized water flow rate and wafer base station 701 that control nozzle 702 sprays, to material
The thickness for the hydrophilic film 300 that 200 surface of the bed of material is formed is controlled.In the specific embodiment, in 200 table of material layer
Face formed hydrophilic film 300 with a thickness of 1 μm~10 μm.
Referring to FIG. 4, carrying out wet etching to the material layer 200 (please referring to Fig. 3), 130 bottom of channel hole is removed
The material layer in portion exposes 100 surface of substrate of 130 bottom of channel hole, retains the 130 sidewall surface portions thickness of channel hole
Material layer, as side wall 201.
Since 200 surface of material layer has hydrophilic film 300 (please referring to Fig. 3), etching solution touches the parent
After aqueous film 300, will not directly it be contacted with 200 surface of material layer, it is easier to flow to institute along the hydrophilic film 300
The bottom in channel hole 130 is stated, so that the etching solution in the channel hole 130 is more, etch rate is improved.
Further, it can be performed etching using hydrophobic etching solution, such as HF solution etc..Due to the hydrophily
Film 300 has hydrophily, and hydrophobic etching solution is less susceptible to infiltrate with the hydrophilic film 300, therefore, is more advantageous to etching
Solution flows into the bottom in channel hole 130, to improve the etch rate to the material layer 200 of 130 bottom of channel hole.It is described hydrophilic
Property film 300 with the progress of etching process, mixes, without additional technique during wet etching with the etching solution
Removal.
If not formed hydrophilic film, and directlys adopt wet-etching technology and material layer 200 is performed etching.Due to etching
Solution contacts the material layer 2000 at 130 top of channel hole first, so that the etch rate to top layer of material 200 is greater than to channel
The etch rate of the material layer 200 of 130 bottom of hole.And in specifically mode of the invention, pass through and forms the hydrophilic film
300, so that more etching solutions enter 130 bottom of channel hole, so as to improve the material layer 200 of 130 bottom of channel hole
Etch rate.Finally, after the removal of the material layer 200 of 130 bottom of channel hole is exposed 100 surface of substrate, the ditch
The sidewall surfaces in road hole 130 also have the material layer of segment thickness as side wall 201, protect the stacking of two sides in the subsequent process
Structure 110.The side wall 201 can completely cover the side wall of the channel 130, can also expose close to 130 bottom of channel hole
The partial sidewall in face.
In the specific embodiment, the etching solution that the wet-etching technology uses is HF solution, from above substrate 100
Etching solution is sprayed to substrate 100, while substrate 100 is rotated.Specifically, substrate 100 is placed in the indoor wafer base of chamber
Platform surface deionized water is sprayed to substrate surface, while wafer base station drives the substrate by the nozzle above wafer base station
It is rotated, so that etching solution is evenly distributed.Since the substrate 100 is horizontal positioned, so that etching solution is easier to flow into ditch
The bottom in road hole 130.Further, the revolving speed of the substrate 100 is reduced, is more had by the revolving speed that can control the substrate 100
Enter in channel hole 130 conducive to etching solution.In a specific embodiment, the revolving speed of the substrate 100 is 500 revolutions per seconds
~1000 revolutions per seconds.
It is adjustable by the control concentration of etching solution, the parameters such as thickness of the revolving speed of substrate 100, hydrophilic film 300
To the etch rate of material layer 200 during the wet etching.In a specific embodiment, the channel hole 130 is pushed up
The etch rate ratio of the material layer 300 of the etch rate and 130 bottom of channel hole of the material layer 300 in portion is (0.5~2): 1.
The above method improves the material to 130 bottom of channel hole by forming a hydrophilic film on 200 surface of material layer
The etch rate of layer 200, so that after the material layer 200 for removing 130 bottom of channel hole, in 130 side of channel hole
Wall surface retains side wall, can play in the subsequent process to the 130 side wall protective effect of channel hole.
Referring to FIG. 5, in the specific embodiment, further includes: in the material layer 200 for removing 130 bottom of channel hole
Later, the substrate 100 of 130 bottom of channel hole is etched, the recess 500 being located in substrate 100 is formed.
Substrate 100 can be performed etching to along the channel hole 130 with using plasma etching technics.Due to the ditch
There is 130 sidewall surfaces of road hole side wall 201 therefore during etched substrate 100, will not make to the side wall in channel hole 130
At damage, the characteristic size in channel hole 130 will not be impacted.
Referring to FIG. 6, removing the side wall 201 (please referring to Fig. 5) of 130 sidewall surfaces of channel；In the channel hole 130
Channel pore structure is formed in (please referring to Fig. 5).
The channel pore structure includes: the epitaxial semiconductor layer 601 positioned at the substrate surface of 130 bottom of channel hole；
Cover the function side walls 602 of channel hole sidewall surfaces, the covering function side wall 602 and semiconductor epitaxial layers 601
Channel layer 603 and the channel dielectric layer 604 that the full channel hole 130 is filled positioned at 603 surface of channel layer.The function
Energy side wall includes silica barrier layer, silicon nitride charge trapping layer and silica tunnel layer.
Referring to FIG. 4, a specific embodiment of the invention also provides a kind of memory construction formed using the above method,
It include: substrate 100,100 surface of substrate has stacked structure 110；Through the channel hole 130 of the stacked structure 110；Position
In the side wall 201 of 130 sidewall surfaces of channel hole, the thickness of the side wall 210 along 130 bottom upwardly direction of channel hole by
It is cumulative big.
The stacked structure 110 includes the insulating layer 111 and sacrificial layer being stacked with along 100 surface direction of vertical substrates
112.110 top of stacked structure also has a cap layer 120.In the specific embodiment, the cap layer 120 includes oxygen
The ONO structure layer that SiClx layer 121 and silicon nitride layer 122 are constituted.In other specific embodiments, the stacked structure 110 is pushed up
It portion can also be without the cap layer 120.
The side wall 201 can completely cover the side wall of the channel 130, can also expose close to 130 bottom of channel hole
The partial sidewall in face.
The maximum gauge of the side wall 201 is 1.5~2 times of minimum thickness.
The material of the side wall 201 includes at least one of silica, silicon oxynitride, silicon nitride.
The side wall 201 in the technique of subsequent etching substrate 100 for, including the side wall in the channel hole 130, avoiding
The side wall in the channel hole 130 is depleted and influences the characteristic size in channel hole 130.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (16)
1. a kind of forming method of semiconductor structure characterized by comprising
A substrate is provided, the substrate surface has stacked structure；
Form the channel hole for running through the stacked structure；
Inner wall surface in the channel hole forms a material layer, and the thickness of the material layer is pushed up along channel hole bottom to channel hole
Portion direction is gradually increased；
A hydrophilic film is formed in the material surface；
Wet etching is carried out to the material layer, the material layer of channel hole bottom is at least partly removed, exposes channel hole
The substrate surface of bottom retains the material layer of the channel hole sidewall surface portions thickness.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that the maximum gauge of the material layer
It is 1.5~2 times of minimum thickness.
3. the forming method of semiconductor structure according to claim 1, which is characterized in that use atom layer deposition process shape
At the material layer, and during forming the material layer, substrate is rotated, and sets 2000 for the revolving speed of substrate
Revolutions per second~3500 revolutions per seconds.
4. the forming method of semiconductor structure according to claim 3, which is characterized in that in the mistake for forming the material layer
Deposition gases are sprayed to the substrate by Cheng Zhong from above substrate.
5. the forming method of semiconductor structure according to claim 1, which is characterized in that the hydrophilic film is moisture film.
6. the forming method of semiconductor structure according to claim 5, which is characterized in that the forming method packet of the moisture film
Include: from substrate, direction crystal column surface is sprayed water, while substrate is rotated.
7. the forming method of semiconductor structure according to claim 1, which is characterized in that during wet etching, from lining
Direction substrate sprays etching solution on bottom, while substrate is rotated.
8. the forming method of semiconductor structure according to claim 1, which is characterized in that the wet etching is using hydrophobic
Property etching solution.
9. the forming method of semiconductor structure according to claim 7, which is characterized in that during the wet etching,
The revolving speed of the substrate is 500 revolutions per seconds~1000 revolutions per seconds.
10. the forming method of semiconductor structure according to claim 1, which is characterized in that during the wet etching,
The etch rate ratio of the material layer of the etch rate and channel hole bottom of material layer at the top of the channel hole is (0.5~2): 1.
11. the forming method of semiconductor structure according to claim 1, which is characterized in that the material packet of the material layer
Include at least one of silica, silicon oxynitride, silicon nitride.
12. the forming method of semiconductor structure according to claim 1, which is characterized in that further include: remove the channel
After the material layer of hole bottom, the substrate of channel hole bottom is etched；Remove the remaining material of channel hole sidewall surfaces
Layer；Channel pore structure is formed in the channel hole.
13. the forming method of semiconductor structure according to claim 12, which is characterized in that the channel pore structure packet
It includes: positioned at the epitaxial semiconductor layer of the substrate surface of channel hole bottom；Cover the functioning side of channel hole sidewall surfaces
Wall, the covering function side wall and semiconductor epitaxial layers channel layer and to be located at channel layer surface filling full described
The channel dielectric layer in channel hole.
14. a kind of semiconductor structure, which is characterized in that formed, wrapped using any one of claims 1 to 13 forming method
It includes:
Substrate, the substrate surface have stacked structure；
Through the channel hole of the stacked structure；
Positioned at the side wall of channel hole sidewall surfaces, the thickness of the side wall gradually increases along channel hole bottom upwardly direction
Greatly.
15. semiconductor structure according to claim 14, which is characterized in that the maximum gauge of the side wall is minimum thickness
1.5~2 times.
16. semiconductor structure according to claim 14, which is characterized in that the material of the material layer include silica,
At least one of silicon oxynitride, silicon nitride.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110544244A (en) * | 2019-08-29 | 2019-12-06 | 长江存储科技有限责任公司 | method and device for obtaining channel through hole characteristic parameters |
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| US20020168811A1 (en) * | 2001-05-11 | 2002-11-14 | Chien-Wei Chen | Method of fabricating an insulating layer |
| CN102543697A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing tunnel oxide layer window in electrically erasable programmable read only memory (EEPROM) |
| CN107611128A (en) * | 2017-08-31 | 2018-01-19 | 长江存储科技有限责任公司 | A kind of three-dimensional computer flash memory device and preparation method thereof and buffering layer manufacturing method thereof |
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| US20020168811A1 (en) * | 2001-05-11 | 2002-11-14 | Chien-Wei Chen | Method of fabricating an insulating layer |
| CN102543697A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing tunnel oxide layer window in electrically erasable programmable read only memory (EEPROM) |
| CN107611128A (en) * | 2017-08-31 | 2018-01-19 | 长江存储科技有限责任公司 | A kind of three-dimensional computer flash memory device and preparation method thereof and buffering layer manufacturing method thereof |
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| CN110544244A (en) * | 2019-08-29 | 2019-12-06 | 长江存储科技有限责任公司 | method and device for obtaining channel through hole characteristic parameters |
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