CN109273443B - Manufacturing method of SONOS device - Google Patents

Manufacturing method of SONOS device Download PDF

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CN109273443B
CN109273443B CN201811396604.7A CN201811396604A CN109273443B CN 109273443 B CN109273443 B CN 109273443B CN 201811396604 A CN201811396604 A CN 201811396604A CN 109273443 B CN109273443 B CN 109273443B
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silicon oxide
sonos device
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oxide layer
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CN109273443A (en
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朱华宁
章晶
黄冠群
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Shanghai Huali Microelectronics Corp
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

The invention discloses a manufacturing method of an SONOS device, which comprises the following steps: forming a first liner silicon oxide layer and a second silicon nitride layer to form shallow trench field oxide; the thicknesses of the first pad silicon oxide layer and the second silicon nitride layer define the step height of the shallow trench field oxide. And removing the second silicon nitride layer. A third protective layer is formed to protect the formation region of the ONO layer. And wet-removing a portion of the thickness of the first liner silicon oxide layer outside the formation region of the ONO layer. Removing the third protective layer; and performing wet etching to completely remove the first liner silicon oxide layer outside the forming area of the ONO layer and reserve part of the thickness in the forming area of the ONO layer. Before the tunneling silicon oxide layer forming process of the ONO layer is carried out, a wet soaking process is further included, and the step height of the shallow trench field oxide before and after the wet soaking process is kept by the reserved first liner silicon oxide layer. The invention can avoid the influence of the wet etching process on the step height of the field oxygen and can improve the process window.

Description

Manufacturing method of SONOS device
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a SONOS device.
Background
In the High Voltage (HV) product process of 55nm low-leakage Embedded flash (E-flash) SONOS, a process of G1-before is adopted, wherein G1-before means that a Gate Oxide (Gate Oxide) of a Gate of a logic device such as a CMOS device integrated with the SONOS device grows in two parts, and the Gate Oxide of the first part, namely G1, is formed before an ONO layer of the SONOS device, namely G1-before; the gate oxide layer of the second portion is formed after the ONO layer is formed.
Before the gate oxide layer grows, the pad silicon oxide layer is removed by wet etching of etching liquid containing hydrofluoric acid, and because the material of field oxygen such as shallow trench field oxygen (STI) is also silicon oxide, the silicon oxide on the surface of the STI is also partially removed when the pad silicon oxide layer is removed; thus, when a tunnel Oxide (Tunneling Oxide) layer, which is the bottom Oxide layer of the ONO layer in the SONOS device region, is formed subsequently, a wet dip (wet dip) process is required before oxidation, and the wet dip process also continues to etch silicon Oxide, which further consumes silicon Oxide on the top surface of field Oxide in the SONOS device formation region and further reduces the top surface of the field Oxide, so that the step height (step height) of field Oxide in the SONOS device formation region is reduced, and defects such as active area damage (AAdamage), void (void) of field Oxide, and ONO layer residue (residual) are caused by too low step height of field Oxide.
As shown in fig. 1A to fig. 1C, the method is a schematic diagram of a device structure in each step of a manufacturing method of a conventional SONOS device, in which the SONOS device and a logic device are integrated together to form the SONOS device, and the method includes the following steps:
step one, as shown in fig. 1A, providing a semiconductor substrate 101, forming a first pad silicon oxide layer 104 and a second silicon nitride layer 105 on a surface of the semiconductor substrate 101, defining a formation region of a shallow trench and forming a shallow trench, and filling the shallow trench with the silicon oxide layer to form a shallow trench field oxide 106; the thicknesses of the first pad silicon oxide layer 104 and the second silicon nitride layer 105 define a step height of the shallow trench field oxide 106, and the step height is a height difference between the top surface of the shallow trench field oxide 106 and the surface of the semiconductor substrate 101.
The semiconductor substrate 101 is a silicon substrate.
In fig. 1A, the formation area of the ONO layer and the formation area of the ONO layer are separated by an AA line, wherein the right side of the AA line is the formation area of the ONO layer, the left side of the AA line is the formation area of the ONO layer, and the left side of the AA line is generally used for forming a logic device such as a PMOS transistor or an NMOS transistor in a CMOS device.
Before forming the shallow trench field oxide 106, a step of forming a well region in a selected region of the semiconductor substrate 101 is further included. In fig. 1A, reference numeral 102 denotes a well region corresponding to the logic device, and an area denoted by reference numeral 103 denotes a well region corresponding to the SONOS device.
Step two, as shown in fig. 1B, the second silicon nitride layer 105 is removed.
And thirdly, as shown in fig. 1C, removing the first pad silicon oxide layer 104 by using a wet etching process.
In the subsequent process, before the tunneling silicon oxide layer forming process of the ONO layer, a wet soaking process is further included, which may consume a certain amount of silicon oxide of the shallow trench field oxide 106 and thus lower the step height of the shallow trench field oxide 106.
The step height of the shallow trench field oxide 106 becomes lower as follows:
before the wet soaking process, the BB lines correspond to the surface of the shallow trench field oxide 106;
after the wet dip process, the surface of the shallow trench field oxide 106 is lowered to the location of the CC line.
The DD line corresponds to a surface location of the semiconductor substrate 101. It can be seen that the height difference between the BB line and the DD line is d 101; the height difference between the CC line and the DD line is d 102; d102 is smaller than d101, wherein d101 corresponds to the step height of the shallow trench field oxide 106 before the wet soaking process, and d102 corresponds to the step height of the shallow trench field oxide 106 after the wet soaking process, so that the wet soaking process can lower the step height of the shallow trench field oxide 106, which finally affects the process window, and makes the control of various processes more difficult.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of an SONOS device, which can avoid the influence of a wet etching process on the step height of field oxide and can improve a process window.
In order to solve the above technical problem, the method for manufacturing a SONOS device according to the present invention, in which the SONOS device and a logic device are integrated together, includes the following steps:
providing a semiconductor substrate, forming a first liner silicon oxide layer and a second silicon nitride layer on the surface of the semiconductor substrate, defining a forming area of a shallow groove, forming a shallow groove, and filling the shallow groove with silicon oxide to form shallow groove field oxygen; the step height of the shallow trench field oxide is defined by the thickness of the first pad silicon oxide layer and the second silicon nitride layer, and the step height is the height difference between the top surface of the shallow trench field oxide and the surface of the semiconductor substrate.
And step two, removing the second silicon nitride layer.
Step three, forming a third protective layer, and defining by using a mask plate of an ONO layer of the SONOS device to remove the third protective layer outside the forming area of the ONO layer and reserve the third protective layer in the forming area of the ONO layer; the ONO layer is formed by superposing a tunneling silicon oxide layer, a storage silicon nitride layer and a control silicon oxide layer.
And fourthly, removing the partial thickness of the first liner silicon oxide layer outside the forming area of the ONO layer by adopting a first wet etching process under the protection of the third protective layer.
And fifthly, removing the third protective layer, and performing a second wet etching process to completely remove the first liner silicon oxide layer outside the forming area of the ONO layer and simultaneously reserve a part of thickness of the first liner silicon oxide layer in the forming area of the ONO layer.
And step six, before the tunneling silicon oxide layer forming process of the ONO layer is carried out, a wet soaking process is further included, the first liner silicon oxide layer reserved in the forming area of the ONO layer is completely removed by the wet soaking process, the shallow trench field oxygen is simultaneously subjected to loss with the same thickness by the wet soaking process, and the step height of the shallow trench field oxygen before and after the wet soaking process is kept by the first liner silicon oxide layer.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, before forming the shallow trench field oxide in the first step, a step of forming a well region in a selected region of the semiconductor substrate is further included.
The further improvement is that the gate oxide layer of the logic device is formed by adopting a two-time gate oxide growth process, and the first gate oxide growth is carried out after the first liner oxide layer outside the forming area of the ONO layer is removed in the step five and the first partial thickness of the gate oxide layer is formed.
A second gate oxide growth is placed after the ONO layer is formed.
In a further improvement, the material of the third protective layer in step three is an anti-reflective coating or photoresist.
In a further improvement, the third protective layer is formed by superposing an anti-reflection coating and photoresist.
In a further improvement, the antireflective coating is a bottom antireflective coating.
The further improvement is that the first wet etching process adopts etching liquid for etching silicon oxide; and the second wet etching process adopts etching liquid for etching silicon oxide.
The further improvement is that the etching rate of the etching liquid of the first wet etching process to the silicon oxide is greater than the etching rate to the silicon nitride; the etching liquid of the second wet etching process has a higher etching rate to silicon oxide than to silicon nitride.
The further improvement is that the etching liquid of the first wet etching process comprises HF, and the etching liquid of the second wet etching process comprises HF.
The further improvement is that the etching liquid of the first wet etching process adopts a buffer oxide etching liquid; and the etching liquid of the second wet etching process adopts buffer oxide etching liquid.
The further improvement is that under the condition of ensuring that the first liner silicon oxide layer outside the ONO layer forming area is completely removed, the proportion matching of the solubility of HF in the etching solution of the first wet etching process and the solubility of HF in the second wet etching process can be adjusted.
In a further improvement, the total thickness of the silicon oxide removed by the first wet etching process and the second wet etching process is
Figure BDA0001875339630000041
In a further improvement, the first liner silicon oxide layer has a thickness of less than or equal to
Figure BDA0001875339630000042
In a further improvement, the SONOS device adopts a 55nm technology.
The invention makes special design for the wet removing process of the first liner silicon oxide layer in the manufacturing method of the SONOS device, after the shallow trench field oxygen is formed and the second silicon nitride layer in the superposed layer of the first liner silicon oxide layer and the second silicon nitride layer which define the step height of the shallow trench field oxygen is removed, a step of forming a third protective layer in the forming area of the ONO layer of the SONOS device is added, then, part of the thickness of the first liner silicon oxide layer outside the forming area of the ONO layer is removed, then, the third protective layer is removed, then, the remaining first liner silicon oxide layer outside the forming area is removed by wet etching, meanwhile, the first liner silicon oxide layer with part of the thickness is remained in the forming area of the ONO layer, because the first liner silicon oxide layer after the remained part of the ONO layer in the forming area of the ONO layer, when the wet soaking process is carried out before the formation of the bottommost oxide layer of the subsequent oxide layer, namely the tunneling oxide layer, the height of the shallow trench field oxide protruding out of the surface of the semiconductor substrate can be maintained under the condition that the first liner silicon oxide layer with the residual thickness is completely removed, namely the step height of the field oxide is maintained; the step height of the field oxide is kept, the control difficulty of various processes in the manufacturing method of the SONOS device can be reduced, and the process window can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1C are schematic diagrams of device structures in various steps of a conventional SONOS device manufacturing method;
FIG. 2 is a flow chart of a method of fabricating a SONOS device according to an embodiment of the present invention;
fig. 3A-3C are schematic device structures at various steps of a method for fabricating a SONOS device according to an embodiment of the present invention.
Detailed Description
Fig. 2 is a flow chart of a method for manufacturing a SONOS device according to an embodiment of the present invention; as shown in fig. 3A to fig. 3C, which are schematic diagrams of device structures in steps of a manufacturing method of a SONOS device according to an embodiment of the present invention, the manufacturing method of a SONOS device according to an embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, providing a semiconductor substrate 1, forming a first pad silicon oxide layer 4 and a second silicon nitride layer 5 on the surface of the semiconductor substrate 1, defining a formation region of a shallow trench and forming a shallow trench, and filling the shallow trench with the silicon oxide layer to form a shallow trench field oxide 6; the thicknesses of the first pad silicon oxide layer 4 and the second silicon nitride layer 5 define the step height of the shallow trench field oxide 6, and the step height is the height difference between the top surface of the shallow trench field oxide 6 and the surface of the semiconductor substrate 1.
The semiconductor substrate 1 is a silicon substrate.
In fig. 3A, the formation area of the ONO layer and the formation area of the ONO layer are separated by an EE line, wherein the right side of the EE line is the formation area of the ONO layer, the left side of the EE line is the formation area of the ONO layer, and the left side of the EE line is commonly used for forming logic devices such as PMOS transistors or NMOS transistors in CMOS devices.
Before the shallow trench field oxide 6 is formed, a step of forming a well region in a selected region of the semiconductor substrate 1 is further included. In fig. 3A, reference numeral 2 denotes a well region corresponding to the logic device, and an area denoted by reference numeral 3 denotes a well region corresponding to the SONOS device.
Step two, as shown in fig. 3B, the second silicon nitride layer 5 is removed.
Step three, as shown in fig. 3B, forming a third protection layer, and defining by using a mask plate of an ONO layer of the SONOS device to remove the third protection layer outside the formation region of the ONO layer and to reserve the third protection layer inside the formation region of the ONO layer; the ONO layer is formed by superposing a tunneling silicon oxide layer, a storage silicon nitride layer and a control silicon oxide layer.
The material of the third protective layer is an anti-reflection coating 7 or photoresist 8. More preferably, the third protective layer is formed by overlapping an anti-reflection coating 7 and a photoresist 8. The anti-reflective coating 7 is a bottom anti-reflective coating 7.
And step four, as shown in fig. 3B, removing a part of the thickness of the first liner silicon oxide layer 4 outside the formation region of the ONO layer by using a first wet etching process under the protection of the third protective layer.
And fifthly, as shown in fig. 3C, removing the third protective layer, and performing a second wet etching process to completely remove the first liner silicon oxide layer 4 outside the formation region of the ONO layer while leaving a part of the thickness of the first liner silicon oxide layer 4 in the formation region of the ONO layer.
Step six, as shown in fig. 3C, before the tunneling silicon oxide layer forming process of the ONO layer is performed, a wet soaking process is further included, the wet soaking process completely removes the first pad silicon oxide layer 4 remaining in the forming region of the ONO layer, the wet soaking process simultaneously performs loss of the same thickness on the shallow trench field oxide 6, and the first pad silicon oxide layer 4 maintains the step height of the shallow trench field oxide 6 before and after the wet soaking process.
The step height of the shallow trench field oxide 6 is maintained as follows:
before the wet soaking process in the sixth step, the FF line corresponds to the surface of the shallow trench field oxide 6, and the height difference between the GG line and the FF line corresponding to the surface of the remaining first liner silicon oxide layer 4 is d1, where d1 is the height of the shallow trench field oxide 6 protruding, i.e. the step height;
after the wet soaking process in the sixth step, the surface of the shallow trench field oxide 6 is lowered to the HH line, the first pad silicon oxide layer 4 is completely removed to expose the surface of the semiconductor substrate 1 corresponding to the line II, and the height difference between the HH line and the line II is d2, which is the protruding height of the shallow trench field oxide 6, i.e. the step height, of the d 2; it can be seen that the values of d2 and d1 can be approximately equal, so that the method of the embodiment of the present invention can well control the step height of the shallow trench field oxide 6, and can prevent the step height of the shallow trench field oxide 6 from decreasing too low.
And the gate oxide layer of the logic device is formed by adopting a two-time gate oxide growth process, and the first gate oxide growth is carried out after the first liner oxide layer 4 outside the forming area of the ONO layer is removed in the step five and the first partial thickness of the gate oxide layer is formed.
A second gate oxide growth is placed after the ONO layer is formed.
In the method of the embodiment of the invention, the first wet etching process selects etching liquid for etching silicon oxide; and the second wet etching process adopts etching liquid for etching silicon oxide. The etching rate of the etching liquid of the first wet etching process to the silicon oxide is greater than that to the silicon nitride; the etching liquid of the second wet etching process has a higher etching rate to silicon oxide than to silicon nitride.
The etching liquid of the first wet etching process comprises HF, and the etching liquid of the second wet etching process comprises HF. Preferably, the etching solution of the first wet etching process is a buffered oxide etching solution; and the etching liquid of the second wet etching process adopts buffer oxide etching liquid.
Under the condition of ensuring that the first liner silicon oxide layer 4 outside the ONO layer forming area is completely removed, the proportion of the solubility of HF in the etching solution of the first wet etching process and the solubility of HF in the second wet etching process can be adjusted.
The total thickness of the silicon oxide removed by the first wet etching process and the second wet etching process is
Figure BDA0001875339630000071
The thickness of the first liner silicon oxide layer 4 is less than or equal to
Figure BDA0001875339630000072
The SONOS device adopts a 55nm technology, and the finally formed product is a 55nm E-flash SONOS HV product.
The embodiment of the invention makes a special design for a wet removing process of a first liner silicon oxide layer 4 in a manufacturing method of a SONOS device, adds a step of forming a third protective layer in a forming area of an ONO layer of the SONOS device after a shallow trench field oxide 6 is formed and a second silicon nitride layer 5 in a first liner silicon oxide layer 4 and a second silicon nitride layer 5 which define the step height of the shallow trench field oxide 6 is removed, then removes a part of the thickness of the first liner silicon oxide layer 4 outside the forming area of the ONO layer, removes the third protective layer, then removes the remaining first liner silicon oxide layer 4 outside the forming area of the ONO layer by wet etching, and simultaneously retains the first liner silicon oxide layer 4 with the part of the thickness in the forming area of the ONO layer, and because the first liner silicon oxide layer 4 behind the part retained in the forming area of the ONO layer is subjected to a wet soaking process before the formation of the bottommost oxide layer of the subsequent layers, namely tunnel oxide layer of the subsequent layers The height of the shallow trench field oxide 6 protruding from the surface of the semiconductor substrate 1 can be maintained under the condition that the first pad silicon oxide layer 4 with the residual thickness is completely removed, namely the step height of the field oxide is maintained; the step height of the field oxide is maintained, the control difficulty of various processes in the manufacturing method of the SONOS device can be reduced, and the process window can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A method of fabricating a SONOS device, wherein the SONOS device and a logic device are integrated together, comprising the steps of:
providing a semiconductor substrate, forming a first liner silicon oxide layer and a second silicon nitride layer on the surface of the semiconductor substrate, defining a forming area of a shallow groove, forming a shallow groove, and filling the shallow groove with silicon oxide to form shallow groove field oxygen; the step height of the shallow trench field oxide is defined by the thickness of the first pad silicon oxide layer and the second silicon nitride layer, and the step height is the height difference between the top surface of the shallow trench field oxide and the surface of the semiconductor substrate;
step two, removing the second silicon nitride layer;
step three, forming a third protective layer, and defining by using a mask plate of an ONO layer of the SONOS device to remove the third protective layer outside the forming area of the ONO layer and reserve the third protective layer in the forming area of the ONO layer; the ONO layer is formed by superposing a tunneling silicon oxide layer, a storage silicon nitride layer and a control silicon oxide layer;
fourthly, removing the partial thickness of the first liner silicon oxide layer outside the forming area of the ONO layer by adopting a first wet etching process under the protection of the third protective layer;
fifthly, removing the third protective layer, and carrying out a second wet etching process to completely remove the first liner silicon oxide layer outside the forming area of the ONO layer and simultaneously reserve the first liner silicon oxide layer with partial thickness in the forming area of the ONO layer;
and step six, before the tunneling silicon oxide layer forming process of the ONO layer is carried out, a wet soaking process is further included, the first liner silicon oxide layer reserved in the forming area of the ONO layer is completely removed by the wet soaking process, the shallow trench field oxygen is simultaneously subjected to loss with the same thickness by the wet soaking process, and the step height of the shallow trench field oxygen before and after the wet soaking process is kept by the first liner silicon oxide layer.
2. The method of fabricating the SONOS device of claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The method of fabricating the SONOS device of claim 1, wherein: before the shallow trench field oxide is formed in the first step, a well region is formed in a selected region of the semiconductor substrate.
4. The method of fabricating the SONOS device of claim 1, wherein: a gate oxide layer of the logic device is formed by adopting a two-time gate oxide growth process, and the first gate oxide growth is carried out after the first liner oxide layer outside the forming area of the ONO layer is removed in the step five and forms the first part of thickness of the gate oxide layer;
a second gate oxide growth is placed after the ONO layer is formed.
5. The method of fabricating the SONOS device of claim 1, wherein: and in the third step, the third protective layer is made of an anti-reflection coating or photoresist.
6. The method of fabricating the SONOS device of claim 5, wherein: the third protective layer is formed by superposing an anti-reflection coating and photoresist.
7. The method of fabricating the SONOS device of claim 6, wherein: the anti-reflective coating is a bottom anti-reflective coating.
8. The method of fabricating the SONOS device of claim 1, wherein: the first wet etching process adopts etching liquid for etching silicon oxide; and the second wet etching process adopts etching liquid for etching silicon oxide.
9. The method of fabricating the SONOS device of claim 8, wherein: the etching rate of the etching liquid of the first wet etching process to the silicon oxide is greater than that to the silicon nitride; the etching liquid of the second wet etching process has a higher etching rate to silicon oxide than to silicon nitride.
10. The method of fabricating the SONOS device of claim 8, wherein: the etching liquid of the first wet etching process comprises HF, and the etching liquid of the second wet etching process comprises HF.
11. The method of fabricating the SONOS device of claim 10, wherein: the etching liquid of the first wet etching process adopts buffer oxide etching liquid; and the etching liquid of the second wet etching process adopts buffer oxide etching liquid.
12. The method of fabricating the SONOS device of claim 11, wherein: under the condition of ensuring that the first liner silicon oxide layer outside the forming area of the ONO layer is completely removed, the proportion matching of the solubility of HF in the etching liquid of the first wet etching process and the solubility of HF in the second wet etching process can be adjusted.
13. The method of fabricating the SONOS device of claim 11, wherein: the total thickness of the silicon oxide removed by the first wet etching process and the second wet etching process is
Figure FDA0002528671930000021
14. The method of fabricating the SONOS device of claim 13, wherein: the thickness of the first liner silicon oxide layer is less than or equal to
Figure FDA0002528671930000022
15. The method of fabricating the SONOS device of claim 13, wherein: the SONOS device adopts a 55nm technology.
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CN103531520A (en) * 2012-07-02 2014-01-22 中芯国际集成电路制造(上海)有限公司 Forming method of shallow trench isolation and semiconductor structure
CN103227144A (en) * 2013-05-07 2013-07-31 上海华力微电子有限公司 Method of improving shallow trench isolating performance of high-voltage device

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