CN103227144A - Method of improving shallow trench isolating performance of high-voltage device - Google Patents
Method of improving shallow trench isolating performance of high-voltage device Download PDFInfo
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Abstract
The invention relates to a manufacturing technology of a semiconductor integrated circuit, in particular to method of improving the shallow trench isolating performance of a high-voltage device. According to the method, two shallow trench isolating regions in different depths are formed in a high-voltage device region and a low-voltage logic region of a semiconductor device respectively by utilizing a photoetching technology and an etching technology for twice, the depth of the shallow trench isolating region in the high-voltage device region is greater than that of the shallow trench isolating region in the low-voltage logic region, so that the problem of high electric leakage of the high-voltage device region is solved, the voltage endurance capability of the high-voltage device and the shallow trench isolating performance of the HV (high-voltage) device are improved, and the overall performances of a product are improved.
Description
Technical field
The present invention relates generally to the semiconductor integrated circuit manufacturing process, more precisely, relate to a kind of method that improves high tension apparatus shallow trench isolation performance.
Background technology
In recent years, the LCD of portable electronic product such as mobile phone, digital camera is used in a large number.The more and more light-emitting diodes that adopt of large-sized monitor and large-screen receiver, can aspect brightness, contrast and power consumption, obtain than traditional CRT(Cathode Ray Tube, cathode ray tube) display and the more outstanding performance performance of LCD.Progress and development along with CMOS technology, HV CMOS (High Voltage Complementary Metal Oxide Semiconductor, the high voltage complementary metal oxide semiconductors (CMOS)) in high-voltage applications more and more widely, topmost application comprises (the Liquid Crystal Display as LCD, LCD)/and LED(Light Emitting Diode, light-emitting diode) drive(drives) and the control circuit of power device.Along with the fast development of LCD/LED industry, the demand of respective drive device and the also corresponding increase of requirement.Require reaction speed faster, higher withstand voltage properties and unfailing performance, lower electric leakage and consumed power.
HV CMOS is because operating voltage higher (being generally 20-600V) is also high to the withstand voltage properties requirement of device, so leakage current wants big than Low-Voltage Logic Devices.And be a very complicated system for the high pressure chip that is used for LCD/LED drive, in order to realize its driveability, generally include a plurality of modules: high voltage device regions, low voltage logic district, embedded memory storage district, even also comprise middle compression functions district and analog circuit block.In the manufacturing technology that adopts, numerous modules realize in same set of light shield group and manufacturing process at present.This method of making simultaneously has simple, the lower-cost advantage of technology.But in fact, each module is because the difference of function, also is what to exist than big-difference to performance demands.The operating voltage in high tension apparatus zone big (generally at 20-300V) for example, so require to have higher withstand voltage properties and electric isolation performance preferably, and the operating voltage in static memory zone is generally about the 1-3 volt, characteristics such as the device that its functional requirement should the zone has fast, low electric leakage and high data stability.Particularly in device isolation, in 0.35um technology and more advanced technology node, the isolation of device all adopt the STI(shallow trench isolation from).As shown in Figure 1, the shallow trench owing to high voltage device regions HV and low voltage logic district in the prior art forms simultaneously, so the degree of depth of the shallow trench STI1 of high voltage device regions HV is identical with the shallow trench STI2 degree of depth in low voltage logic district.Because the operating voltage of higher-pressure region is higher, but still the degree of depth with the shallow trench in low voltage logic district is identical for the degree of depth, and then causes high voltage device regions that higher electric leakage is just arranged, and influences device performance.
For solving this contradiction, the designer who has uses for reference LDMOS (Laterally Diffused Metal Oxide Semiconductor, Laterally Diffused Metal Oxide Semiconductor) structure in the technological design of HV CMOS.Though this design a model can reduce electric leakage, improve withstand voltage, but because additional diffusion region area is bigger, make the high voltage structures of this LDMOS compared to big many of common high-voltage device structure area, thereby the valuable chip area of waste very, reduced the integrated level of chip.
Also have a kind of solution to be in the prior art, the STI degree of depth of entire chip is increased to the needed degree of depth of high tension apparatus.Low-pressure area also has the darker shallow trench isolation in higher-pressure region from the degree of depth like this, and then makes the isolation performance in low voltage logic district also increase.But because the limitation of manufacturing process, dark excessively etching depth requirement meeting brings serious challenge to etching technics.Darker etching depth also requires higher etching barrier layer and photoresistance, has proposed a difficult problem to photoetching process again.Darker groove, the filling difficulty of its dielectric film also increase greatly.Therefore, integral body adds the shallow trench isolation of large chip from the degree of depth, has not only strengthened the difficulty of manufacturing process, has reduced the manufacturability of chip; Simultaneously manufacturing cost is increased greatly, make complexity and increase, speed of production reduces.So there is limitation equally in this settling mode.
Chinese patent (publication number: CN102496573A) disclose a kind of manufacture method of insulated trench gate type bipolar transistor, may further comprise the steps:: substrate is provided, is divided into active area and terminal structure zone; Leave the window of guard ring in the terminal structure zone; Form the device guard ring by ion injection and diffusion technology at substrate; Form an oxygen at substrate surface, finish the active area definition; Form trench hard mask layer and photoresist layer at a substrate and an oxygen surface, and photoresist layer is done graphical; The etching groove hard mask layer exposes substrate; At substrate surface deposit side wall protective layer and time quarter, form the protection side wall in the both sides of trench hard mask layer side-walls, at substrate surface growth thermal oxide layer; With trench hard mask layer and protection side wall is hard mask, and etching thermal oxide layer and substrate form groove in substrate successively, and thermal oxide layer stretches between protection side wall and the substrate in the groove top, forms beak.
But it is identical to invent the final gash depth that forms, because the gash depth of zones of different is identical, causes certain regional leaky more serious easily, if the whole simultaneously degree of depth that adds deep trench, simultaneously also production cost can be improved, also certain influence can be caused to device performance simultaneously.
Therefore, how can existing technique initialization not being changed under the bigger prerequisite, realizing the differentiation manufacturing of the shallow trench isolation in high voltage device regions and low voltage logic district from the degree of depth, is a very meaningful problems.
Summary of the invention
The present invention provides a kind of semiconductor structure and preparation method who improves high tension apparatus shallow trench isolation performance according to the deficiencies in the prior art, by adopting Twi-lithography technology and etch process, high voltage device regions at semiconductor device forms two shallow channel isolation areas that the degree of depth is different with the low voltage logic district, and the shallow channel isolation area degree of depth of high voltage device regions is greater than the shallow channel isolation area degree of depth in low voltage logic district, and then slowed down the high problem of high tension apparatus electric leakage, improve the voltage endurance capability of high tension apparatus, and then improved HV device shallow trench isolation performance.
In order to realize above technical scheme, the technical solution used in the present invention is:
A kind of method that improves high voltage structures shallow trench isolation performance wherein, may further comprise the steps:
Step S1, provide a semiconductor structure with silicon substrate, described semiconductor structure comprises high voltage device regions and low voltage logic district, the upper surface of described substrate from bottom to top order successively growth one cushion oxide layer and a silicon nitride layer are arranged;
Step S2, employing photoetching, etching technics, preparation first groove in the high voltage device regions of described semiconductor structure, and form the silicon nitride retaining layer;
Step S3, preparation second anti-reflecting layer are full of described first groove and cover the upper surface of described silicon nitride retaining layer;
Step S4, eat-back described second anti-reflecting layer, form the second antireflection retaining layer that is positioned at described first groove, and continue photoetching, etching technics, in described low voltage logic district, prepare second groove to the upper surface of described silicon nitride retaining layer;
Wherein, the degree of depth of described first groove is greater than the degree of depth of described second groove.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance, wherein, described step S2 may further comprise the steps:
1) after the upper surface of described silicon nitride layer is grown first anti-reflecting layer, the spin coating photoresist covers the upper surface of this first anti-reflecting layer;
2) after exposure, the development, remove unnecessary photoresist, formation has the photoresistance of first channel patterns, and be mask with this photoresistance, described first anti-reflecting layer of etching, described silicon nitride layer are to the upper surface of described cushion oxide layer successively, after removing described photoresistance and remaining first anti-reflecting layer, form silicon nitride retaining layer with first channel patterns;
3) be the described cushion oxide layer of mask etching to described substrate with described silicon nitride retaining layer, form described first groove.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance, wherein, described step S4 may further comprise the steps:
1) eat-backs the upper surface of described second anti-reflecting layer, and in described first groove, form the second antireflection retaining layer to described silicon nitride retaining layer;
2) the spin coating photoresist covers the upper surface of described silicon nitride retaining layer and is full of the part that described first groove is not filled by the described second antireflection retaining layer simultaneously, after exposure, the development, remove unnecessary photoresist, formation has the photoresistance of second channel patterns, and be mask with this photoresistance, remaining cushion oxide layer of etching and substrate form second groove.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance wherein, adopts plasma etching substrate and residue substrate to form described first groove and second groove.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance, wherein, by controlling described plasma etching condition and then controlling the degree of depth of described first groove and second groove, to satisfy different process requirements.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance, wherein, the upper surface of the described second anti-reflecting layer remaining structure is positioned at the lower surface of residue oxide layer.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance, wherein, silicon substrate material monocrystalline silicon among the described step S1.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance, wherein, cushion oxide layer is a silicon oxide layer among the described step S1.
Above-mentioned a kind of method that improves high voltage structures shallow trench isolation performance, described first antireflecting coating is different with the material of described second antireflecting coating.
Because the present invention has adopted above technical scheme, can simply effectively make fleet plough groove isolation structure in the high voltage device regions and the Low-Voltage Logic Devices district of semiconductor structure, and then form the sti structure of two kinds of different depths in zones of different, simultaneously because the STI degree of depth of the semiconductor structure high voltage device regions that the present invention prepares is greater than the STI degree of depth in Low-Voltage Logic Devices district, slowed down the high problem of high tension apparatus electric leakage, improved the voltage endurance capability of high tension apparatus, and then improve HV device shallow trench isolation performance, promoted the overall performance of production technology and product.
Description of drawings
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is at the schematic diagram of the fleet plough groove isolation structure of high voltage device regions and low voltage logic district preparation in the prior art;
Fig. 2-13 is a kind of flow chart that improves the method for high voltage structures shallow trench isolation performance of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described:
A kind of method that improves high voltage structures shallow trench isolation performance that provides of the present invention specifically may further comprise the steps:
Step S1, provide a semiconductor structure with silicon substrate 100, as shown in Figure 2: this semiconductor structure comprises high voltage device regions HV and low voltage logic district LG, the upper surface of silicon substrate 100 is grown from bottom to top successively cushion oxide layer 101 and silicon nitride layer 102, in an embodiment of the present invention, silicon substrate 100 materials are monocrystalline silicon, and cushion oxide layer 101 materials are silica.
Step S2, in the upper surface of silicon nitride layer 102 one first anti-reflecting layer 103 of growing, the upper surface at first anti-reflecting layer 103 applies one deck photoresist 104 more then, forms structure shown in Figure 3 after this step is finished.
Step S3, expose, developing process, remove unnecessary photoresist 104, form photoresistance 104 with first channel patterns 108 ', first channel patterns 108 is positioned at the high voltage device regions HV of described semiconductor structure, formation structure shown in Figure 4 this step is finished after;
Step S4, utilize first channel patterns 108 etchings, first anti-reflecting layer 103 and the silicon nitride layer 102, in silicon nitride layer 102 form an opening 108 ', formation structure shown in Figure 5 this step is finished after.
Step S5, adopt wet-etching technology remove photoresistance 104 ' and the first anti-reflecting layer remaining structure 103 '.
Step S6, utilize silicon nitride retaining layer 102 ' opening 108 ' etching cushion oxide layer 101 to substrate 100, form first grooves 110.In an embodiment of the present invention, adopt plasma etching cushion oxide layer 101 and substrate 100, form structure shown in Figure 6 after this step is finished.
Step S7, growth second anti-reflecting layer 105 with cover silicon nitride retaining layer 102 ' upper surface fill described first groove 110 simultaneously, formation structure shown in Figure 7 this step is finished after.
Step S8, remove silicon nitride retaining layer 102 ' upper surface second anti-reflecting layer 105 simultaneously part remove second anti-reflecting layers 105 of filling in first groove 110, the formation second antireflection retaining layer 105 in first groove 110 ', this second antireflection retaining layer 105 ' upper surface a little less than cushion oxide layer 101 ' height and far above the bottom of first groove 110, form structure shown in Figure 8 after this step is finished.
Step S9, in silicon nitride retaining layer 102 ' upper surface apply one deck photoresist 106 and fill first groove 110 simultaneously, formation structure shown in Figure 9 after this step is finished not by the remainder of the second antireflection retaining layer 105 ' fillings.
Step S10, expose, developing process, remove unnecessary photoresist 106, formation have the photoresistance 106 of second channel patterns 109 ', this second channel patterns 109 is positioned at the low voltage logic area L G of described semiconductor structure, forms structure shown in Figure 10 after this step is finished.
Step S11, utilize second channel patterns, 109 etch silicon nitride retaining layers 102 ', in remaining nitride silicon layer 102 " form a breach 109 ', formation structure shown in Figure 11 this step is finished after.
Step S12, use wet etching remove photoresistance 106 ', formation structure shown in Figure 12 this step is finished after.
Step S13, utilize breach 109 ' carry out plasma etching industrial etching residue cushion oxide layer 101 ' and residue substrate 100 ' formations second groove 120, use then wet etching remove the second interior anti-reflective coating retaining layer 105 of first groove 110 '.After all finishing, this step forms structure shown in Figure 13, as shown in the figure, high voltage device regions at semiconductor structure is formed with i.e. first groove 110 of fleet plough groove isolation structure 110(), be formed with i.e. second groove 120 of fleet plough groove isolation structure 120(in the low voltage logic district), the depth H 2 of the fleet plough groove isolation structure 120 that depth H 1＞low voltage logic district of high voltage device regions formation fleet plough groove isolation structure 110 forms, and then slowed down the high problem of high tension apparatus electric leakage, improve the voltage endurance capability of high tension apparatus, and then improved HV device shallow trench isolation performance.
The present invention simultaneously since in first groove 110, be formed with in advance the second anti-reflective coating retaining layer 105 '; this second anti-reflective coating retaining layer 105 when using plasma etching to form second groove 120 '; avoid the damage that when using plasma etching to form second groove 120, first groove 110 caused, well protected first groove 110.Simultaneously in an embodiment of the present invention; the second anti-reflecting layer material 105 has adopted the material different with first anti-reflecting layer 103; first anti-reflecting layer 103 is in order better to carry out exposure imaging technology to guarantee the complete of first channel patterns 108; and the second anti-reflecting layer material 105 is to protect first groove 110 to avoid damage when plasma etching forms second groove 120 in order to carry out, so the anti-reflective coating layer material of twice preparation is inequality.
Step S14, carry out follow-up shallow trench fill process and chemical mechanical milling tech,, repeat no more in this present invention because this step technique scheme is a technical scheme conventionally known to one of skill in the art.
In sum, owing to adopt the method for raising high tension apparatus shallow trench isolation performance provided by the invention, can simply effectively make fleet plough groove isolation structure in the high voltage device regions and the Low-Voltage Logic Devices district of semiconductor structure, and then form the sti structure of two kinds of different depths in zones of different, simultaneously because the STI degree of depth of the semiconductor structure high voltage device regions that the present invention prepares is greater than the STI degree of depth in Low-Voltage Logic Devices district, slowed down the high problem of high tension apparatus electric leakage, improved the voltage endurance capability of high tension apparatus, and then improve HV device shallow trench isolation performance, promoted the overall performance of production technology and product.
It should be appreciated by those skilled in the art that those skilled in the art can realize described variation example in conjunction with prior art and the foregoing description, do not repeat them here.Such variation example does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, wherein equipment of not describing in detail to the greatest extent and structure are construed as with the common mode in this area and are implemented; Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (9)
1. a method that improves high voltage structures shallow trench isolation performance is characterized in that, may further comprise the steps:
Step S1, provide a semiconductor structure with silicon substrate, described semiconductor structure comprises high voltage device regions and low voltage logic district, the upper surface of described substrate from bottom to top order successively growth one cushion oxide layer and a silicon nitride layer are arranged;
Step S2, employing photoetching, etching technics, preparation first groove in the high voltage device regions of described semiconductor structure, and form the silicon nitride retaining layer;
Step S3, preparation second anti-reflecting layer are full of described first groove and cover the upper surface of described silicon nitride retaining layer;
Step S4, eat-back described second anti-reflecting layer, form the second antireflection retaining layer that is positioned at described first groove, and continue photoetching, etching technics, in described low voltage logic district, prepare second groove to the upper surface of described silicon nitride retaining layer;
Wherein, the degree of depth of described first groove is greater than the degree of depth of described second groove.
2. a kind of method that improves high voltage structures shallow trench isolation performance according to claim 1 is characterized in that described step S2 may further comprise the steps:
1) after the upper surface of described silicon nitride layer is grown first anti-reflecting layer, the spin coating photoresist covers the upper surface of this first anti-reflecting layer;
2) after exposure, the development, remove unnecessary photoresist, formation has the photoresistance of first channel patterns, and be mask with this photoresistance, described first anti-reflecting layer of etching, described silicon nitride layer are to the upper surface of described cushion oxide layer successively, after removing described photoresistance and remaining first anti-reflecting layer, form silicon nitride retaining layer with first channel patterns;
3) be the described cushion oxide layer of mask etching to described substrate with described silicon nitride retaining layer, form described first groove.
3. a kind of method that improves high voltage structures shallow trench isolation performance according to claim 1 is characterized in that described step S4 may further comprise the steps:
1) eat-backs the upper surface of described second anti-reflecting layer, and in described first groove, form the second antireflection retaining layer to described silicon nitride retaining layer;
2) the spin coating photoresist covers the upper surface of described silicon nitride retaining layer and is full of the part that described first groove is not filled by the described second antireflection retaining layer simultaneously, after exposure, the development, remove unnecessary photoresist, formation has the photoresistance of second channel patterns, and be mask with this photoresistance, remaining cushion oxide layer of etching and substrate form second groove.
4. according to claim 2 or 3 described a kind of methods that improve high voltage structures shallow trench isolation performance, it is characterized in that, adopt plasma etching substrate and residue substrate to form described first groove and second groove.
5. a kind of method that improves high voltage structures shallow trench isolation performance according to claim 6 is characterized in that, by controlling described plasma etching condition and then controlling the degree of depth of described first groove and second groove, to satisfy different process requirements.
6. a kind of method that improves high voltage structures shallow trench isolation performance according to claim 1 is characterized in that, the upper surface of the described second anti-reflecting layer remaining structure is positioned at the lower surface of residue oxide layer.
7. a kind of method that improves high voltage structures shallow trench isolation performance according to claim 1 is characterized in that, silicon substrate material monocrystalline silicon among the described step S1.
8. a kind of method that improves high voltage structures shallow trench isolation performance according to claim 1 is characterized in that cushion oxide layer is a silicon oxide layer among the described step S1.
9. a kind of method that improves high voltage structures shallow trench isolation performance according to claim 1, described first antireflecting coating is different with the material of described second antireflecting coating.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538309A (en) * | 2014-12-31 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Low on resistance LDMOS structure and manufacturing method thereof |
| CN105244350A (en) * | 2014-07-11 | 2016-01-13 | 联咏科技股份有限公司 | Integrated circuit of driving device and manufacturing method thereof |
| CN109273443A (en) * | 2018-11-22 | 2019-01-25 | 上海华力微电子有限公司 | The manufacturing method of SONOS device |
| CN110364525A (en) * | 2018-04-10 | 2019-10-22 | 世界先进积体电路股份有限公司 | Semiconductor structure and its manufacturing method |
| US11158533B2 (en) | 2018-11-07 | 2021-10-26 | Vanguard International Semiconductor Corporation | Semiconductor structures and fabrication method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050009290A1 (en) * | 2003-07-09 | 2005-01-13 | Jiang Yan | Method of forming shallow trench isolation using deep trench isolation |
| CN1862785A (en) * | 2005-05-12 | 2006-11-15 | 海力士半导体有限公司 | Verfahren zur herstellung eines halbleiterbauelements |
| CN101573791A (en) * | 2007-01-02 | 2009-11-04 | 国际商业机器公司 | High-z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
-
2013
- 2013-05-07 CN CN201310165188.0A patent/CN103227144B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050009290A1 (en) * | 2003-07-09 | 2005-01-13 | Jiang Yan | Method of forming shallow trench isolation using deep trench isolation |
| CN1862785A (en) * | 2005-05-12 | 2006-11-15 | 海力士半导体有限公司 | Verfahren zur herstellung eines halbleiterbauelements |
| CN101573791A (en) * | 2007-01-02 | 2009-11-04 | 国际商业机器公司 | High-z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244350A (en) * | 2014-07-11 | 2016-01-13 | 联咏科技股份有限公司 | Integrated circuit of driving device and manufacturing method thereof |
| CN104538309A (en) * | 2014-12-31 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Low on resistance LDMOS structure and manufacturing method thereof |
| CN110364525A (en) * | 2018-04-10 | 2019-10-22 | 世界先进积体电路股份有限公司 | Semiconductor structure and its manufacturing method |
| CN110364525B (en) * | 2018-04-10 | 2021-10-08 | 世界先进积体电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| US11158533B2 (en) | 2018-11-07 | 2021-10-26 | Vanguard International Semiconductor Corporation | Semiconductor structures and fabrication method thereof |
| CN109273443A (en) * | 2018-11-22 | 2019-01-25 | 上海华力微电子有限公司 | The manufacturing method of SONOS device |
| CN109273443B (en) * | 2018-11-22 | 2020-09-01 | 上海华力微电子有限公司 | Manufacturing method of SONOS device |
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