CN109270856A - For the electric power management circuit of low-consumption wireless chip - Google Patents
For the electric power management circuit of low-consumption wireless chip Download PDFInfo
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- CN109270856A CN109270856A CN201710569216.3A CN201710569216A CN109270856A CN 109270856 A CN109270856 A CN 109270856A CN 201710569216 A CN201710569216 A CN 201710569216A CN 109270856 A CN109270856 A CN 109270856A
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- 230000000087 stabilizing effect Effects 0.000 claims description 74
- 230000005669 field effect Effects 0.000 claims description 40
- 239000003990 capacitor Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000006641 stabilisation Effects 0.000 abstract 7
- 238000011105 stabilization Methods 0.000 abstract 7
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25236—Detail, detect presence of operator to wake up system
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25279—Switch on power, awake device from standby if detects action on device
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention discloses a kind of electric power management circuits for low-consumption wireless chip, comprising: master control digital logic module, operating mode power supply stabilization circuit and suspend mode power supply stabilization circuit；Wherein, the suspend mode power output end of the working power output end of operating mode power supply stabilization circuit and suspend mode power supply stabilization circuit is connect with the master control power input of master control digital logic module；The signal output end of master control digital logic module is connect with the control terminal of operating mode power supply stabilization circuit；In suspend mode, master control digital logic module controls operating mode power supply stabilization circuit and closes, to provide operating voltage as master control digital logic module by suspend mode power supply stabilization circuit in suspend mode.
Description
Technical Field
The present application relates to the field of electronic technologies, and for example, to a power management circuit for a low power consumption wireless chip.
Background
In recent years, electronic devices powered by batteries, such as handheld mobile devices, toys, and internet of things sensors, have been widely developed and popularized. How to reduce the power consumption of the wireless system and prolong the service life of the battery also becomes a key requirement of the system design in this aspect.
In a system of a wireless electronic device, not all modules or circuits are in an operating state all the time, some modules only need to operate under specific time or condition, and other time can be in a dormant state. Based on the consideration of reducing the power consumption of the system, the power supply circuit can be turned off when the system or some modules are in a dormant state, and then turned on when the system or the modules need to be awakened. Referring to fig. 1, a power management circuit for a low power wireless chip may include a main control digital logic module for controlling and managing an operating state of the entire system. In the aspect of power management, external power supply voltage can be converted into internal working power supply voltage through one or more voltage stabilizing circuits, and power supply voltage is provided for different circuit modules.
In the system, when the system is in a working state, each module is powered by the voltage stabilizing circuit to provide normal working state power consumption. When the system is in a dormant state, most of modules in the system and voltage-stabilized power supply circuits of the modules can be in a closed state so as to reduce power consumption. However, the master digital logic module also requires a power supply voltage to enable the master digital logic module to maintain a minimum power consumption operating state, such as holding values in registers and memories, maintaining a low speed clock generator, receiving an external wake-up signal to leave a sleep mode, and sending a start signal to start other circuit modules, etc. Therefore, the voltage regulator circuit that controls the digital circuit must also remain on during sleep mode. Because the voltage and power consumption requirements of the main control digital logic module in a working state need to be met by the voltage stabilizing power supply circuit, the power consumption of the voltage stabilizing power supply circuit cannot be made very small, and thus the system is difficult to maintain ultra-low power consumption in a dormant state.
Disclosure of Invention
The application provides a power management circuit to low-power consumption wireless chip to reduce the low-power consumption in sleep mode, reach the requirement of ultra-low power consumption.
The application provides a power management circuit for a low-power consumption wireless chip, which comprises a main control digital logic module, a working mode power supply voltage stabilizing circuit and a dormant mode power supply voltage stabilizing circuit;
the working power supply output end of the working mode power supply voltage stabilizing circuit and the dormant power supply output end of the dormant mode power supply voltage stabilizing circuit are both connected with the main control power supply input end of the main control digital logic module;
the signal output end of the main control digital logic module is connected with the control end of the working mode power supply voltage stabilizing circuit;
and in the sleep mode, the main control digital logic module controls the working mode power supply voltage stabilizing circuit to be closed, so that the working voltage is provided for the main control digital logic module through the sleep mode power supply voltage stabilizing circuit in the sleep mode.
And the signal input end of the main control digital logic module is used for receiving a sleep signal or a wake-up signal.
The sleep mode voltage stabilizing circuit comprises a sleep power supply input end, a negative feedback circuit, a current limiting resistor, a source follower and a sleep power supply output end;
the power supply end of the negative feedback circuit is connected with the input end of the dormant power supply, the output end of the negative feedback circuit is connected with the input end of the source electrode follower, the input end of the negative feedback circuit is connected with the output end of the dormant power supply, and the grounding end of the negative feedback circuit is connected with the ground wire;
the power end of the source electrode follower is connected with the input end of the dormant power supply through the current-limiting resistor, and the output end of the source electrode follower is connected with the output end of the dormant power supply.
The negative feedback circuit comprises a load resistor, a first N-type field effect transistor and a first P-type field effect transistor;
the first end of the load resistor is used as a power supply end of the negative feedback circuit, the second end of the load resistor is connected with the drain electrode of the first N-type field effect transistor to be used as an output end of the negative feedback circuit, the grid electrode of the first N-type field effect transistor is used as an input end of the negative feedback circuit, the source electrode of the first N-type field effect transistor is connected with the source electrode of the first P-type field effect transistor, and the drain electrode and the grid electrode of the first P-type field effect transistor are connected to be used as a grounding end of the negative feedback circuit.
The source follower is a second N-type field effect transistor, and a grid electrode, a drain electrode and a source electrode of the second N-type field effect transistor are respectively used as an input end, a power supply end and an output end of the source follower.
The second N-type field effect transistor is a depletion type field effect transistor.
The resistance value of the load resistor is megaohm level, and the resistance value of the current limiting resistor is kiloohm level.
The sleep mode voltage stabilizing circuit further comprises a compensation capacitor, wherein the first end of the compensation capacitor is connected with the output end of the negative feedback circuit, and the second end of the compensation capacitor is grounded.
The sleep mode voltage stabilizing circuit further comprises a third N-type field effect transistor;
and the drain electrode of the third N-type field effect transistor is connected with the output end of the dormant power supply, and the grid electrode and the source electrode of the third N-type field effect transistor are both grounded.
The load resistor is a polysilicon resistor.
The load resistor is at least one series narrow and long channel P-type field effect transistor with grounded grid electrode.
According to the technical scheme, the sleep mode power supply voltage stabilizing circuit is additionally connected with the working mode power supply voltage stabilizing circuit in parallel and is connected with the main control digital logic module. In the sleep mode, the main control numerical logic module controls the working mode power supply voltage stabilizing circuit to be turned off, so that the working voltage is provided for the main control digital logic module through the sleep mode power supply voltage stabilizing circuit in the sleep mode. Because the sleep mode power supply voltage stabilizing circuit only needs to supply power to the main control digital logic module in the sleep mode, and the working mode power supply voltage stabilizing circuit needs to supply power to the main control digital logic module in the working mode, the power consumption of the sleep mode power supply voltage stabilizing circuit is lower than that of the working mode power supply voltage stabilizing circuit, so that the power consumption can be reduced in the sleep mode, and the requirement of ultra-low power consumption is met.
Drawings
Fig. 1 is a schematic structural diagram of a power management circuit for a low power consumption wireless chip provided in the related art;
fig. 2 is a schematic structural diagram of a power management circuit for a low power consumption wireless chip provided in the present application;
FIG. 3 is a schematic diagram illustrating a structure of a voltage regulator circuit for a sleep mode power supply according to the present application;
FIG. 4 is a schematic diagram illustrating a structure of a voltage regulator circuit for a sleep mode power supply according to the present application;
FIG. 5 is a schematic diagram illustrating a structure of a voltage regulator circuit for a sleep mode power supply according to the present application; and
FIG. 6 is a schematic diagram illustrating a structure of a sleep mode power supply voltage regulator circuit according to the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. The embodiments described herein are merely illustrative and are not intended to limit the present application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures.
Fig. 2 is a schematic structural diagram of a power management circuit for a low power consumption wireless chip provided in an embodiment of the present application, as shown in fig. 2, the power management circuit for a low power consumption wireless chip includes a main control digital logic module 10, an operating mode power supply voltage stabilizing circuit 20, and a sleep mode power supply voltage stabilizing circuit 30;
the working power output end 202 of the working mode power supply voltage stabilizing circuit 20 and the sleep power output end 302 of the sleep mode power supply voltage stabilizing circuit 30 are both connected with the main control power supply input end 101 of the main control digital logic module 10;
the signal output end 102 of the main control digital logic module 10 is connected with the control end 203 of the working mode power supply voltage stabilizing circuit 20;
in the sleep mode, the main control digital logic module 10 controls the operation mode power supply voltage stabilizing circuit 20 to be turned off, so as to provide the operation voltage for the main control digital logic module 10 through the sleep mode power supply voltage stabilizing circuit 30 in the sleep mode.
The operating mode power supply voltage stabilizing circuit 20 is configured to supply power to the main control digital logic module 10 in an operating mode, so that the main control digital logic module 10 can control and manage an operating state of the system. Since the operating mode power supply voltage stabilizing circuit 20 needs to meet the voltage and power consumption requirements of the main control digital logic module 10 in the operating state, the power consumption of the operating mode power supply voltage stabilizing circuit 20 is relatively large. The sleep mode power supply voltage stabilizing circuit 30 is configured to supply power to the main control digital logic module 10 in the sleep mode, so that the main control digital logic module 10 maintains a low power consumption operating state: such as only holding values in registers and memory, maintaining a low speed clock generator, receiving an external wake-up signal to exit sleep mode, and sending enable signals to other circuit blocks.
In summary, since the power consumption of the main control digital logic module 10 in the sleep mode is much lower than the power consumption in the working mode, the power consumption of the sleep mode power supply voltage stabilizing circuit 30 is lower than the power consumption of the working mode power supply voltage stabilizing circuit 20.
In the technical scheme provided by this embodiment, a sleep mode power supply voltage stabilizing circuit connected in parallel with the operating mode power supply voltage stabilizing circuit and connected with the main control digital logic module is added. In the sleep mode, the main control numerical logic module controls the working mode power supply voltage stabilizing circuit to be turned off, so that the working voltage is provided for the main control digital logic module through the sleep mode power supply voltage stabilizing circuit in the sleep mode. Because the sleep mode power supply voltage stabilizing circuit only needs to supply power to the main control digital logic module in the sleep mode, and the working mode power supply voltage stabilizing circuit needs to supply power to the main control digital logic module in the working mode, the power consumption of the sleep mode power supply voltage stabilizing circuit is lower than that of the working mode power supply voltage stabilizing circuit, so that the power consumption can be reduced in the sleep mode, and the requirement of ultra-low power consumption is met.
In the working mode, the set output voltage of the working mode power supply voltage stabilizing circuit is higher than the set output voltage of the sleep mode power supply voltage stabilizing circuit, so that the output end of the sleep mode power supply voltage stabilizing circuit is automatically closed, and the output voltage of the working mode power supply voltage stabilizing circuit is not influenced.
The voltage stabilizing circuit structure of the sleep mode power supply provided by the embodiment can realize the voltage stabilizing function with ultra-low power consumption through a special negative feedback structure with a self-biasing function.
The technical solutions in the embodiments of the present application will be described in detail, clearly and completely in the following with reference to the accompanying drawings in the embodiments of the present application.
Based on the above embodiment, referring to fig. 2, the signal input terminal 103 of the main control digital logic module 10 is configured to receive a sleep signal or a wake-up signal, so as to control the operating state of the system, such as the operating state of the operating mode power supply voltage stabilizing circuit 20 or other power supply voltage stabilizing circuits, according to the received sleep signal or wake-up signal. The power input terminal 201 of the operating mode power supply voltage stabilizing circuit 20 and the power input terminal 301 of the sleep mode power supply voltage stabilizing circuit 30 are both connected to an external power supply.
Fig. 3 is a schematic structural diagram of a voltage stabilizing circuit of a sleep mode power supply provided in an embodiment of the present application. Referring to FIG. 3, the sleep mode power supply regulation circuit 30 may include a sleep power supply input Vin, a negative feedback circuit 31, a current limiting resistor R2, a source follower 32, and a sleep power supply output Vout.
The power source terminal 311 of the negative feedback circuit 31 is connected to the sleep power input terminal Vin, the output terminal 312 of the negative feedback circuit 31 is connected to the input terminal 323 of the source follower 32, the input terminal 313 of the negative feedback circuit 31 is connected to the sleep power output terminal Vout, and the ground terminal 314 of the negative feedback circuit 31 is connected to the ground.
The power source terminal 321 of the source follower 32 is connected to the sleep power input terminal Vin via a current limiting resistor R2
The output 322 of the source follower 32 is connected to the output Vout of the sleep power supply.
Referring to fig. 3, after the input terminal 313 of the negative feedback circuit 31 receives the output voltage of the sleep mode power supply voltage stabilizing circuit from the output terminal Vout of the sleep power supply, the voltage at the output terminal 312 of the negative feedback circuit 31 varies inversely with the voltage at the input terminal 313 due to the inverse amplification of the negative feedback circuit 31, so that the voltage at the output terminal Vout of the sleep power supply remains stable.
On the basis of the above embodiment, the negative feedback circuit can be realized by a load resistor, an N-type field effect transistor and a P-type field effect transistor. Referring to fig. 4, the negative feedback circuit 31 may include a load resistor R1, a first N-type fet MN2, and a first P-type fet MP 1.
A first end of the load resistor R1 is used as the power supply terminal 311 of the negative feedback circuit 31, a second end of the load resistor R1 is connected to the drain of the first N-type fet MN2 as the output terminal 312 of the negative feedback circuit 31, the gate of the first N-type fet MN2 is used as the input terminal 313 of the negative feedback circuit 31, the source of the first N-type fet MN2 is connected to the source of the first P-type fet MP1, and the drain and the gate of the first P-type fet MP1 are connected to the ground terminal 314 of the negative feedback circuit 31.
Referring to fig. 4, due to the special structure of the negative feedback circuit, the output voltage Vout of the regulator circuit of the sleep mode power supply can be substantially maintained at the threshold voltage of an N-fet plus the threshold voltage of a P-fet plus a sufficient overdrive voltage.
Referring to fig. 5, the source follower 32 may be a second N-type fet MN1, and the gate, drain and source of the second N-type fet MN1 are respectively used as the input 323, power terminal 321 and output terminal 322 of the source follower 32.
Referring to fig. 5, to allow for a lower external power source, the second N-type fet MN1 may be a depletion (Native) fet, for example. Optionally, since the gate voltage (input voltage) of the second N-type fet MN1 needs to be higher than the source voltage (output voltage) by a threshold voltage, and the threshold voltage of the depletion-type fet is close to 0, the gate voltage of the second N-type fet MN1 may be close to or lower than the source voltage, so as to effectively reduce the voltage of the external power source.
Referring to fig. 5, the load resistor R1 may have a resistance of mega-ohm, for example. Optionally, since the load resistor R1 is used to set the working current of the sleep mode power supply voltage stabilizing circuit, in order to make the power consumption of the sleep mode power supply voltage stabilizing circuit be in the sub-microampere level, the resistance of the load resistor R1 may be in the mega-ohm level. Optionally, in order to reduce the area of the sleep mode power supply voltage stabilizing circuit on a chip, the load resistor R1 may be a polysilicon resistor or a predetermined number of series-connected narrow and long channel P-type fets with grounded gates. It should be noted that, the preset value is not limited in this embodiment, and only the resistance of the load resistor R1 can reach the mega-ohm level.
Referring to fig. 5, the current limiting resistor R2 may have a value of kilo-ohm, for example. If the output end Vout of the sleep power supply is short-circuited with the ground wire, the current limiting resistor R2 can limit the first N-type FET MN2 and the output current, so as to prevent the circuit from being damaged due to the overlarge short-circuit current.
And the output of the sleep mode power supply voltage stabilizing circuit is connected with the output of the operating mode power supply voltage stabilizing circuit. Under the working mode, the output of the working mode power supply voltage stabilizing circuit is higher than the intrinsic output voltage of the sleep mode power supply voltage stabilizing circuit, namely the source electrode of the second N-type field effect transistor or the grid electrode voltage of the first N-type field effect transistor is pulled high, and due to the negative feedback effect of the first N-type field effect transistor, the grid electrode voltage of the second N-type field effect transistor is pulled low, so that the two N-type field effect transistors are not conducted, and therefore, under the working mode, the sleep mode power supply voltage stabilizing circuit does not influence the working of the working mode power supply voltage stabilizing circuit.
Referring to FIG. 6, for example, the sleep mode voltage regulator circuit may include a compensation capacitor C1, the compensation capacitor C1 having a first terminal connected to the output terminal 312 of the negative feedback circuit 31 and a second terminal connected to ground. Because the sleep mode voltage regulator circuit is a negative feedback structure, the compensation capacitor C1 is needed to make the open loop phase margin of the loop large enough to keep the sleep mode voltage regulator circuit in a stable state.
Referring to fig. 6, the sleep mode voltage regulation circuit may include, for example, a third N-type fet MN 3; the drain of the third N-type field effect transistor MN3 is connected to the output terminal Vout of the sleep power supply, and the gate and the source of the third N-type field effect transistor MN3 are both grounded. The gate of the third N-type fet MN3 is grounded and always in a non-conducting state, and only leakage current of nanoampere or picoampere level is present, so that the output Vout of the sleep power supply can keep the voltage not too high even in the absence of a load.
The technical scheme provided by the embodiment of the application can be used in a radio frequency wireless transceiving system of a 0.18um field effect transistor process, the allowable change index of the external input voltage is 1.9V-3.6V, and the working voltage of a core circuit is 1.8V. In the sleep mode, the output variation range of the sleep mode voltage-stabilized power supply circuit is 1.3V-1.6V, and the current of the whole system in the sleep mode is less than 1 uA.
The technical scheme provided by the embodiment of the application can provide stable power supply voltage for the main control digital logic control module under ultra-low power consumption, and the system can tolerate a larger external input power supply voltage variation range, effectively prolong the service life of a battery, and simultaneously have higher flexibility in system application.
Note that the above are only alternative embodiments of the present application. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, although the present application is described in more detail by the above embodiments, the present application is not limited to the above embodiments.
Claims (11)
1. A power management circuit for a low power consumption wireless chip, comprising: the digital logic circuit comprises a main control digital logic module, a working mode power supply voltage stabilizing circuit and a sleep mode power supply voltage stabilizing circuit; wherein,
the working power supply output end of the working mode power supply voltage stabilizing circuit and the dormant power supply output end of the dormant mode power supply voltage stabilizing circuit are both connected with the main control power supply input end of the main control digital logic module;
the signal output end of the main control digital logic module is connected with the control end of the working mode power supply voltage stabilizing circuit;
and in the sleep mode, the main control digital logic module controls the working mode power supply voltage stabilizing circuit to be closed, so that the working voltage is provided for the main control digital logic module through the sleep mode power supply voltage stabilizing circuit in the sleep mode.
2. The power management circuit for a low power consumption wireless chip of claim 1, wherein: and the signal input end of the main control digital logic module is used for receiving a sleep signal or a wake-up signal.
3. The power management circuit for a low power consumption wireless chip of claim 1, wherein: the sleep mode voltage stabilizing circuit comprises a sleep power supply input end, a negative feedback circuit, a current limiting resistor, a source follower and a sleep power supply output end;
the power supply end of the negative feedback circuit is connected with the input end of the dormant power supply, the output end of the negative feedback circuit is connected with the input end of the source electrode follower, the input end of the negative feedback circuit is connected with the output end of the dormant power supply, and the grounding end of the negative feedback circuit is connected with the ground wire;
the power end of the source electrode follower is connected with the input end of the dormant power supply through the current-limiting resistor, and the output end of the source electrode follower is connected with the output end of the dormant power supply.
4. The power management circuit for a low power consumption wireless chip of claim 3, wherein:
the negative feedback circuit comprises a load resistor, a first N-type field effect transistor and a first P-type field effect transistor;
the first end of the load resistor is used as a power supply end of the negative feedback circuit, the second end of the load resistor is connected with the drain electrode of the first N-type field effect transistor to be used as an output end of the negative feedback circuit, the grid electrode of the first N-type field effect transistor is used as an input end of the negative feedback circuit, the source electrode of the first N-type field effect transistor is connected with the source electrode of the first P-type field effect transistor, and the drain electrode and the grid electrode of the first P-type field effect transistor are connected to be used as a grounding end of the negative feedback circuit.
5. The power management circuit for a low power consumption wireless chip of claim 4, wherein:
the source follower is a second N-type field effect transistor, and a grid electrode, a drain electrode and a source electrode of the second N-type field effect transistor are respectively used as an input end, a power supply end and an output end of the source follower.
6. The power management circuit for a low power consumption wireless chip of claim 5, wherein: the second N-type field effect transistor is a depletion type field effect transistor.
7. The power management circuit for a low power consumption wireless chip of claim 5, wherein: the resistance value of the load resistor is megaohm level, and the resistance value of the current limiting resistor is kiloohm level.
8. The power management circuit for a low power consumption wireless chip of claim 4, wherein: the sleep mode voltage stabilizing circuit further comprises a compensation capacitor, wherein the first end of the compensation capacitor is connected with the output end of the negative feedback circuit, and the second end of the compensation capacitor is grounded.
9. The power management circuit for a low power consumption wireless chip of claim 4, wherein: the sleep mode voltage stabilizing circuit further comprises a third N-type field effect transistor;
and the drain electrode of the third N-type field effect transistor is connected with the output end of the dormant power supply, and the grid electrode and the source electrode of the third N-type field effect transistor are both grounded.
10. The power management circuit for a low power consumption wireless chip of claim 4, wherein: the load resistor is a polysilicon resistor.
11. The power management circuit for a low power consumption wireless chip of claim 4, wherein: the load resistor is at least one series narrow and long channel P-type field effect transistor with grounded grid electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710569216.3A CN109270856A (en) | 2017-07-13 | 2017-07-13 | For the electric power management circuit of low-consumption wireless chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710569216.3A CN109270856A (en) | 2017-07-13 | 2017-07-13 | For the electric power management circuit of low-consumption wireless chip |
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| CN109270856A true CN109270856A (en) | 2019-01-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105958799A (en) * | 2016-06-28 | 2016-09-21 | 上海晶曦微电子科技有限公司 | Power management circuit |
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| CN207781206U (en) * | 2018-04-02 | 2018-08-28 | 睿力集成电路有限公司 | Suspend mode stationary state logic circuit, semiconductor memory |
| CN110570644A (en) * | 2019-09-24 | 2019-12-13 | 广州华端科技有限公司 | Remote control device |
| CN110908493A (en) * | 2019-11-15 | 2020-03-24 | 浙江大华技术股份有限公司 | Power supply control method and device |
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- 2017-07-13 CN CN201710569216.3A patent/CN109270856A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958799A (en) * | 2016-06-28 | 2016-09-21 | 上海晶曦微电子科技有限公司 | Power management circuit |
| CN108447514A (en) * | 2018-04-02 | 2018-08-24 | 睿力集成电路有限公司 | Semiconductor memory, suspend mode stationary state logic circuit and its suspend mode stationary state method |
| CN207781206U (en) * | 2018-04-02 | 2018-08-28 | 睿力集成电路有限公司 | Suspend mode stationary state logic circuit, semiconductor memory |
| CN110570644A (en) * | 2019-09-24 | 2019-12-13 | 广州华端科技有限公司 | Remote control device |
| CN110908493A (en) * | 2019-11-15 | 2020-03-24 | 浙江大华技术股份有限公司 | Power supply control method and device |
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Application publication date: 20190125 |
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| RJ01 | Rejection of invention patent application after publication |