CN116300546A - Circuit structure for realizing MCU low-power consumption power management and switching method thereof - Google Patents
Circuit structure for realizing MCU low-power consumption power management and switching method thereof Download PDFInfo
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- CN116300546A CN116300546A CN202111569033.4A CN202111569033A CN116300546A CN 116300546 A CN116300546 A CN 116300546A CN 202111569033 A CN202111569033 A CN 202111569033A CN 116300546 A CN116300546 A CN 116300546A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a circuit structure for realizing MCU low-power consumption power management, wherein the circuit structure comprises: the first low dropout linear voltage regulator unit (LDOA) is used for starting a circuit to work after receiving a high-level signal sent by an external digital logic unit (logic) and outputting a large current to enable the circuit structure to enter a high-performance mode; and the second low dropout linear voltage regulator unit (LDOB) is used for starting a circuit to work after receiving a low-level signal sent by the external digital logic unit (logic) and outputting low current so that the circuit structure enters an ultra-low power consumption mode. The invention also relates to a corresponding switching method. The circuit structure for realizing MCU low-power consumption power management and the switching method thereof have the advantages of simple structure, less required circuit devices, chip area saving, simple and easy realization of the switching process and capability of effectively improving the chip yield.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to the technical field of power management, and particularly relates to a circuit structure for realizing MCU low-power consumption power management and a switching method thereof.
Background
In the MCU (micro controller unit) design process, how to realize high performance and low power consumption is always a design difficulty, especially the current MCU circuit scale is larger and larger, the power consumption problem of the MCU is also more prominent, and the low power consumption design becomes a hotspot and a difficulty of the MCU design. The low-power consumption design of the MCU is realized, the endurance time of the equipment can be greatly increased in an application scene using battery power supply, the temperature of the MCU during operation can be reduced, and the service life of the equipment can be prolonged.
In the existing MCU design, a low-power mode is mostly adopted to reduce the power consumption current of the MCU during sleep, specifically, the work frequency of the MCU is switched to a low-frequency mode when the equipment has few or no work tasks, and meanwhile, part of digital modules are closed to reduce the power consumption current of the MCU during standby.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a circuit structure for realizing MCU low-power-consumption power management with simple structure and lower power consumption and a switching method thereof.
In order to achieve the above purpose, the circuit structure for realizing MCU low power consumption power management and the switching method thereof of the present invention are as follows:
the circuit structure for realizing MCU low-power consumption power management is mainly characterized by comprising:
the first low-dropout linear voltage stabilizing unit is used for starting a circuit to work after receiving a high-level signal sent by the external digital logic unit and outputting a large current to enable the circuit structure to enter a high-performance mode; and
the second low-voltage difference linear voltage stabilizing unit is used for starting a circuit to work after receiving a low-level signal sent by the external digital logic unit and outputting low current to enable the circuit structure to enter an ultra-low power consumption mode;
and the output end of the first low-voltage-difference linear voltage-stabilizing unit and the output end of the second low-voltage-difference linear voltage-stabilizing unit are connected with the digital circuit at the rear end, and are used for controlling the working state of the small load and/or the large load of the digital circuit.
Preferably, the system further comprises a central processing unit, wherein the central processing unit comprises the external digital logic unit,
the first enabling input end of the external digital logic unit is used for inputting a low-power consumption mode signal;
the second enabling input end of the external digital logic unit is used for inputting a linear voltage stabilizing signal;
the first enabling output end of the external digital logic unit is used for inputting a first logic control signal to the second low dropout linear voltage stabilizing unit through the central processing unit;
the second enabling output end of the external digital logic unit is used for inputting a second logic control signal to the first low dropout linear voltage stabilizing unit through the central processing unit.
Preferably, the first low dropout linear voltage regulator unit specifically includes:
the first end of the operational amplifier is used for receiving a first reference voltage output by the band gap reference circuit;
the grid electrode of the third PMOS field effect transistor is connected with the output end of the operational amplifier, and the drain electrode of the third PMOS field effect transistor is used for being connected with a power supply voltage;
a first adjustable resistor and a second resistor;
the second resistor is connected between the second end of the operational amplifier and the source electrode of the third PMOS field effect transistor;
the first adjustable resistor is connected between the second resistor and the ground.
Preferably, the circuit structure is further provided with a control signal, and the control signal is used for setting the resistance value of the first adjustable resistor.
Preferably, the second low dropout linear voltage regulator unit specifically includes:
the grid electrode of the first PMOS field effect transistor is used for being connected with the first logic control signal, and the drain electrode of the first PMOS field effect transistor is used for outputting bias current;
the grid electrode of the second PMOS field effect tube is grounded, and the drain electrode of the second PMOS field effect tube is used for being connected with a power supply voltage;
the grid electrode and the drain electrode of the second NMOS field effect tube are connected with the source electrode of the first PMOS field effect tube;
the grid electrode and the drain electrode of the first NMOS field effect tube are connected with the source electrode of the second NMOS field effect tube; and
the drain electrode of the third NMOS field effect tube is connected with the source electrode of the second PMOS field effect tube, the grid electrode of the third NMOS field effect tube is connected with the grid electrode and the drain electrode of the second NMOS field effect tube, and the source electrode of the third NMOS field effect tube is connected between the third PMOS field effect tube and the second resistor.
Preferably, the resistance value of the first adjustable resistor is adjusted by the control signal, so that the second low-power-consumption voltage driving current is output by the second low-dropout linear voltage stabilizing unit.
The method for realizing low-power switching of the dual-LDO structure by utilizing the circuit structure is mainly characterized by comprising the following steps of:
(1) The chip enters a first working period, the circuit structure is in a high-performance mode, and the first low-dropout linear voltage stabilizing unit and the second low-dropout linear voltage stabilizing unit execute circuit processing in the mode;
(2) Judging whether the micro control unit receives an externally transmitted command for switching the low power consumption mode, if so, entering a step (3), otherwise, continuing to maintain the processing of the step (1);
(3) The micro control unit sends out a switching low-power consumption command;
(4) The chip enters a second working period, and the second low-voltage difference linear voltage stabilizing unit enters an ultralow power consumption mode according to the received low-power consumption command and executes circuit processing under the mode.
Preferably, the step (1) specifically includes the following steps:
the micro control unit sets the low power consumption mode signal to be in a cut-off state and sets the linear voltage stabilizing signal to be in a conduction state;
(1.2) after the processing of the external digital logic unit, the first logic control signal outputs a low level signal, and the second logic control signal outputs a high level signal;
the operational amplifier receives a high level signal output by the second logic control signal, and the first low dropout linear voltage stabilizing unit starts to work;
the first PMOS field-effect transistor of (1.4) receives the low-level signal output by the first logic control signal, and the second low dropout linear voltage regulator unit starts to operate.
Preferably, the step (4) specifically includes the following steps:
the second low dropout linear voltage stabilizing unit receives a low power consumption command sent by the micro control unit (4.1);
(4.2) the micro control unit sets the low power command to a low level, turns off a heavy load circuit which does not maintain the basic function of the chip, and then enters a delay state;
(4.3) after the delay is finished, the micro control unit sets the low-power consumption mode signal and the linear voltage stabilizing signal to be in a conducting state;
(4.4) after the processing of the external digital logic unit, the first logic control signal outputs a low level signal, and the second logic control signal outputs a low level signal;
after the operational amplifier receives the low level signal output by the second logic control signal, the first low dropout linear voltage regulator unit turns off the circuit;
and (4.6) the first PMOS field effect transistor receives the low-level signal output by the first logic control signal, and the second low-dropout linear voltage stabilizing unit keeps in a working state.
Preferably, the driving currents output by the first low dropout linear voltage stabilizing unit and the second low dropout linear voltage stabilizing unit are of uA level, so that the circuit structure meets the requirement of ultra-low power consumption.
By adopting the circuit structure for realizing MCU low-power consumption power management and the switching method thereof, when the working frequency of the circuit is reduced and the circuit is in a low-power consumption mode, the low-power consumption LDO structure is adopted, the power consumption is further reduced, the low-power consumption LDO structure is simple and easy to realize, few circuit devices are added in the circuit structure, no extra bias voltage is needed, only 5 MOS tubes are needed, and the chip area is greatly saved by integrating the circuit structure into the chip. The novel low-power LDO structure can work with a high-performance LDO at the same time, and cannot affect each other.
Drawings
Fig. 1 is a schematic circuit structure diagram of the MCU low-power consumption power management according to the present invention.
Fig. 2 is a schematic diagram of a method for implementing low power switching of a dual LDO structure according to the present invention.
Fig. 3 is a timing diagram of low power switching of the dual LDO structure of the present invention.
Reference numerals
LDOA first low dropout linear voltage stabilizing unit
LDOB second low dropout linear voltage stabilizing unit
logic digital logic unit
CPU central processing unit
Standby_enh low power mode signal
LDO 15-PDN linear voltage stabilizing signal
PDN first logic control signal
STANDBY second logic control signal
AMP operational amplifier
BGR band gap reference circuit
VBG first reference voltage
VDDD50 supply voltage
MP1 first PMOS field effect transistor
MP2 second PMOS field effect transistor
MP3 third PMOS field effect transistor
mn1 first NMOS field effect transistor
mn2 second NMOS field effect transistor
Native_mn3 third NMOS field effect transistor
R1 first adjustable resistor
R2 second resistor
LDO15_TRIM <4:0> control signals
MCU micro-control unit
ENZ low power command
Standby_enh low power mode signal
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that relational terms, such as first and second, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 1, the circuit structure for implementing MCU low-power consumption power management includes:
the first LDOA is used for starting a circuit to work after receiving a high-level signal sent by an external digital logic unit logic and outputting a large current to enable the circuit structure to enter a high-performance mode; and
the second low dropout linear voltage regulator unit LDOB is used for starting a circuit to work after receiving a low-level signal sent by an external digital logic unit logic and outputting low current to enable the circuit structure to enter an ultra-low power consumption mode;
and the output end of the first low dropout linear voltage regulator unit LDOA and the output end of the second low dropout linear voltage regulator unit LDOB are connected with a digital circuit at the rear end, and are used for controlling and processing the working state of the small load and/or the large load of the digital circuit.
As a preferred embodiment of the invention, it further comprises a central processing unit CPU comprising said external digital logic unit logic, wherein,
the first enabling input end of the external digital logic unit logic is used for inputting a low-power consumption mode signal standby_enh;
the second enabling input end of the external digital logic unit logic is used for inputting a linear voltage stabilizing signal LDO15_PDN;
the first enabling output end of the external digital logic unit logic is used for inputting a first logic control signal PDN to the second low dropout linear voltage stabilizing unit LDOB through the CPU;
the second enabling output end of the external digital logic unit logic is used for inputting a second logic control signal STANDBY to the first low dropout linear voltage stabilizing unit LDOA through the CPU.
As a preferred embodiment of the present invention, the first low dropout linear regulator unit LDOA specifically includes:
an operational amplifier AMP, a first end of which is configured to receive a first reference voltage VBG output by the bandgap reference circuit BGR;
the grid electrode of the third PMOS field effect transistor mp3 is connected with the output end of the operational amplifier AMP, and the drain electrode of the third PMOS field effect transistor mp3 is used for being connected with the power supply voltage VDDD50;
the first adjustable resistor R1 and the second resistor R2;
the second resistor R2 is connected between the second end of the operational amplifier AMP and the source electrode of the third PMOS field effect transistor mp 3;
the first adjustable resistor R1 is connected between the second resistor R2 and the ground.
In practical application, the LDOA is composed of an operational amplifier AMP, a MOS transistor mp3, and resistors R2 and R1. R1 is an adjustable resistor, and is controlled by setting LDO15_TRIM<4:0>The resistance value may be set to change the output voltage of VDDD 15. AMP may be turned on high through the signal line STANDBY. In addition, LDOA requires a bias voltage VBG, which is typically generated by a bandgap reference circuit BRG. The LDOA working principle in fig. 1 is that vp=vbg=v under feedback of op AMP bias The voltage at VDDD15 is therefore:
VDDD15＝V bias ×(R2+R1)/R1；
by adjusting the resistances of R2 and R1, the voltage of VDDD15 can be adjusted to 1.5V.
As a preferred embodiment of the present invention, the circuit structure is further provided with a control signal LDO15_TRIM <4:0>, and the control signal LDO15_TRIM <4:0> is used for setting the resistance value of the first adjustable resistor R1.
As a preferred embodiment of the present invention, the second low dropout linear regulator unit LDOB specifically includes:
the first PMOS field effect transistor mp1, wherein the grid electrode of the first PMOS field effect transistor mp1 is used for being connected with the first logic control signal PDN, and the drain electrode of the first PMOS field effect transistor mp1 is used for outputting bias current IBIAS0;
the grid electrode of the second PMOS field effect tube mp2 is grounded, and the drain electrode of the second PMOS field effect tube mp2 is used for being connected with the power supply voltage VDDD50;
the grid electrode and the drain electrode of the second NMOS field effect tube mn2 are connected with the source electrode of the first PMOS field effect tube mp 1;
the grid electrode and the drain electrode of the first NMOS field effect tube mn1 are connected with the source electrode of the second NMOS field effect tube mn 2; and
the drain electrode of the third NMOS field effect tube Native_mn3 is connected with the source electrode of the second PMOS field effect tube mp2, the grid electrode of the third NMOS field effect tube Native_mn3 is connected with the grid electrode of the second NMOS field effect tube mn2, and the source electrode of the third NMOS field effect tube Native_mn3 is connected between the third PMOS field effect tube mp3 and the second resistor R2.
As a preferred embodiment of the present invention, the resistance of the first adjustable resistor R1 is adjusted by the control signal LDO15_TRIM <4:0>, so that the second LDOB outputs the required low power consumption voltage driving current.
In practical application, the LDOB is composed of two P-type MOS transistors mp1 and mp2 and three N-type MOS transistors mn1, mn2 and native_mn3, and the working principle is that the mn1 and mn2 transistors adopt diode connection under the action of bias current of IBIAS0 to generate a voltage of 1.5V at Vp point. The mn3 tube is a native tube, a normally open tube, and also 1.5V at its source (V15). Ldos require a bias current derived from a low frequency oscillator, and all MCU chips will have low frequency oscillators, requiring no additional bias circuits, unlike ldos which require additional bandgap reference circuits. The circuit structure of the LDOB is very simple, the required basic devices (resistor, capacitor and MOS tube) are few, and the LDOB occupies a small area when integrated into the chip, which means lower cost. The 1.5V voltage driving current generated by the structure is only at uA level, and the power consumption current of the whole circuit is very small, so that the ultra-low power consumption requirement is met.
The method for realizing low-power switching of the dual-LDO structure by utilizing the circuit structure comprises the following steps:
(1) The chip enters a first working period, the circuit structure is in a high-performance mode, and the first low-dropout linear voltage stabilizing unit LDOA and the second low-dropout linear voltage stabilizing unit LDOB execute circuit processing in the mode;
(2) Judging whether the MCU receives an externally transmitted command for switching the low power consumption mode, if so, entering a step (3), otherwise, continuing to maintain the processing of the step (1);
(3) The MCU sends a switching low-power-consumption command ENZ;
(4) The chip enters a second working period, and the second low dropout linear voltage regulator unit LDOB enters an ultra-low power consumption mode according to the received low power consumption command ENZ and executes circuit processing under the mode.
As a preferred embodiment of the present invention, the step (1) specifically includes the steps of:
the micro control unit MCU of (1.1) sets the low power consumption mode signal STANDBY_ENH to be in an off state, and sets the linear voltage stabilizing signal LDO15_PDN to be in an on state;
(1.2) after the processing of the external digital logic unit logic, the first logic control signal PDN outputs a low level signal, and the second logic control signal STANDBY outputs a high level signal;
the operational amplifier AMP receives the high level signal output by the second logic control signal STANDBY, and the first low dropout linear voltage regulator unit LDOA starts to operate;
the first PMOS fet mp1 described in (1.4) receives the low level signal output by the first logic control signal PDN, and the second low dropout linear regulator LDOB starts to operate.
As a preferred embodiment of the present invention, the step (4) specifically includes the following steps:
the second low dropout linear regulator unit LDOB described in (4.1) receives the low power consumption command ENZ sent by the MCU;
(4.2) the micro control unit MCU sets the low power command ENZ to a low level, turns off a heavy load circuit which does not maintain the basic function of the chip, and then enters a delay state;
(4.3) after the delay is finished, the micro control unit MCU sets the low power consumption mode signal standby_enh and the linear voltage stabilizing signal LDO15_PDN to be in a conducting state;
(4.4) after the processing of the external digital logic unit logic, the first logic control signal PDN outputs a low level signal, and the second logic control signal STANDBY outputs a low level signal;
after receiving the low level signal output by the second logic control signal STANDBY, the operational amplifier AMP described in (4.5) turns off the LDOA circuit;
the first PMOS fet mp1 described in (4.6) receives the low level signal output by the first logic control signal PDN, and the second low dropout linear regulator unit LDOB continues to maintain the operating state.
As a preferred embodiment of the invention, the driving current output by the first LDO and the second LDO is of uA level, so as to realize that the circuit structure meets the requirement of ultra-low power consumption.
In practical application, when the MCU enters the first working period, the digital circuit needs a large current when the chip is in the high-performance mode, and at this time, standby_enh=0 and ldos15_pdn=1, PDN outputs a low level after being processed by the digital unit logic, STANDBY outputs a high level, AMP receives the high level and then the circuit is turned on, LDOA starts working, and a large current is output. mp1 is a P-type MOS tube, and when receiving the low level of PDN, the LDOB circuit starts to work. Since the output current of LDOB is large relative to LDOB, LDOB has little contribution to VDDD15 supply current, and LDOB can be considered to be inoperative at this time.
In practical application, when the MCU enters the second working period, the MCU sends out command ENZ to turn off the heavy load circuit which does not maintain the basic function of the chip when the chip is to enter the ultra-low power consumption mode, after a delay time (in order to ensure smooth switching of the dual LDO structure, the delay time needs to be ensured to be as long as possible), then the MCU will make standby_enh=1, LDO 15_pdn=1, PDN output low level after logic processing of the digital unit, STANDBY output low level, AMP receives low level and then turns off the circuit. The LDOB is still low level, so that the circuit continuously works, and the low power consumption operation of the chip is ensured by outputting small current.
Referring to fig. 2, in the low power switching process of the present invention, since LDOB only outputs uA-level current, if the lddb is directly switched without considering the load change, VDDD15 is powered down and the chip is disabled and reset, a switching sequence is required when switching from normal operation to low power mode. The MCU receives the command of switching the low power consumption mode, the MCU firstly sends the low power consumption command ENZ, the ENZ is set to be low level, the large load circuit module of the digital circuit is turned off immediately, but the small load circuit involved in the ENZ cannot be turned off immediately, a delay time is needed, after the MCU delays for a period of time, only some small load circuit modules which maintain the operation of the chip in the digital circuit only need small current, then the MCU pulls STANDBY to be low level, the LDOA is turned off, and the MCU enters the low power consumption mode.
It can be seen that the LDOB is always operated in the normal operation and the low power consumption mode in the present technical solution, so the whole switching process is very simple. When the MCU needs to restore the normal working mode, the MCU only needs to start the LDOA first, and after a period of stable time, the MCU can start all the digital circuits.
Referring to fig. 3, in an embodiment of the present invention, a timing chart of low power switching of a dual LDO structure is shown in fig. 3:
when the circuit structure receives a low-power-consumption command ENZ sent by the MCU, the low-power-consumption command ENZ is immediately placed in a low-level state, and then enters a delay state, in the process, the first logic control signal PDN always maintains the low-level state, namely the second low-dropout linear voltage stabilizing unit LDOB is in a working state in a normal working mode or a low-power-consumption mode; and after the same delay time, the second logic control signal STANDBY is switched from the original high-level state to the low-level state, namely the current circuit enters a low-power consumption mode, and the first low dropout linear voltage regulator unit LDOA stops working.
It should be noted that, in the dual LDO structure, the switching between the two LDO structures needs to be performed after the circuit is in the low power mode and stable, which is beneficial to that, since the driving current of the LDO is small, the module with larger power consumption current in the digital circuit needs to be turned off before the LDO is turned off, and the LDO is turned off after the digital circuit is in the sleep mode and stable. There is therefore a need to make some demands on the switching timing of the two LDOs.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution device.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, where the program when executed includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented as software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
By adopting the circuit structure for realizing MCU low-power consumption power management and the switching method thereof, when the working frequency of the circuit is reduced and the circuit is in a low-power consumption mode, the low-power consumption LDO structure is adopted, the power consumption is further reduced, the low-power consumption LDO structure is simple and easy to realize, few circuit devices are added in the circuit structure, no extra bias voltage is needed, only 5 MOS tubes are needed, and the chip area is greatly saved by integrating the circuit structure into the chip. The novel low-power LDO structure can work with a high-performance LDO at the same time, and cannot affect each other.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (10)
1. The circuit structure for realizing MCU low-power consumption power management is characterized by comprising:
the first low dropout linear voltage regulator unit (LDOA) is used for starting a circuit to work after receiving a high-level signal sent by an external digital logic unit (logic) and outputting a large current to enable the circuit structure to enter a high-performance mode; and
the second low dropout linear voltage regulator unit (LDOB) is used for starting a circuit to work after receiving a low-level signal sent by an external digital logic unit (logic) and outputting low current to enable the circuit structure to enter an ultra-low power consumption mode;
the output end of the first low dropout linear voltage stabilizing unit (LDOA) and the output end of the second low dropout linear voltage stabilizing unit (LDOB) are connected with a digital circuit at the rear end, and the digital circuit is used for controlling and processing the working state of a small load and/or a large load of the digital circuit.
2. The circuit structure for implementing MCU low power consumption power management of claim 1, further comprising a Central Processing Unit (CPU) including said external digital logic unit (logic), wherein,
the first enabling input end of the external digital logic unit (logic) is used for inputting a low power consumption mode signal (STANDBY_ENH);
the second enabling input end of the external digital logic unit (logic) is used for inputting a linear voltage stabilizing signal (LDO15_PDN);
the first enabling output end of the external digital logic unit (logic) is used for inputting a first logic control signal (PDN) to the second low dropout linear voltage stabilizing unit (LDOB) through the Central Processing Unit (CPU);
the second enable output end of the external digital logic unit (logic) is used for inputting a second logic control Signal (STANDBY) to the first low dropout linear voltage regulator unit (LDOA) through the Central Processing Unit (CPU).
3. The circuit structure for implementing MCU low power consumption power management as defined in claim 2, wherein said first low dropout linear regulator unit (LDOA) comprises:
an operational Amplifier (AMP), a first terminal of the operational Amplifier (AMP) being configured to receive a first reference Voltage (VBG) output by the bandgap reference circuit (BGR);
the grid electrode of the third PMOS field effect transistor (mp 3) is connected with the output end of the operational Amplifier (AMP), and the drain electrode of the third PMOS field effect transistor (mp 3) is used for being connected with a power supply voltage (VDDD 50);
a first adjustable resistor (R1) and a second resistor (R2);
the second resistor (R2) is arranged between the second end of the operational Amplifier (AMP) and the source electrode of the third PMOS field effect transistor (mp 3); the first adjustable resistor (R1) is arranged between the second resistor (R2) and the ground.
4. A circuit arrangement for implementing MCU low power consumption power management as defined in claim 3, further provided with a control signal (ldO15_TRIM <4:0 >), said control signal (ldO15_TRIM <4:0 >) being used to set the resistance of said first adjustable resistor (R1).
5. The circuit structure for implementing low power consumption power management of MCU as defined in claim 4, wherein said second low dropout linear regulator unit (LDOB) comprises:
the first PMOS field effect transistor (mp 1), the grid electrode of the first PMOS field effect transistor (mp 1) is used for being connected with the first logic control signal (PDN), and the drain electrode of the first PMOS field effect transistor (mp 1) is used for outputting bias current (IBIAS 0);
the grid electrode of the second PMOS field effect tube (mp 2) is grounded, and the drain electrode of the second PMOS field effect tube (mp 2) is used for being connected with a power supply voltage (VDDD 50);
the grid electrode and the drain electrode of the second NMOS field effect tube (mn 2) are connected with the source electrode of the first PMOS field effect tube (mp 1);
the grid electrode and the drain electrode of the first NMOS field effect tube (mn 1) are connected with the source electrode of the second NMOS field effect tube (mn 2); and
the drain electrode of the third NMOS field effect tube (native_mn3) is connected with the source electrode of the second PMOS field effect tube (mp 2), the grid electrode of the third NMOS field effect tube (native_mn3) is connected with the grid electrode of the second NMOS field effect tube (mn 2) and the drain electrode, and the source electrode of the third NMOS field effect tube (native_mn3) is arranged between the third PMOS field effect tube (mp 3) and the second resistor (R2).
6. The circuit structure for implementing low power consumption power management of MCU according to claim 5, wherein the resistance value of the first adjustable resistor (R1) is adjusted by the control signal (ldo15_trim <4:0 >) so that the second low dropout linear regulator unit (LDOB) outputs the required low power consumption voltage driving current.
7. A method for implementing low power switching of a dual LDO structure by using the circuit structure of any of claims 1 to 6, comprising the steps of:
(1) The chip enters a first working period, the circuit structure is in a high-performance mode, and the first low-dropout linear voltage stabilizing unit (LDOA) and the second low-dropout linear voltage stabilizing unit (LDOB) execute circuit processing in the mode;
(2) Judging whether a Micro Control Unit (MCU) receives an externally transmitted command for switching the low power consumption mode, if so, entering a step (3), otherwise, continuing to maintain the processing of the step (1);
(3) The Micro Control Unit (MCU) sends out a switching low power consumption command (ENZ);
(4) The chip enters a second working period, and the second low dropout linear voltage regulator unit (LDOB) enters an ultra-low power consumption mode according to a received low power consumption command (ENZ) and executes circuit processing under the mode.
8. The method for implementing low power switching of dual LDO structure as set forth in claim 7, wherein said step (1) comprises the steps of:
(1.1) the Micro Control Unit (MCU) sets the low power mode signal (standby_enh) to an off state and sets the linear voltage stabilizing signal (ldos15_pdn) to an on state;
(1.2) after processing by said external digital logic unit (logic), said first logic control signal (PDN) outputting a low level signal and said second logic control Signal (STANDBY) outputting a high level signal;
(1.3) said operational Amplifier (AMP) receiving a high level signal output by said second logic control Signal (STANDBY), said first low dropout linear regulator unit (LDOA) starting operation;
the first PMOS field-effect transistor (mp 1) of (1.4) receives the low-level signal output by the first logic control signal (PDN), and the second low dropout linear voltage regulator unit (LDOB) starts to operate.
9. The method for implementing low power switching of dual LDO structure as set forth in claim 8, wherein said step (4) comprises the steps of:
the second low dropout linear regulator unit (LDOB) described in (4.1) receives the low power consumption command (ENZ) sent by the Micro Control Unit (MCU);
(4.2) said Micro Control Unit (MCU) setting said low power command (ENZ) to low level and turning off the heavy load circuit which does not maintain the basic function of the chip, and then entering a delay state;
(4.3) after the delay is finished, the Micro Control Unit (MCU) sets the low power consumption mode signal (STANDBY_ENH) and the linear voltage stabilizing signal (LDO15_PDN) to be in a conducting state;
(4.4) after said external digital logic unit (logic) processing, said first logic control signal (PDN) outputting a low level signal and said second logic control Signal (STANDBY) outputting a low level signal;
after the operational Amplifier (AMP) receives the low level signal output by the second logic control Signal (STANDBY), the first low dropout linear regulator unit (LDOA) turns off the circuit;
the first PMOS field-effect transistor (mp 1) of (4.6) receives the low-level signal output by the first logic control signal (PDN), and the second low dropout linear voltage regulator unit (LDOB) continues to maintain the operating state.
10. The method of claim 7, wherein the driving currents output by the first low dropout linear voltage regulator (LDOA) and the second low dropout linear voltage regulator (LDOB) are of uA level, so as to achieve that the circuit structure meets the requirement of ultra low power consumption.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111569033.4A CN116300546A (en) | 2021-12-21 | 2021-12-21 | Circuit structure for realizing MCU low-power consumption power management and switching method thereof |
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