CN110908493A - Power supply control method and device - Google Patents
Power supply control method and device Download PDFInfo
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- CN110908493A CN110908493A CN201911118830.3A CN201911118830A CN110908493A CN 110908493 A CN110908493 A CN 110908493A CN 201911118830 A CN201911118830 A CN 201911118830A CN 110908493 A CN110908493 A CN 110908493A
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
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Abstract
The invention discloses a power supply control method and a power supply control device, which are used for solving the problem that the conventional low-power-consumption management device still has static power consumption in a sleep mode. In the device, a normally open module is respectively connected with a main control digital logic module, a first power supply module and a switch module, and the switch module is respectively connected with the main control digital logic module and the first power supply module; the normally open module is used for sending a first control signal for disconnecting the connection to the switch module when the master control digital logic module is determined to enter the sleep mode; and the switch module is used for disconnecting the connection between the first power supply module and the main control digital logic module after receiving the first control signal sent by the normally open module. Because the main control digital logic module is completely powered off in the sleep mode, the static power consumption of the main control digital logic module is reduced.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a power supply control method and device.
Background
At present, devices and terminals based on internet applications are rapidly developed and widely applied, and one of the main characteristics of the applications is that batteries are needed to supply power for a long time, and the requirements on power consumption are very sensitive. Therefore, it is important to reduce the system power consumption of chips in devices and terminals.
In order to reduce power consumption, a sleep mode power supply voltage stabilizing circuit connected in parallel with a working mode power supply voltage stabilizing circuit and connected with a main control digital logic module is mainly added in the prior art. In the sleep mode, the working mode power supply voltage stabilizing circuit is turned off, the sleep mode power supply voltage stabilizing circuit supplies power to the main control digital logic module, and in the working mode, the working mode power supply voltage stabilizing circuit supplies power to the main control digital logic module. Because the system power consumption when the power supply voltage stabilizing circuit in the sleep mode supplies power is lower than the power consumption when the power supply voltage stabilizing circuit in the working mode supplies power, the power consumption can be reduced in the sleep mode.
However, in the sleep mode, although the main control digital logic module already performs standby operation at a lower frequency, power supply still exists, and static power consumption at this time cannot be ignored.
Disclosure of Invention
The embodiment of the invention provides a power supply control method and a power supply control device, which are used for solving the problem that the existing low-power-consumption management device still has static power consumption in a sleep mode.
An embodiment of the present invention provides a power supply control apparatus, including:
the system comprises a normally open module, a main control digital logic module, a first power supply module and a switch module;
the normally open module is respectively connected with the main control digital logic module, the first power supply module and the switch module, and the switch module is respectively connected with the main control digital logic module and the first power supply module;
the normally open module is used for sending a first control signal for disconnecting the connection to the switch module when the master control digital logic module is determined to enter the sleep mode;
the first power supply module is used for supplying power to the normally open module and the main control digital logic module;
and the switch module is used for disconnecting the connection between the first power supply module and the main control digital logic module after receiving a first control signal sent by the normally open module.
Further, the main control digital logic module is configured to send a first request signal for entering a sleep mode to the normally open module after completing an initialization task or a digital logic processing task;
and the normally open module is used for determining that the main control digital logic module enters a sleep mode after receiving the first request signal.
Further, the normally open module is further configured to send a second control signal for establishing a connection to the switch module when the master digital logic module is determined to be woken up, and send first notification information for entering a low power consumption working mode to the master digital logic module;
the switch module is further configured to receive a second control signal sent by the normally open module, so that the first power supply module is connected with the main control digital logic module;
and the main control digital logic module also enters a low-power-consumption working mode after receiving the first notification information sent by the normally open module.
Further, the normally open module is further configured to determine to wake up the main control digital logic module when at least one of an external IO wake-up signal, an analog sensing trigger signal, and an internal timing circuit trigger signal is received.
The master control digital logic module is further configured to determine whether to enter a full-function operating mode, send a second request signal for entering the full-function operating mode to the normally open module if the master control digital logic module is in the full-function operating mode, and enter the full-function operating mode after receiving second notification information sent by the normally open module;
the normally open module is further configured to send second notification information for entering a full-function working mode to the main control digital logic module after receiving the second request signal;
the device further comprises: the current output by the second power supply module is larger than the current output by the first power supply module;
the second power supply module is respectively connected with the switch module and the normally open module and is used for supplying power to the main control digital logic module;
the normally open module is further configured to send a third control signal for turning on power supply to the second power supply module after receiving the second request signal; sending second notification information for entering a full-function working mode to the main control digital logic module;
the second power module is further configured to start power supply after receiving the third control signal.
Further, the main control digital logic module is further configured to determine whether the digital logic processing task is completed when it is determined that the full-function operating mode is not entered, and keep the current state unchanged if the digital logic processing task is not completed.
Further, the normally open module is further configured to send a fourth control signal for turning off power supply to the second power module after determining that the main control digital logic module enters a sleep mode or sending first notification information for entering a low power consumption operating mode to the main control digital logic module;
and the second power supply module is also used for cutting off power supply after receiving the fourth control signal.
Further, the apparatus further comprises: the current output by the second power supply module is larger than the current output by the first power supply module;
the second power supply module is respectively connected with the switch module and the normally open module and is used for supplying power to the main control digital logic module;
the normally open module is further used for sending a second control signal for establishing connection to the switch module and sending a third control signal for starting power supply to the second power module when power-on initialization is carried out;
the switch module is further configured to connect the first power supply module and the second power supply module with the main control digital logic module after receiving the second control signal sent by the normally open module;
the second power module is further configured to start power supply after receiving the third control signal.
Correspondingly, the embodiment of the invention also provides a power supply control method, which comprises the following steps:
and when the master control digital logic module is determined to enter the sleep mode, sending a disconnection control signal to the switch module, and controlling the switch module to disconnect the first power supply module from the master control digital logic module.
Further, the determining that the master digital logic module enters the sleep mode includes:
and if a first request signal sent by the main control digital logic module is received, determining that the main control digital logic module enters a sleep mode, wherein the first request signal is sent by the main control digital logic module after an initialization task or a digital logic processing task is completed.
Further, when the main control digital logic module is determined to be awakened, a second control signal for establishing connection is sent to the switch module, so that the first power supply module is connected with the main control digital logic module, and first notification information for entering a low-power-consumption working mode is sent to the main control digital logic module, so that the main control digital logic module enters the low-power-consumption working mode.
Further, after receiving a second request signal, sending a third control signal for turning on power supply to a second power module, wherein the second power module is connected with the switch module; and sending second notification information for entering a full-function working mode to the main control digital logic module, wherein the second request signal is sent when the main control digital logic module judges that the full-function working mode is entered.
Further, after determining that the main control digital logic module enters a sleep mode or sending first notification information for entering a low power consumption mode to the main control digital logic module, sending a fourth control signal for disconnecting power supply to the second power supply module, so that the second power supply module stops supplying power.
The embodiment of the invention provides a power supply control method and a device, wherein a normally open module in the device is respectively connected with a main control digital logic module, a first power supply module and a switch module, and the switch module is respectively connected with the main control digital logic module and the first power supply module; the normally open module is used for sending a first control signal for disconnecting the connection to the switch module when the master control digital logic module is determined to enter the sleep mode; the first power supply module is used for supplying power to the normally open module and the main control digital logic module; and the switch module is used for disconnecting the connection between the first power supply module and the main control digital logic module after receiving the first control signal sent by the normally open module. In the embodiment of the invention, in the sleep mode, the normally open module disconnects the first power supply module from the main control digital logic module through the control switch module, so that the main control digital logic module is completely powered off in the sleep mode, and the static power consumption of the main control digital logic module is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a power control apparatus according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another power control apparatus according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a power management scheme of a chip according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating steps of a power control method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to effectively reduce the static power consumption of the main control digital logic module in the sleep mode, the embodiment of the invention provides a power supply control method and a power supply control device.
Example 1:
fig. 1 is a schematic structural diagram of a power control apparatus according to an embodiment of the present invention, where the apparatus includes: the normally open module 10, the main control digital logic module 40, the first power module 30 and the switch module 20.
The normally open module 10 is respectively connected to the main control digital logic module 40, the first power module 30 and the switch module 20, and the switch module 20 is respectively connected to the main control digital logic module 40 and the first power module 30.
The normally open module 10 is configured to send a first control signal for disconnecting to the switch module 20 when it is determined that the main control digital logic module 40 enters the sleep mode.
The first power module 30 is configured to supply power to the normally open module 10 and the main control digital logic module 40.
The switch module 20 is configured to disconnect the first power module 30 from the main control digital logic module 40 after receiving the first control signal sent by the normally open module 10.
The normally open module 10 is a module for controlling the opening and closing of the switch module 20, and the normally open module 10 includes an input port 101, an output port 104 and an output port 103, where the input port 101 is connected to the first power module 30, the output port 104 is connected to the switch module 20, and the output port 103 is connected to the main control digital logic module 40.
The first power module 30 includes an input port 301 and an output port 302, wherein the input port 301 is used for connecting an external power source, and the first power module 30 processes the voltage and the current of the external power source accordingly, so as to conveniently supply power to the normally open module 10 and the main control digital logic module 40. The output port 302 of the first power module 30 is connected to the input port 101 of the normally-open module 10 and the switch module 20, respectively.
Master digital logic module 40 includes an input port 401, and input port 401 is connected to switch module 20.
When the switch module 20 is closed, the main control digital logic module 40 is connected to the first power module 30 and receives power from the first power module 30.
The normally open module 10 is configured to monitor whether the current main control digital logic module 40 enters the sleep mode, and when it is determined that the main control digital logic module 40 enters the sleep mode, the normally open module 10 does not need to work after the main control digital logic module 40 enters the sleep mode, and at this time, in order to reduce static power consumption, the normally open module 10 sends a first control signal for disconnecting the connection to the switch module 20 through the output port 104.
In the present embodiment, the first power module 30 is a low current power supply module. An external power supply supplies power to the low-current power supply module 30 through the input port 301, and the low-current power supply module 30 supplies power to the normally-open module 10 and the main control digital logic module 40 through the output port 302. Because the main control digital logic module 40 is powered off in the sleep mode, the static power consumption of the main control digital logic module 40 is reduced, and the first power module 30 only supplies power to the normally open module 10 in the sleep mode of the chip, so that the power consumption is extremely low, and the current is usually dozens of to hundreds of nanoamperes.
In the embodiment of the present invention, when the main control digital logic module 40 is in the sleep mode, the normally open module 10 disconnects the first power module 30 from the main control digital logic module 40 through the control switch module 20, so that the main control digital logic module 40 is completely powered off in the sleep mode, thereby reducing the static power consumption of the main control digital logic module 40.
Example 2:
in order to accurately determine whether the main control digital logic module 40 enters the sleep mode, on the basis of the above embodiment, fig. 2 is a schematic structural diagram of another power control apparatus provided in the embodiment of the present invention, in the embodiment of the present invention:
the main control digital logic module 40 is configured to send a first request signal for entering a sleep mode to the normally open module 10 after completing an initialization task or a digital logic processing task.
The normally open module 10 is configured to determine that the main control digital logic module 40 enters a sleep mode after receiving the first request signal.
The main control digital logic module 40 further includes an output port 403 and an input port 402, the normally open module 10 further includes an input port 107 and an output port 105, the output port 403 of the main control digital logic module 40 is connected to the input port 107 of the normally open module 10, and the input port 402 of the main control digital logic module 40 is connected to the output port 105 of the normally open module 10.
The initialization task refers to performing power-on initialization configuration on digital logic and analog circuits in the main control digital logic module 40. Digital logic processing tasks include data processing tasks and logic analysis tasks.
The main control digital logic module 40 may determine whether the initialization task is completed according to its current state, and may also determine whether the data logic processing task is completed according to the current processing progress, and if the initialization task or the data logic processing task is completed, send a first request signal to the normally open module 10. Or the normally open module 10 may also actively acquire the status of the main control digital logic module 40 to determine whether the main control digital logic module 40 has completed the initialization task or the data logic processing task.
After the normally open module 10 receives the first request signal, it is determined that the main control digital logic module 40 can enter the sleep mode, and in order to save power consumption, the normally open module 10 sends a first control signal to control the switch module 20 to be switched off.
The working mode of the main control digital logic module 40 is controlled by the normally open module 10, and when the normally open module 10 determines that the main control digital logic module 40 enters the sleep state, the normally open module 10 sends a notification message of entering the sleep mode to the port 402 of the main control digital logic module 40 through the output port 105, and controls the main control digital logic module 40 to enter the sleep mode.
In the embodiment of the present invention, after receiving the first request signal sent by the main control digital logic module 40, the normally open module 10 determines that the main control digital logic module 40 enters the sleep mode, so as to control the switch module 20, thereby ensuring the accuracy of the control.
Example 3:
after the main control digital logic module 40 enters the sleep mode, if the main control digital logic module 40 needs to execute a digital logic processing task, the main control digital logic module 40 needs to be awakened, and on the basis of the above embodiments, in the embodiment of the present invention:
the normally open module 10 is further configured to send a second control signal for establishing a connection to the switch module 20 when determining to wake up the main control digital logic module 40, and send a first notification message for entering a low power consumption operating mode to the main control digital logic module 40.
The switch module 20 is further configured to receive a second control signal sent by the normally open module 10, so that the first power module 30 is connected to the main control digital logic module 40.
The main control digital logic module 40 is further configured to enter a low power consumption operating mode after receiving the first notification message sent by the normally open module 10.
In the embodiment of the present invention, when the normally open module 10 determines that the main control digital logic module 40 needs to be awakened, the control switch module 20 establishes a connection, after the switch module 20 establishes a connection, the first power module 30 supplies power to the main control digital logic module 40 through the switch module 20, and the normally open module 10 sends the first notification message entering the low power consumption operating mode to the main control digital logic module 40, because it is not known what task needs to be processed after the main control digital logic module 40 is awakened at this time, the main control digital logic module 40 can be temporarily operated in the low power consumption operating mode, that is, only the first power module 30 supplies power to the main control digital logic module 40 at this time. In order to ensure that the main control digital logic module 40 operates in the low power consumption operating mode, units of the main control digital logic module 40 that operate in the low power consumption operating mode may be preconfigured, and only part of the units of the main control digital logic module 40 operate in the low power consumption operating mode, that is, in the low power consumption operating mode, only part of the functions of the main control digital logic module 40 need to be turned on, and what functions are specifically turned on, may be flexibly selected according to the power supply amount of the first power module 30 and the power consumption amount of each function.
In order to facilitate the normally open module 10 to determine whether to wake up the main control digital logic module 40, in the embodiment of the present invention:
the normally open module 10 is further configured to determine to wake up the main control digital logic module 40 when receiving at least one of an external IO wake-up signal, an analog sensing trigger signal, and an internal timing circuit trigger signal.
The normally open module 10 further includes an input port 103 and an input port 106, the input port 103 of the normally open module 10 is configured to receive an external IO wake-up signal, and the input port 106 is configured to receive an analog sensing trigger signal.
The external IO wake-up signal can be any one of a low level signal, a high level signal, a rising edge signal and a falling edge signal; the analog sensing trigger signal is an analog signal converted from any one of non-electric signals such as temperature, pressure, displacement, velocity and the like.
In addition, the normally open module 10 may further include a timer, specifically, when the normally open module 10 determines that the main control digital logic module 40 enters the sleep mode, the timer may be started, and if the normally open module 10 does not receive the reception of the external IO wake-up signal and the analog sensing trigger signal within the timing duration of the timer, the main control digital logic module 40 is determined to be woken up when the timer is timed to end.
When the normally open module 10 determines to wake up the main control digital logic module 40, the normally open module 10 sends a first notification message to the main control digital logic module 40 through the output port 105, and sends a second control signal to the switch module 20 through the output port 104.
The main control digital logic module 40 enters a low power consumption operating mode after receiving the first notification information through the input port 402, the low power consumption operating mode is an operating mode in which a local necessary function of the main control digital logic module 40 operates, the first power supply module 30 is sufficient for providing power drive for the chip, and the power consumption of the chip in the low power consumption operating mode is generally tens to hundreds of microamperes of current.
In the sleep mode, an external IO wake-up signal is input into the normally open module 10 through the input port 103, the normally open module 10 determines that the main control digital logic module 40 needs to be woken up, and the normally open module controls the switch module 20 to be closed through the output port 104, so that the first power module 30 supplies power to the main control digital logic module 40; or the analog sensing trigger signal is input into the normally open module 10 through the input port 106, the normally open module 10 determines that the main control digital logic module 40 needs to be awakened, and the normally open module controls the switch module 20 to be closed through the output port 104, so that the first power module 30 supplies power to the main control digital logic module 40; or after the internal timing circuit or timer of the normally open module 10 is triggered, the normally open module 10 determines that the main control digital logic module 40 needs to be awakened, and the normally open module controls the switch module 20 to be closed through the output port 104, so that the first power module 30 supplies power to the main control digital logic module 40. At this time, the normally open module controls partial functions of the main control digital logic module 40 to be opened through the output port 105, and the main control digital logic module 40 operates in the low power consumption operating mode.
In the embodiment of the present invention, the main control digital logic module 40 firstly enters the low power consumption operating mode after being awakened from the sleep mode, and in the low power consumption operating mode, the main control digital logic module 40 only has local necessary functions to operate, and the operating power consumption is only tens to hundreds of microampere-level current, which further reduces the power consumption of the main control digital logic module 40.
Example 4:
in order to further ensure the requirement of data processing, on the basis of the above embodiments, in the embodiment of the present invention:
the main control digital logic module 40 is further configured to determine whether to enter a full-function operating mode, and if so, send a second request signal for entering the full-function operating mode to the normally open module 10, and enter the full-function operating mode after receiving a second notification message sent by the normally open module 10.
The device further comprises: a second power module 50, wherein the current output by the second power module 50 is larger than the current output by the first power module 30.
The second power module 50 is connected to the switch module 20 and the normally open module 10, respectively, and is configured to supply power to the main control digital logic module 40.
The normally open module 10 is further configured to send a third control signal for turning on power supply to the second power module after receiving the second request signal; and sends a second notification to the master digital logic module 40 to enter a full function mode of operation.
The second power module 50 is further configured to start power supply after receiving the third control signal.
The main control digital logic module 40 can determine whether to enter the full-function operating mode according to the data processing requirement. If the main control digital logic module 40 is in the low power consumption mode according to the requirement of data processing, only the local necessary functions are activated, and it is known which functions the main control digital logic module 40 is activated, and when data processing is performed, the required processing functions can be known for each data processing, so that the main control digital logic module 40 determines whether to enter the full function operating mode according to the requirement of data processing, that is, all the functional units of the main control digital logic module 40 are activated.
The main control digital logic module 40 needs to start all the internal functional units in the full-function operating mode, and if the main control digital logic module 40 is only powered by the first power module 30, all the functional units cannot be started, so that a large-current power supply module is needed for supplying power, and therefore, the power control device of the embodiment of the invention further includes a second power module 50.
The second power module 50 includes an input port 501, an input port 503 and an output port 502, wherein the input port 501 is used for connecting an external power supply; the output port 502 of the second power module 50 is connected to the switch module 20, specifically to the end of the switch module 20 connected to the first power module 30; the normally open module 10 further includes an output port 102, and the second power module 50 is connected to the output port 102 of the normally open module 10 through an input port 503. The normally open module 10 sends a third control signal through the output port 102 to control the second power module 50.
When the main control digital logic module 40 determines to enter the full-function operating mode, the main control digital logic module 40 sends a second request signal for entering the full-function operating mode to the normally open module 10 through the output port 403, and after the normally open module 10 receives the second request signal through the input port 107, it may be determined that the main control digital logic module 40 needs to enter the full-function operating mode.
When the normally open module 10 determines that the main control digital logic module 40 enters the full-function operating mode, the third control signal for turning on power supply is sent to the second power module 50 through the output port 102, and after the second power module 50 receives the third control signal through the input port 503, the second power module 50 connected with an external power supply supplies power to the outside through the output port 502, because the output port 502 of the second power module 50 is connected with the switch module 20, if the switch module 20 is closed, the second power module 50 will supply power to the main control digital logic module 40, and therefore at this time, the switch module 20 needs to be in a closed state, even if the second power module 50 and the first power module 30 are connected with the main control digital logic module 40.
After the normally open module 10 sends the third control signal for turning on the power supply to the second power module 50 through the output port 102, the normally open module 10 sends the second notification information for entering the full-function operating mode to the main control digital logic module 40 through the output port 105, and the main control digital logic module 40 enters the full-function operating mode after receiving the second notification information through the input port 402.
Because the main control digital logic module 40 can determine whether to enter the full-function operating mode according to the requirement of data processing, if the full-function operating mode does not need to be entered, in order to implement corresponding control, in the embodiment of the present invention:
the main control digital logic module 40 is further configured to determine whether the digital logic processing task is completed when it is determined that the full-function operating mode is not entered, and keep the current state unchanged if the digital logic processing task is not completed.
If it is determined that the main control digital logic module 40 does not need to enter the full-function working mode according to the data processing requirement, it is determined whether the current data logic processing task is completed, and the specific main control digital logic module 40 may periodically perform the determination or perform the determination when the task is changed, and if it is determined that the data processing task is not completed, the current low-power-consumption working mode may be maintained unchanged.
Because the full-function operating mode may not be required to be turned on during data processing, and may also be required to be turned on, no matter in which operating mode, after the task of data processing is completed, in order to further reduce power consumption, in the embodiment of the present invention:
the normally open module 10 is further configured to send a fourth control signal for turning off power supply to the second power module 50 after determining that the main control digital logic module 40 enters the sleep mode or sending the first notification information for entering the low power consumption operating mode to the main control digital logic module 40.
The second power module 50 is further configured to disconnect power supply after receiving the fourth control signal.
When the main control digital logic module 40 is in the low power consumption operating mode or the full function operating mode, the main control digital logic module 40 determines whether the current data logic processing task is completed. If the data logic processing task is completed, the main control digital logic module 40 sends a first request signal to the normally open module 10, and the normally open module 10 determines that the main control digital logic module 40 enters the sleep mode. Or the normally open module 10 may also actively acquire the status of the master digital logic module 40 to determine whether the master digital logic module 40 has completed the data logic processing task.
Or when the main control digital logic module 40 is in the full-function operating mode and the main control digital logic module 40 judges that the main control digital logic module 40 does not need to be in the full-function operating mode according to the self state, the main control digital logic module 40 sends a feedback signal for entering the low-power consumption operating mode to the normally open module 10 through the output port 403. After receiving the feedback signal through the input port 107, the normally open module 10 sends the first notification information to the main control digital logic module 40 through the output port 105, and then sends a fourth control signal to the second power module 50 through the output port 103. The second power module 50 receives the fourth control signal through the input port 503 and then cuts off the power supply. The main control digital logic module 40 enters a low power consumption operation mode after receiving the first notification information through the input port 402.
The second power module 50 starts to supply power when the main control digital logic module 40 is in the full-function operating mode or at power-on initialization, so that the power supply needs to be cut off after the main control digital logic module 40 finishes the full-function operating mode or enters the sleep mode at power-on initialization.
Specifically, when the main control digital logic module 40 enters the low power consumption operating mode from the full function operating mode, the normally open module sends a fourth control signal for disconnecting power supply to the second power module, so that it can be ensured that only the first power module 30 supplies power to the main control digital logic module 40 in the low power consumption operating mode.
Example 5:
in order to better supply power to each module in the chip, on the basis of the above embodiments, in an embodiment of the present invention, the apparatus further includes: and a second power module 50, wherein the current output by the second power module 50 is larger than the current output by the first power module.
The second power module 50 is connected to the switch module 20 and the normally open module 10, respectively, and is configured to supply power to the main control digital logic module 40.
The normally open module 10 is further configured to send a second control signal for establishing a connection to the switch module 20 and send a third control signal for turning on power supply to the second power module 50 during power-on initialization.
The switch module 20 is further configured to connect the first power module 30 and the second power module 50 with the main control digital logic module 40 after receiving the second control signal sent by the normally open module 10.
The second power module 50 is further configured to start power supply after receiving the third control signal.
In the power-on initialization process, the first power module 30 supplies power to the normally open module 10 through the output port 302, the normally open module 10 sends a third control signal for turning on the power supply to the second power module 50 through the output port 102, after the second power module 50 receives the third control signal through the input port 503, the second power module 50 connected with an external power supply supplies power to the outside through the output port 502, and then the normally open module 10 controls the switch module 20 to be closed through the output port 104, so that the second power module 50 and the first power module 30 are connected with the main control digital logic module 40, and the first power module 30 and the second power module 50 supply power to the main control digital logic module 40.
After the main control digital logic module 40 is powered on, the digital logic and analog circuits in the main control digital logic module 40 are powered on for initialization configuration. Meanwhile, the main control digital logic module 40 may determine whether the initialization configuration is completed according to its current state, and if the initialization configuration is not completed, continue the initialization configuration.
In the embodiment of the present invention, after the chip is powered on and initialized, the normally open module 10 enables the second power module 50 and the first power module 30 to be connected to the main control digital logic module 40 by turning on the switch module 20 and the second power module 50, so that the first power module 30 and the second power module 50 supply power to the main control digital logic module 40.
Specifically, the power control device is located in the chip.
The power control apparatus according to an embodiment of the present invention will be described below with reference to a block diagram in a chip.
Fig. 3 is a schematic structural diagram of a power management scheme of a chip according to an embodiment of the present invention, and a module frame of the chip includes a normally open digital/analog module 10, a switch module 20, a low-current power supply module 30, a main control digital logic module 40, and a high-current power supply module 50.
The normally open digital/analog module 10 is a control module for controlling various operating modes of the main control digital logic module 40 and the main control power switch. In an embodiment of the present invention, the normally-open digital/analog module 10 is a normally-open module 10.
The large current power supply module 50 and the small current power supply module 30 are power modules for supplying power to the normally open digital/analog module 10 and the main control digital logic module 40, in the embodiment of the present invention, the large current power supply module 50 is the second power supply module 50, and the small current power supply module 30 is the first power supply module 30.
Master digital logic module 40 is an execution module that performs initialization tasks and digital logic processing tasks.
The switch module 20 is a control module, and is configured to control connection and disconnection between the main control digital logic module 40 and the high-current power supply module 50 and the low-current power supply module 30.
Firstly, during the power-on initialization process, the low-current power supply module 30 and the high-current power supply module 50 are sequentially turned on, the normally open digital/analog module 10 sends a power-on control signal to the high-current power supply module 50 through the port 102, and the port 104 controls the switch module 20 to be closed. The chip main control digital logic module 40 completes power-on initialization configuration.
After the initialization is completed, the normally open digital/analog module 10 determines that the main control digital logic module 40 enters the sleep mode, the normally open digital/analog module 10 sends a control signal for disconnecting the power supply to the high-current power supply module 50 through the port 102, and the port 104 controls the switch module 20 to disconnect.
In a sleep mode, an external IO wake-up signal is input into the normally-open digital/analog module 10 through the input port 103, the normally-open digital/analog module 10 determines that the master digital logic module 40 needs to be woken up, and the normally-open digital/analog module 10 controls the switch module 20 to be closed through the output port 104, so that the low-current power supply module 30 supplies power to the master digital logic module 40; or the analog sensing trigger signal is input into the normally open module 10 through the input port 106, the normally open digital/analog module 10 determines that the main control digital logic module 40 needs to be awakened, and the normally open digital/analog module 10 controls the switch module 20 to be closed through the output port 104, so that the low-current power supply module 30 supplies power to the main control digital logic module 40; or after the internal timing circuit of the normally open digital/analog module 10 is triggered, the normally open digital/analog module 10 determines that the main control digital logic module 40 needs to be awakened, and the normally open digital/analog module 10 controls the switch module 20 to be closed through the output port 104, so that the low-current power supply module 30 supplies power to the main control digital logic module 40. At this time, the normally open digital/analog module 10 sends a notification message of entering the low power consumption operation mode to the main control digital logic module 40 through the output port 105, and the main control digital logic module 40 operates in the low power consumption operation mode.
In the low power consumption operating mode, the main control digital logic module 40 determines whether to enter the full-function operating mode according to the data logic processing result and the logic analysis requirement during the operation process. When master digital logic module 40 determines to enter the full-function operating mode, port 403 sends a request signal for entering the full-function operating mode to normally-open digital/analog module 10.
When the main control digital logic module 40 determines that the full-function working mode is not entered, it determines whether the digital logic processing task is completed, and if the digital logic processing task is not completed, the current state is kept unchanged.
After receiving the request signal for entering the full-function operating mode, the normally open digital/analog module 10 sends a second notification message for entering the full-function operating mode to the main control digital logic module 40, and the normally open digital/analog module 10 sends a control signal for turning on power supply to the high-current power supply module 50 through the port 102. After the power-on is completed, the high-current power supply module 50 provides a high-driving power supply voltage from the port 502 to the main control digital logic module 40. At this time, the chip will operate in a full-function operating mode.
If the main control digital logic module 40 has completed the required digital logic processing task or initialization task, the normally open digital/analog module 10 controls the main control digital logic module 40 to close again and enable through the output port 105, and after the power supply mounting capability is released, the port 104 of the normally open digital/analog module 10 controls the switch module 20 to be disconnected, and the chip returns to the sleep mode.
Example 6:
in order to effectively reduce static power consumption of a main control digital logic module in a sleep mode, an embodiment of the present invention provides a power control method, where the method includes:
when determining that the main control digital logic module 40 enters the sleep mode, sending a disconnection control signal to the switch module 20, and controlling the switch module 20 to disconnect the connection between the first power supply module 30 and the main control digital logic module 40.
The determining that the master digital logic module 40 enters the sleep mode includes:
if a first request signal sent by the main control digital logic module 40 is received, it is determined that the main control digital logic module 40 enters a sleep mode, where the first request signal is sent after the main control digital logic module 40 completes an initialization task or a digital logic processing task.
In an embodiment of the present invention, the power control method further includes: when the main control digital logic module 40 is determined to be woken up, a second control signal for establishing connection is sent to the switch module 20, so that the first power module 30 is connected with the main control digital logic module 40, and first notification information for entering a low power consumption working mode is sent to the main control digital logic module 40, so that the main control digital logic module 40 enters the low power consumption working mode.
In an embodiment of the present invention, the power control method further includes: after receiving the second request signal, sending a third control signal for turning on power supply to the second power module 50, wherein the second power module 50 is connected to the switch module 20; and sending a second notification message of entering a full-function operating mode to the main control digital logic module 40, where the second request signal is sent when the main control digital logic module 40 determines to enter the full-function operating mode.
In an embodiment of the present invention, the power control method further includes: master digital logic module 40 sends a first request signal to normally open module 10 through output port 403. After determining that the main control digital logic module 40 enters the sleep mode or sending the first notification information of entering the low power consumption mode to the main control digital logic module 40, sending a fourth control signal for disconnecting power supply to the second power supply module 50, so that the second power supply module 50 stops supplying power.
The power control method in the embodiment of the present invention is applied to the normally-open module 10.
In the embodiment of the present invention, when the main control digital logic module 40 is in the sleep mode, the normally open module 10 disconnects the first power module 30 from the main control digital logic module 40 through the control switch module 20, so that the main control digital logic module is completely powered off in the sleep mode 40, thereby reducing the static power consumption of the main control digital logic module 40.
An embodiment of the present invention provides a power supply control method, and specifically, fig. 4 is a flowchart illustrating steps of the power supply control method provided in the embodiment of the present invention, where the method includes the following steps:
s401: and (5) power-on initialization.
S402: the low current power supply module 30 is powered on.
S403: the normally open digital/analog module 10 sends a control signal for starting power supply to the high-current power supply module 50 through the port 102, and the high-current power supply module 50 is powered on and started.
S404: the operating mode is initialized.
All digital logic and analog circuits of the chip complete power-on initialization configuration. The normally-open digital/analog module 10 sends a control signal for starting power supply to the high-current power supply module 50 through the port 102, and the port 104 controls the switch module 20 to be switched off.
S405: whether chip initialization is complete. If yes, the process proceeds to S406, otherwise, the process still proceeds to S404.
S406: the shutdown master digital logic module 40 is enabled.
S407: the master digital logic module 40 is powered down.
Normally open digital/analog module 10 is controlled by port 104 to open switch module 20.
S408: the high current power supply module 50 is powered on and off.
The normally-on digital/analog module 10 sends a control signal to turn off the power supply to the high current power supply module 50 through the port 102.
S409: chip sleep mode.
And in the chip sleep mode, only the normally-on digital/analog module 10 works and the low-current power supply module 30 works. The chip operates in sleep mode with very low power consumption, typically on the order of tens to hundreds of nanoamps.
S410: in the sleep mode, an external IO wake-up signal enters the normally open digital/analog module 10 from the port 103; or after the analog sensing trigger signal is input into the normally open module 10 through the input port 106; or the internal timing circuit of the normally-on digital/analog module 10 is triggered, and the process proceeds to S411.
S411: the main control digital logic module 40 is powered on.
Normally open digital/analog module 10 controls switch module 20 to close by port 104.
S412: the master digital logic module 40 is turned on.
S413: and (4) a low-power consumption working mode of the chip.
At this time, the normally open digital/analog module 10 sends notification information of entering a low power consumption operating mode to the main control digital logic module 40, the chip operates in the low power consumption operating mode, local necessary functions of the main control digital logic module 40 operate, and the chip operating power consumption is generally tens to hundreds of microamperes of current.
In the low power consumption mode, the power consumption of the chip is still very low, the small current power supply module 30 is enough to provide the power driving capability of the chip, and the port 102 of the normally open digital/analog module 10 controls the large current power supply module 50 to be closed.
S414: whether to start the full-function working mode. If so, the process proceeds to S416, and if not, the process proceeds to S415.
When master digital logic module 40 determines to enter the full-function operating mode, port 403 sends a request signal for entering the full-function operating mode to normally-open digital/analog module 10.
When the main control digital logic module 40 determines that the full-function working mode is not entered, it determines whether the digital logic processing task is completed, and if the digital logic processing task is not completed, the current state is kept unchanged.
S415: whether the digital logic task is processed is complete. If so, the process proceeds to S409, and if not, the process proceeds to S413.
S416: the high current power supply module 50 is powered on.
The normally open digital logic module 40 first controls the high current power supply module 50 to start operation through the port 102.
S417: and (4) a full-function working mode of the chip.
After the power is turned on, the high-current power supply module 50 supplies a high-driving power supply voltage from the port 502 to the chip core. Then, the normally-open digital/analog module 10 controls the master digital logic module 40 to fully operate from the output port 105, and at this time, the chip will operate in a fully-functional operating mode.
S418: whether the digital logic task is processed is complete. If so, the process proceeds to S406, and if not, the process proceeds to S417.
In summary, in the power control method and the power control device provided in the embodiments of the present invention, in the sleep mode, the normally open module disconnects the first power module from the main control digital logic module through the control switch module, so that the main control digital logic module is completely powered off in the sleep mode, thereby reducing the static power consumption of the main control digital logic module.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A power supply control device, comprising: the system comprises a normally open module, a main control digital logic module, a first power supply module and a switch module;
the normally open module is respectively connected with the main control digital logic module, the first power supply module and the switch module, and the switch module is respectively connected with the main control digital logic module and the first power supply module;
the normally open module is used for sending a first control signal for disconnecting the connection to the switch module when the master control digital logic module is determined to enter the sleep mode;
the first power supply module is used for supplying power to the normally open module and the main control digital logic module;
and the switch module is used for disconnecting the connection between the first power supply module and the main control digital logic module after receiving a first control signal sent by the normally open module.
2. The power control device according to claim 1, wherein the main control digital logic module is configured to send a first request signal for entering a sleep mode to the normally open module after an initialization task or a digital logic processing task is completed;
and the normally open module is used for determining that the main control digital logic module enters a sleep mode after receiving the first request signal.
3. The power control device according to claim 1 or 2, wherein the normally open module is further configured to send a second control signal for establishing a connection to the switch module when determining to wake up the main control digital logic module, and send first notification information for entering a low power consumption operating mode to the main control digital logic module;
the switch module is further configured to connect the first power module with the main control digital logic module after receiving the second control signal sent by the normally open module;
and the master control digital logic module is also used for entering a low-power-consumption working mode after receiving the first notification information sent by the normally open module.
4. The power control device of claim 3, wherein the normally open module is further configured to determine to wake up the main control digital logic module when at least one of an external IO wake-up signal, an analog sensing trigger signal, and an internal timing circuit trigger signal is received.
5. The power control device according to claim 4, wherein the main control digital logic module is further configured to determine whether to enter a full-function operating mode, and if so, send a second request signal for entering the full-function operating mode to the normally open module, and enter the full-function operating mode after receiving a second notification message sent by the normally open module;
the device further comprises: the current output by the second power supply module is larger than the current output by the first power supply module;
the second power supply module is respectively connected with the switch module and the normally open module and is used for supplying power to the main control digital logic module;
the normally open module is further configured to send a third control signal for turning on power supply to the second power supply module after receiving the second request signal; sending second notification information for entering a full-function working mode to the main control digital logic module;
the second power module is further configured to start power supply after receiving the third control signal.
6. The power control device of claim 5, wherein the main control digital logic module is further configured to determine whether the digital logic processing task is completed when it is determined that the full-function operating mode is not entered, and keep the current state unchanged if the digital logic processing task is not completed.
7. The power control device according to claim 5 or 6, wherein the normally open module is further configured to send a fourth control signal for turning off power supply to the second power module after determining that the main control digital logic module enters the sleep mode or sending the first notification information for entering the low power consumption operation mode to the main control digital logic module;
and the second power supply module is also used for cutting off power supply after receiving the fourth control signal.
8. The power control device of claim 1, further comprising: the current output by the second power supply module is larger than the current output by the first power supply module;
the second power supply module is respectively connected with the switch module and the normally open module and is used for supplying power to the main control digital logic module;
the normally open module is further used for sending a second control signal for establishing connection to the switch module and sending a third control signal for starting power supply to the second power module when power-on initialization is carried out;
the switch module is further configured to connect the first power supply module and the second power supply module with the main control digital logic module after receiving the second control signal sent by the normally open module;
the second power module is further configured to start power supply after receiving the third control signal.
9. A method for controlling a power supply, the method comprising:
when the master control digital logic module is determined to enter the sleep mode, a first control signal for disconnecting the connection is sent to the switch module, and the switch module is controlled to disconnect the connection between the first power supply module and the master control digital logic module.
10. The power control method of claim 9, wherein determining that the master digital logic module enters the sleep mode comprises:
and if a first request signal sent by the main control digital logic module is received, determining that the main control digital logic module enters a sleep mode, wherein the first request signal is sent after the main control digital logic module completes an initialization task or a digital logic processing task.
11. The power supply control method according to claim 9 or 10, characterized by further comprising:
and when the main control digital logic module is confirmed to be awakened, sending a second control signal for establishing connection to the switch module, enabling the first power supply module to be connected with the main control digital logic module, and sending first notification information for entering a low-power-consumption working mode to the main control digital logic module, so that the main control digital logic module enters the low-power-consumption working mode.
12. The power control method of claim 11, further comprising:
after receiving a second request signal, sending a third control signal for starting power supply to a second power supply module, wherein the second power supply module is connected with the switch module; and sending second notification information for entering a full-function working mode to the main control digital logic module, wherein the second request signal is sent when the main control digital logic module judges that the full-function working mode is entered.
13. The power control method of claim 12, further comprising:
and after determining that the main control digital logic module enters a sleep mode or sending first notification information for entering a low power consumption mode to the main control digital logic module, sending a fourth control signal for disconnecting power supply to the second power supply module, so that the second power supply module stops supplying power.
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