WO2018000517A1

WO2018000517A1 - Power management circuit

Info

Publication number: WO2018000517A1
Application number: PCT/CN2016/093262
Authority: WO
Inventors: 郝虹宇
Original assignee: 上海晶曦微电子科技有限公司
Priority date: 2016-06-28
Filing date: 2016-08-04
Publication date: 2018-01-04
Also published as: CN105958799B; CN105958799A

Abstract

A power management circuit, comprising a master control digital logic module (10), an operating mode power voltage regulator circuit (20), and a sleep mode power voltage regulator circuit (30). An operating power output end (202) of the operating mode power voltage regulator circuit (20) and a sleep power output end (302) of the sleep mode power voltage regulator circuit (30) are both connected to a master control power input end (101) of the master control digital logic module (10). A signal output end (102) of the master control digital logic module (10) is connected to a control end (203) of the operating mode power voltage regulator circuit (20). In a sleep mode, the operating mode power voltage regulator circuit (20) of the master control digital logic module (10) is disconnected so that the sleep mode power voltage regulator circuit (30) supplies operating voltage to the master control digital logic module (10) in the sleep mode.

Description

Power management circuit

Technical field

Embodiments of the present application relate to the field of electronic technologies, for example, to a power management circuit.

Background technique

In recent years, electronic devices powered by batteries, such as handheld mobile devices, toys and IoT sensors, have been widely developed and popularized. How to reduce the power consumption of the system and extend the service life of the battery has become a key requirement for system design in this respect.

Not all modules or circuits in an electronic device system are always in operation, some modules only need to work under a specific time or condition, and other times can be in a sleep state. Based on the consideration of reducing system power consumption, when the system or some modules are in a sleep state, the power circuit can be turned off, and when the system or module needs to be woken up, the power supply circuit is turned on. Referring to Figure 1, the power management circuitry can include a master digital logic module for controlling and managing the operational status of the overall system. In terms of power management, an external power supply voltage can be converted to an internal operating power supply voltage through one or more voltage stabilizing circuits to supply power supply voltages to different circuit modules.

In the above system, when the system is in operation, each module is powered by a voltage stabilizing circuit to provide normal operating state power consumption. When the system is in the sleep state, most of the modules and the regulated power supply circuit of the module can be turned off to reduce power consumption. However, the master digital logic module also requires a supply voltage that allows the master digital logic block to maintain the lowest power operating state, such as holding registers and memory values, maintaining a low speed clock generator that can receive external wake-up signals to disengage Sleep mode, as well as issuing a start signal to start other circuit modules and so on. Therefore, the regulated power supply circuit of the master digital circuit must remain open in the sleep mode. Since the regulated power supply circuit needs to meet the voltage and power consumption requirements of the main control digital logic module under working conditions, the power consumption of the stabilized power supply circuit itself cannot be made very small, so that the system is difficult to maintain ultra low in the sleep state. Power consumption.

Summary of the invention

The embodiment of the present application provides a power management circuit to reduce power consumption in a sleep mode to achieve super Low power requirements.

The embodiment of the present application provides a power management circuit, including a main control digital logic module, a working mode power supply voltage stabilization circuit, and a sleep mode power supply voltage stabilization circuit;

Wherein, the working power output end of the working mode power supply voltage stabilizing circuit and the sleep power output end of the sleep mode power supply voltage stabilizing circuit are both connected to the main control power input end of the main control digital logic module;

a signal output end of the main control digital logic module is connected to a control end of the working mode power supply voltage stabilizing circuit;

In the sleep mode, the master digital logic module controls the operating mode power regulator circuit to be turned off to provide an operating voltage to the master digital logic module through the sleep mode power regulator circuit during the sleep mode.

The technical solution provided by the embodiment of the present application is to increase a sleep mode power supply voltage stabilization circuit connected in parallel with the working mode power supply voltage stabilization circuit and connected to the main control digital logic module. In the sleep mode, the master numerical logic module controls the operating mode power supply voltage regulator circuit to be turned off to provide a working voltage to the digital logic module through the sleep mode power supply voltage regulator circuit in the sleep mode. Since the sleep mode power supply voltage regulator circuit only needs to supply power to the main control digital logic module in the sleep mode, and the working mode power supply voltage stabilization circuit needs to supply power to the main control digital logic module in the working mode, the sleep mode power supply voltage stabilization circuit The power consumption is lower than the power consumption of the operating mode power supply regulator circuit, so that the power consumption can be reduced in the sleep mode, achieving ultra-low power consumption requirements.

DRAWINGS

1 is a schematic structural diagram of a power management circuit provided by a related art;

2 is a schematic structural diagram of a power management circuit provided in an embodiment of the present application;

3 is a schematic structural diagram 1 of a sleep mode power supply voltage stabilization circuit provided in an embodiment of the present application;

4 is a schematic structural diagram 2 of a sleep mode power supply voltage stabilization circuit provided in an embodiment of the present application;

FIG. 5 is a schematic structural diagram 3 of a sleep mode power supply voltage stabilization circuit provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram 4 of a sleep mode power supply voltage stabilization circuit provided in an embodiment of the present application.

detailed description

The present application will be further described in detail below with reference to the accompanying drawings and embodiments. The embodiments described herein are merely illustrative of the present application and are not intended to be limiting. In addition, it should be noted that, for the convenience of description, only some but not all of the structures related to the present application are shown in the drawings.

2 is a schematic structural diagram of a power management circuit according to an embodiment of the present application. As shown in FIG. 2, the power management circuit includes a main control digital logic module 10, a working mode power supply voltage stabilization circuit 20, and a sleep mode power supply voltage regulator. Circuit 30;

The working power output terminal 202 of the working mode power voltage stabilizing circuit 20 and the sleep power output terminal 302 of the sleep mode power voltage stabilizing circuit 30 are both connected to the main power input terminal 101 of the main control digital logic module 10;

The signal output end 102 of the main control digital logic module 10 is connected to the control end 203 of the working mode power supply voltage stabilizing circuit 20;

In the sleep mode, the master digital logic module 10 controls the operating mode power regulator circuit 20 to be turned off to provide the operating voltage to the master digital logic module 10 through the sleep mode power regulator circuit 30 during the sleep mode.

The working mode power supply voltage stabilizing circuit 20 is configured to supply power to the main control digital logic module 10 in the operating mode, so that the main control digital logic module 10 can control and manage the working state of the system. Since the operating mode power supply voltage stabilizing circuit 20 needs to meet the voltage and power consumption requirements of the main control digital logic module 10 in the operating state, the power consumption of the operating mode power supply voltage stabilizing circuit 20 is large. The sleep mode power regulator circuit 30 is configured to power the master digital logic module 10 in the sleep mode to maintain the master digital logic module 10 in a lower power mode of operation: if only the values in the registers and memories are maintained, The low-speed clock generator receives an external wake-up signal to leave the sleep mode, and sends a start signal to other circuit modules.

In summary, since the power consumption of the master digital logic module 10 in the sleep mode is much lower than the power consumption in the active mode, the power consumption of the sleep mode power regulator circuit 30 is lower than that of the power mode regulator circuit 20 of the operation mode. Consumption.

The technical solution provided by this embodiment is to increase a sleep mode power supply voltage stabilization circuit connected in parallel with the working mode power supply voltage stabilization circuit and connected to the main control digital logic module. In the sleep mode, the master numerical logic module controls the operating mode power supply voltage regulator circuit to be turned off to provide the operating voltage to the digital logic module through the sleep mode power supply voltage regulator circuit in the sleep mode. Since the sleep mode power supply regulator circuit only needs to be The main control digital logic module in the sleep mode is powered, and the working mode power supply voltage regulator circuit needs to supply power to the main control digital logic module in the working mode, so the power consumption of the sleep mode power supply voltage stabilization circuit is lower than the working mode power supply voltage regulation. The power consumption of the circuit, which can reduce power consumption in sleep mode, meets the requirements of ultra-low power consumption.

In the working mode, since the set output voltage of the working mode power supply voltage regulator circuit is higher than the set output voltage of the sleep mode power supply voltage stabilizing circuit, the output end of the sleep mode power supply voltage stabilizing circuit is automatically turned off, and does not affect the working mode power supply. The output voltage of the voltage regulator circuit.

The sleep mode power supply voltage regulator circuit structure provided by this embodiment can realize the ultra-low power voltage regulation function through a special negative feedback structure with a self-bias function.

The technical solutions in the embodiments of the present application are described in detail, clearly, and completely in the following description of the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, but not all embodiments. . Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without the creative work are within the scope of the present application.

On the basis of the above embodiment, referring to FIG. 2, the signal input end 103 of the main control digital logic module 10 is configured to receive a sleep signal or a wake-up signal to control the working state of the system according to the received sleep signal or wake-up signal, such as control. Working mode power supply voltage regulator circuit 20 or other power supply voltage regulator circuit operating state. Moreover, the power input terminal 201 of the operation mode power supply voltage stabilization circuit 20 and the power supply input terminal 301 of the sleep mode power supply voltage stabilization circuit 30 are both connected to an external power supply.

FIG. 3 is a schematic structural diagram of a sleep mode power supply voltage stabilization circuit provided in an embodiment of the present application. Referring to FIG. 3, the sleep mode power supply voltage stabilization circuit 30 may include a sleep power supply input terminal Vin, a negative feedback circuit 31, a current limiting resistor R2, a source follower 32, and a sleep power output terminal Vout;

The power supply terminal 311 of the negative feedback circuit 31 is connected to the sleep power supply input terminal Vin, the output terminal 312 of the negative feedback circuit 31 is connected to the input terminal 323 of the source follower 32, the input terminal 313 of the negative feedback circuit 31 and the sleep power supply output terminal Vout. The ground terminal 314 of the connection and the negative feedback circuit 31 is connected to the ground;

The power terminal 321 of the source follower 32 is connected to the sleep power input terminal Vin through the current limiting resistor R2, and the output terminal 322 of the source follower 32 is connected to the sleep power output terminal Vout.

Referring to FIG. 3, after the input terminal 313 of the negative feedback circuit 31 receives the output voltage of the sleep mode power supply voltage regulator from the sleep power supply output terminal Vout, the output terminal 312 of the negative feedback circuit 31 is inverted due to the inverting amplification of the negative feedback circuit 31. The voltage of the input terminal 313 is reversed, so that the voltage of the sleep power supply terminal Vout is maintained. stable.

Based on the above embodiments, the negative feedback circuit can be realized by a load resistor, an N-type field effect transistor, and a P-type field effect transistor. Referring to FIG. 4, the negative feedback circuit 31 may include a load resistor R1, a first N-type field effect transistor MN2, and a first P-type field effect transistor MP1;

The first end of the load resistor R1 serves as the power terminal 311 of the negative feedback circuit 31, and the second end of the load resistor R1 is connected to the drain of the first N-type field effect transistor MN2 as the output terminal 312 of the negative feedback circuit 31, the first N The gate of the FET MN2 serves as the input terminal 313 of the negative feedback circuit 31. The source of the first N-type FET MN2 is connected to the source of the first P-type field effect transistor MP1, and the first P-type field effect The drain and gate of the transistor MP1 are connected as the ground terminal 314 of the negative feedback circuit 31.

Referring to FIG. 4, due to the special structure of the negative feedback circuit, the output voltage Vout of the sleep mode power supply regulator circuit can be substantially maintained at a threshold voltage of an N-type FET plus a threshold voltage of a P-type FET. Plus enough overdrive voltage.

Referring to FIG. 5, the source follower 32 may be a second N-type field effect transistor MN1, and the gate, drain and source of the second N-type field effect transistor MN1 are respectively used as the input 323 of the source follower 32, and the power source. End 321 and output 322.

Referring to FIG. 5, in order to allow a lower external power supply, for example, the second N-type field effect transistor MN1 may be a depletion type (Native) field effect transistor. Optionally, since the gate voltage (input voltage) of the second N-type FET MN1 needs to be higher than the source voltage (output voltage) by a threshold voltage, the threshold voltage of the depletion field effect transistor is close to 0. Therefore, the gate voltage of the second N-type field effect transistor MN1 can be close to or lower than the source voltage, so that the voltage of the external power source can be effectively reduced.

Referring to FIG. 5, for example, the resistance of the load resistor R1 may be in the order of mega ohms. Optionally, since the load resistor R1 is used to set the operating current of the sleep mode power supply voltage regulator, the resistance of the load resistor R1 may be megaohms in order to make the power consumption of the sleep mode power supply voltage regulator sub-microampere. Optionally, in order to reduce the area of the sleep mode power regulator circuit on the chip, the load resistor R1 may be a polysilicon resistor or a preset value of a series connected gate-grounded narrow-length channel P-type field effect transistor. It should be noted that, in this embodiment, the preset value is not limited, and only the resistance of the load resistor R1 can reach the mega ohm level.

Referring to FIG. 5, for example, the resistance of the current limiting resistor R2 may be in the order of kilo ohms. If the sleep power output terminal Vout is short-circuited to the ground, the current limiting resistor R2 can limit the first N-type FET MN2 and the output current to prevent circuit damage caused by excessive short-circuit current.

Moreover, the output of the sleep mode power supply voltage regulator circuit is connected to the output of the operation mode power supply voltage stabilization circuit. In the operating mode, the output of the operating mode power supply voltage regulator circuit is higher than the intrinsic output voltage of the sleep mode power supply voltage regulator circuit, that is, the source of the second N-type FET or the gate of the first N-type FET The voltage is pulled high. Due to the negative feedback of the first N-type FET, the gate voltage of the second N-type FET is pulled low, so that the two N-type FET is not turned on, so in the operating mode, The sleep mode power supply voltage regulator circuit does not affect the operation of the power supply voltage regulator circuit.

Referring to FIG. 6, for example, the sleep mode regulator circuit may include a compensation capacitor C1, the first end of the compensation capacitor C1 is connected to the output terminal 312 of the negative feedback circuit 31, and the second terminal is grounded. Since the sleep mode regulator circuit is a negative feedback structure, the capacitor C1 needs to be compensated to make the open loop phase margin of the loop large enough to allow the sleep mode regulator circuit to maintain a stable state.

Referring to FIG. 6, for example, the sleep mode regulator circuit may include a third N-type FET MN3; the drain of the third N-type FET MN3 is connected to the sleep power output terminal Vout, and the third N-type field effect transistor The gate and source of MN3 are both grounded. Since the gate of the third N-type FET MN3 is grounded, it is always in a non-conducting state, and only the leakage current of the nano-ampere or pico-ampere level enables the sleep power supply output terminal Vout to maintain the voltage without load. Too high.

The technical solution provided by the embodiment of the present application can be used in a radio frequency wireless transceiver system with a 0.18 um FET process, the external input voltage tolerance change index is 1.9V to 3.6V, and the core circuit operating voltage is 1.8V. In sleep mode, the output of the sleep mode regulated power supply circuit ranges from 1.3V to 1.6V, and the current is less than 1uA in the overall system sleep mode.

The technical solution provided by the embodiment of the present application can provide a stable power supply voltage for the main control digital logic control module under ultra low power consumption, and allows the system to allow a large external input power supply voltage variation range, thereby effectively extending battery usage. Lifetime while giving system applications greater flexibility.

Note that the above is only an alternative embodiment of the present application. A person skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various changes, modifications and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, although the present application has been described in detail by the above embodiments, the present application is not limited to the above embodiments.

Claims

A power management circuit includes a main control digital logic module, a working mode power supply voltage stabilization circuit, and a sleep mode power supply voltage stabilization circuit;

The working power output end of the working mode power supply voltage stabilizing circuit and the sleep power output end of the sleep mode power supply voltage stabilizing circuit are both connected to the main control power input end of the main control digital logic module;

a signal output end of the main control digital logic module is connected to a control end of the working mode power supply voltage stabilizing circuit;

In the sleep mode, the master digital logic module controls the operating mode power regulator circuit to be turned off to provide an operating voltage to the master digital logic module through the sleep mode power regulator circuit during the sleep mode.
The circuit of claim 1 wherein the signal input of the master digital logic module is for receiving a sleep signal or a wake-up signal.
The circuit of claim 1 , wherein the sleep mode voltage stabilizing circuit comprises a sleep power input terminal, a negative feedback circuit, a current limiting resistor, a source follower, and a sleep power output;

a power supply end of the negative feedback circuit is connected to the sleep power input end, an output end of the negative feedback circuit is connected to an input end of the source follower, an input end of the negative feedback circuit is connected to the sleep power output end, and The ground of the negative feedback circuit is connected to the ground; and,

The power supply end of the source follower is connected to the sleep power input through the current limiting resistor, and the output of the source follower is connected to the sleep power output.
The circuit according to claim 3, wherein

The negative feedback circuit includes a load resistor, a first N-type field effect transistor, and a first P-type field effect transistor;

a first end of the load resistor is used as a power end of the negative feedback circuit, and a second end of the load resistor is connected to a drain of the first N-type field effect transistor as an output end of the negative feedback circuit. a gate of the first N-type field effect transistor is used as an input end of the negative feedback circuit, a source of the first N-type field effect transistor is connected to a source of the first P-type field effect transistor, and The drain and gate of the first P-type field effect transistor are connected as the ground of the negative feedback circuit.
The circuit according to claim 4, wherein

The source follower is a second N-type field effect transistor, and the gate, the drain and the source of the second N-type field effect transistor are respectively used as an input terminal, a power terminal and an output of the source follower end.
The circuit of claim 5 wherein said second N-type field effect transistor is a depletion mode field effect transistor.
The circuit according to claim 5, wherein the resistance of said load resistor is in the order of mega ohms, and the resistance of said current limiting resistor is in the order of kilo ohms.
The circuit of claim 4 wherein said sleep mode regulator circuit further comprises a compensation capacitor, said first end of said compensation capacitor being coupled to the output of said negative feedback circuit and the second terminal being coupled to ground.
The circuit of claim 4 wherein said sleep mode regulator circuit further comprises a third N-type field effect transistor;

The drain of the third N-type field effect transistor is connected to the output of the sleep power supply, and the gate and the source of the third N-type field effect transistor are both grounded.
The circuit of claim 4 wherein said load resistance is a polysilicon resistor.
The circuit of claim 4 wherein said load resistance is a narrow long channel P-type field effect transistor having at least one gate-grounded in series.