CN105958799A - Power management circuit - Google Patents
Power management circuit Download PDFInfo
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- CN105958799A CN105958799A CN201610487946.4A CN201610487946A CN105958799A CN 105958799 A CN105958799 A CN 105958799A CN 201610487946 A CN201610487946 A CN 201610487946A CN 105958799 A CN105958799 A CN 105958799A
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- circuit
- power supply
- field effect
- effect transistor
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Power Sources (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The embodiment of the invention discloses a power management circuit, comprising a main control digital logic module, a working mode power supply voltage stabilizing circuit and a sleep mode power supply voltage stabilizing circuit, wherein a working power supply output end of the working mode power supply voltage stabilizing circuit and a sleep power supply output end of the sleep mode power supply voltage stabilizing circuit are connected with a main control power supply input end of the main control digital logic module; a signal output end of the main control digital logic module is connected with a control end of the working mode power supply voltage stabilizing circuit; and in a sleep mode, the main control digital logic module controls the working mode power supply voltage stabilizing circuit to close, so as to provide a working voltage for the main control digital logic module through the sleep mode power supply voltage stabilizing circuit in the sleep mode. In the power management circuit, the power consumption of the sleep mode power supply voltage stabilizing circuit is lower than that of the working mode power supply voltage stabilizing circuit, so that the power consumption is reduced in the sleep mode, and the requirements of ultralow power consumption are satisfied.
Description
Technical field
The present embodiments relate to electronic technology field, particularly relate to a kind of electric power management circuit.
Background technology
In recent years, by the electronic equipment of cell powers, such as hand-hold mobile device, toy and Internet of Things
The application such as sensor is widely developed and popularizes, and how to reduce the power consumption of system, extends the use of battery
In the life-span, also become the key request that this respect system designs.
In the system of electronic equipment, not every module or circuit are all constantly in duty, part or institute
Have module have only to the specific time or under the conditions of work, other times may be at resting state.Based on
Reduce the consideration of system power dissipation, when system or certain module are in resting state, its power circuit can be closed
Close, when needs wake up system or module up, then open its power supply circuits.With reference to Fig. 1, electric power management circuit can
To include master control digital logic module, for controlling and manage the duty of whole system.At power management
Aspect, can be converted into the working power of inside by one or more mu balanced circuits by outside supply voltage
Voltage, provides supply voltage to different circuit modules.
In said system, when system is in running order, modules is powered by mu balanced circuit, it is provided that
Normal duty power consumption.When system in a dormant state time, in system major part module and voltage stabilizing electricity
Source circuit may be in closed mode, to reduce power consumption.But, master control digital logic module also needs to one
Individual supply voltage so that it is be able to maintain that lowest power consumption duty, such as the value in holding register and memorizer,
Maintain a low-speed clock generator, and be able to receive that external wake signal, depart from park mode, send
Enabling signal starts other circuit modules etc..Therefore, the voltage-stabilized power supply circuit of master control digital circuit is in dormancy
Must state be held open under pattern.Owing to this voltage-stabilized power supply circuit needs to meet master control Digital Logic
Module in working order under voltage and power consumption requirements, the power consumption of himself can not be made very small, thus
Being extremely difficult in the dormant state, system maintains the requirement of super low-power consumption.
Summary of the invention
The embodiment of the present invention provides a kind of electric power management circuit, to reduce power consumption in the hibernation mode to reach super
The requirement of low-power consumption.
Embodiments provide a kind of electric power management circuit, including master control digital logic module, Working mould
Formula power supply stabilization circuit and park mode power supply stabilization circuit；
The working power outfan of described mode of operation power supply stabilization circuit and described park mode power supply voltage stabilizing electricity
The dormancy power output end on road all master control power inputs with described master control digital logic module are connected；
The signal output part of described master control digital logic module and the control of described mode of operation power supply stabilization circuit
End connects；
When park mode, described master control digital logic module controls described mode of operation power supply stabilization circuit and closes
Close, being described master control digital logic module when park mode by described park mode power supply stabilization circuit
Running voltage is provided.
The technical scheme that the embodiment of the present invention provides, in parallel with mode of operation power supply stabilization circuit by increasing,
And the park mode power supply stabilization circuit being connected with master control digital logic module.In the hibernation mode, master control number
Value logic module control mode of operation power supply stabilization circuit close, with when park mode by described dormancy mould
Formula power supply stabilization circuit provides running voltage for master control digital logic module.Due to park mode power supply voltage stabilizing electricity
Road is only required to be the master control digital logic module being under park mode and powers, and mode of operation power supply stabilization circuit
It is required to be the master control digital logic module being under mode of operation to power, thus park mode power supply stabilization circuit
Power consumption is less than the power consumption of mode of operation power supply stabilization circuit, thus reduces power consumption in the hibernation mode, reaches
The requirement of super low-power consumption.
Accompanying drawing explanation
Fig. 1 is the structural representation of relevant electric power management circuit；
The structural representation of the Fig. 2 a kind of electric power management circuit for providing in the embodiment of the present invention；
The structural representation of the Fig. 3 a kind of park mode power supply stabilization circuit for providing in the embodiment of the present invention；
The structural representation of the Fig. 4 another park mode power supply stabilization circuit for providing in the embodiment of the present invention；
The structural representation of the Fig. 5 another park mode power supply stabilization circuit for providing in the embodiment of the present invention；
The structural representation of the Fig. 6 another park mode power supply stabilization circuit for providing in the embodiment of the present invention.
Detailed description of the invention
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that this
Specific embodiment described by place is used only for explaining the present invention, rather than limitation of the invention.The most also need
It is noted that for the ease of describing, accompanying drawing illustrate only part related to the present invention and not all knot
Structure.
The structural representation of the Fig. 2 a kind of electric power management circuit for providing in the embodiment of the present invention, such as Fig. 2 institute
Showing, this electric power management circuit includes master control digital logic module 10, mode of operation power supply stabilization circuit 20 and stops
Sleep mode power supply stabilization circuit 30；
The working power outfan 202 of mode of operation power supply stabilization circuit 20 and park mode power supply stabilization circuit
The dormancy power output end 302 of 30 is all connected with the master control power input 101 of master control digital logic module 10；
The signal output part 102 of master control digital logic module 10 and the control of mode of operation power supply stabilization circuit 20
End 203 processed connects；
When park mode, master control digital logic module 10 controls mode of operation power supply stabilization circuit 20 and closes,
To provide work by park mode power supply stabilization circuit 30 for master control digital logic module 10 when park mode
Make voltage.
Wherein, mode of operation power supply stabilization circuit 20 is in the operational mode for master control digital logic module 10
Power supply, so that master control digital logic module 10 can control and manage the duty of system.Due to Working mould
Formula power supply stabilization circuit 20 need to meet master control digital logic module 10 in working order under voltage and power consumption
Requirement, thus the power consumption of mode of operation power supply stabilization circuit 20 is bigger.Park mode power supply stabilization circuit 30
For powering for master control digital logic module 10 in the hibernation mode, so that master control digital logic module 10 is tieed up
Hold lower power consumption duty, as only needed the value in holding register and memorizer, maintain low-speed clock to occur
Device, reception external wake signal is to depart from park mode, and sends enabling signal etc. to other circuit modules.
To sum up, the power consumption being under park mode due to master control digital logic module 10 is far below and is in Working mould
Power consumption under formula, thus the power consumption of park mode power supply stabilization circuit 30 is less than mode of operation power supply stabilization circuit
The power consumption of 20.
The technical scheme that the present embodiment provides, in parallel with mode of operation power supply stabilization circuit by increasing, and with
The park mode power supply stabilization circuit that master control digital logic module connects.In the hibernation mode, master control numerical value is patrolled
Collect module and control the closedown of mode of operation power supply stabilization circuit, with steady by park mode power supply when park mode
Volt circuit provides running voltage for master control digital logic module.Owing to park mode power supply stabilization circuit is only required to be
The master control digital logic module being under park mode is powered, and mode of operation power supply stabilization circuit is required to be and is in
Master control digital logic module under mode of operation is powered, thus the power consumption of park mode power supply stabilization circuit is less than
The power consumption of mode of operation power supply stabilization circuit, thus reduce power consumption in the hibernation mode, reach super low-power consumption
Requirement.
In the operational mode, it is higher than dormancy mould due to the setting output voltage of mode of operation power supply stabilization circuit
The setting output voltage of formula power supply stabilization circuit so that the output stage of park mode power supply stabilization circuit is closed automatically
Close, do not affect the output voltage of mode of operation power supply stabilization circuit.
The park mode power supply stabilization circuit structure that the present embodiment provides, by special with automatic biasing function
Negative feedback structure, it is possible to achieve the voltage stabilizing function of super low-power consumption.
It is above the core concept of the application, below in conjunction with the accompanying drawing in the embodiment of the present invention, to the present invention
Technical scheme in embodiment carries out in detail, clearly and completely describes, it is clear that described embodiment is only
It is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, this
Field those of ordinary skill under not making creative work premise, all other embodiments obtained,
Broadly fall into the scope of protection of the invention.
On the basis of above-described embodiment, reference Fig. 2, the signal input part 103 of master control digital logic module 10,
For receiving dormancy or wake-up signal, the dormancy received with foundation or the duty of wake-up signal control system,
As controlled the duty of mode of operation power supply stabilization circuit 20 or other power supply stabilization circuits.Further, work
The power input 201 of mode power mu balanced circuit 20 and the power supply of park mode power supply stabilization circuit 30 are defeated
Enter end 301 to be all connected with external power source.
The structural representation of the Fig. 3 a kind of park mode power supply stabilization circuit for providing in the embodiment of the present invention.
With reference to Fig. 3, this park mode power supply stabilization circuit 30 can include dormancy power input Vin, negative feedback
Circuit 31, current-limiting resistance R2, source follower 32 and dormancy power output end Vout；
The power end 311 of negative-feedback circuit 31, outfan 312, input 313 and earth terminal 314, respectively
With dormancy power input Vin, the input 323 of source follower 32, dormancy power output end Vout and
Ground wire connects；
The power end 321 of source follower 32 is connected with dormancy power input Vin by current-limiting resistance R2,
The outfan 322 of source follower 32 is connected with dormancy power output end Vout.
With reference to Fig. 3, the operation principle of this park mode power supply stabilization circuit is as follows: negative-feedback circuit 31 defeated
Enter end 313 to receive after stabilized circuit outputting voltage from dormancy power output end Vout, due to negative-feedback circuit 31
Anti-phase amplification, outfan 312 voltage of negative-feedback circuit 31 with input 313 voltage reversal change,
Thus dormancy power output end Vout voltage keeps stable.
On the basis of above-described embodiment, negative-feedback circuit can pass through load resistance, N-type field effect transistor and P
Type field effect transistor realizes.With reference to Fig. 4, negative-feedback circuit 31 can include load resistance R1, the second N-type field
Effect pipe MN2 and the first p-type field effect transistor MP1；
First end of load resistance R1 is as the power end 311 of negative-feedback circuit 31, the of load resistance R1
The drain electrode of two ends and the second N-type field effect transistor MN2 connects the outfan 312 as negative-feedback circuit 31,
The grid of the second N-type field effect transistor MN2 is as the input 313 of negative-feedback circuit 31, the second N-type field
The source electrode of effect pipe MN2 and the source electrode of the first p-type field effect transistor MP1 connect, and the first p-type field effect
The drain and gate of pipe MP1 connects the earth terminal 314 as negative-feedback circuit 31.
With reference to Fig. 4, due to the effect of the special construction of this negative-feedback circuit, park mode power supply voltage stabilizing can be made
The output voltage Vout of circuit substantially remains in the threshold voltage of a N-type field effect transistor plus a p-type field
The threshold voltage of effect pipe adds enough overdrive voltages.
With reference to Fig. 5, source follower 32 can be the first N-type field effect transistor MN1, the first N-type field effect
Should the grid of pipe MN1, drain electrode and source electrode, respectively as input 323, the power end of source follower 32
321 and outfan 322.
With reference to Fig. 5, in order to allow lower external power source, exemplary, the first N-type field effect transistor MN1
It can be depletion type (Native) field effect transistor.Concrete, due to the grid of the first N-type field effect transistor MN1
Pole tension (input voltage) needs the amplitude higher than source voltage (output voltage) threshold voltage, consumption
The threshold voltage of type field effect transistor is close to 0 to the greatest extent, thus the grid voltage of the first N-type field effect transistor MN1 can
To be near or below source voltage such that it is able to effectively reduce the voltage of external power source.
With reference to Fig. 5, exemplary, the resistance of load resistance R1 can be a megohm level.Concrete, due to
Load resistance R1 is used for arranging the operating current of park mode power supply stabilization circuit, in order to make park mode power supply
The power consumption of mu balanced circuit is submicron level, and the resistance of load resistance R1 can be a megohm level.Further,
In order to reduce park mode power supply stabilization circuit area on chip, load resistance R1 can be polysilicon electricity
The long narrow raceway groove p-type field effect transistor of the grounded-grid of resistance or default value series connection.It should be noted that this
Default value is not especially limited by embodiment, only needs to make the resistance of load resistance R1 reach a megohm level
?.
With reference to Fig. 5, exemplary, the resistance of current-limiting resistance R2 can be a kilohm level.If dormancy power supply
Output end vo ut and earth short, current-limiting resistance R2 can limit the second N-type field effect transistor MN2 and output
Electric current, prevents that short circuit current is excessive causes circuit to damage.
Further, the output of park mode power supply stabilization circuit is that the output with mode of operation power supply stabilization circuit connects
Together.In the operational mode, the output of mode of operation power supply stabilization circuit is higher than park mode power supply
The intrinsic output voltage of mu balanced circuit, the source electrode of the i.e. first N-type field effect transistor or the second N-type field effect transistor
Grid voltage is driven high, due to the negative feedback of the second N-type field effect transistor, the first N-type field effect transistor
Grid voltage is pulled low, and makes the first N-type field effect transistor be not turned on, thus in the operational mode, park mode
Power supply stabilization circuit does not affect the work of mode of operation power supply stabilization circuit.
With reference to Fig. 6, exemplary, park mode mu balanced circuit may comprise compensating for electric capacity C1, compensates electric capacity
One end of C1 is connected with the outfan 312 of negative-feedback circuit 31, other end ground connection.Due to park mode voltage stabilizing
Circuit is negative feedback structure, needs to compensate electric capacity C1 and makes the open loop phase allowance in loop sufficiently large, allows dormancy mould
Formula mu balanced circuit can keep steady statue.
With reference to Fig. 6, exemplary, park mode mu balanced circuit can include the 3rd N-type field effect transistor MN3；
The drain electrode of the 3rd N-type field effect transistor MN3 is connected with dormancy power output end Vout, the 3rd N-type field effect
The grid of pipe MN3 and source grounding.Due to the grounded-grid of the 3rd N-type field effect transistor MN3, all the time
It is in not on-state, only na or the leakage current of pico-ampere level so that dormancy power output end Vout is not having
Also can keep the voltage will not be too high in the case of loaded.
The technical scheme that the embodiment of the present invention provides, can be used in the wireless radiofrequency of 0.18um field effect transistor technique
In receive-transmit system, external input voltage allows change indicator 1.9V～3.6V, core circuit running voltage 1.8V.
In the hibernation mode, the exporting change scope of park mode voltage-stabilized power supply circuit is 1.3V～1.6V, whole system
Park mode power consumption is less than 1uA.
The technical scheme that the embodiment of the present invention provides, it is possible to control mould for master control Digital Logic under super low-power consumption
Block provides stable supply voltage, and makes system can allow bigger external input power voltage change range,
Effectively extend the service life of battery, make system application have greater flexibility simultaneously.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.Those skilled in the art
It will be appreciated that the invention is not restricted to specific embodiment described here, can enter for a person skilled in the art
Row various obvious changes, readjust and substitute without departing from protection scope of the present invention.Therefore, though
So by above example, the present invention is described in further detail, but the present invention be not limited only to
Upper embodiment, without departing from the inventive concept, it is also possible to include other Equivalent embodiments more,
And the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. an electric power management circuit, it is characterised in that include master control digital logic module, mode of operation electricity
Source mu balanced circuit and park mode power supply stabilization circuit；
The working power outfan of described mode of operation power supply stabilization circuit and described park mode power supply voltage stabilizing electricity
The dormancy power output end on road all master control power inputs with described master control digital logic module are connected；
The signal output part of described master control digital logic module and the control of described mode of operation power supply stabilization circuit
End connects；
When park mode, described master control digital logic module controls described mode of operation power supply stabilization circuit and closes
Close, being described master control digital logic module when park mode by described park mode power supply stabilization circuit
Running voltage is provided.
Circuit the most according to claim 1, it is characterised in that the letter of described master control digital logic module
Number input, is used for receiving dormancy or wake-up signal.
Circuit the most according to claim 1, it is characterised in that described park mode mu balanced circuit includes
Dormancy power input, negative-feedback circuit, current-limiting resistance, source follower and dormancy power output end；
The power end of described negative-feedback circuit, outfan, input and earth terminal, respectively with described dormancy electricity
Source input, the input of described source follower, described dormancy power output end and ground wire connect；
The power end of described source follower is connected with described dormancy power input by described current-limiting resistance,
The outfan of described source follower is connected with described dormancy power output end.
Circuit the most according to claim 3, it is characterised in that
Described negative-feedback circuit includes load resistance, the second N-type field effect transistor and the first p-type field effect transistor；
First end of described load resistance is as the power end of described negative-feedback circuit, the of described load resistance
Two ends are connected the outfan as described negative-feedback circuit with the drain electrode of described second N-type field effect transistor, described
The grid of the second N-type field effect transistor is as the input of described negative-feedback circuit, described second N-type field effect
The source electrode of pipe is connected with the source electrode of described first p-type field effect transistor, and the leakage of described first p-type field effect transistor
Pole and grid connect the earth terminal as described negative-feedback circuit.
Circuit the most according to claim 4, it is characterised in that
Described source follower is the first N-type field effect transistor, the grid of described first N-type field effect transistor, leakage
Pole and source electrode, respectively as input, power end and the outfan of described source follower.
Circuit the most according to claim 5, it is characterised in that described first N-type field effect transistor is
Depletion field effect transistor.
Circuit the most according to claim 5, it is characterised in that the resistance of described load resistance is megaohm
Nurse level, the resistance of described current-limiting resistance is a kilohm level.
Circuit the most according to claim 4, it is characterised in that described park mode mu balanced circuit includes
Compensating electric capacity, one end of described compensation electric capacity is connected with the outfan of described negative-feedback circuit, other end ground connection.
Circuit the most according to claim 4, it is characterised in that described park mode mu balanced circuit includes
3rd N-type field effect transistor；
The drain electrode of described 3rd N-type field effect transistor is connected with described dormancy power output end, described 3rd N-type
The grid of field effect transistor and source grounding.
Circuit the most according to claim 4, it is characterised in that described load resistance is polysilicon electricity
The long narrow raceway groove p-type field effect transistor of the grounded-grid of resistance or default value series connection.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610487946.4A CN105958799B (en) | 2016-06-28 | 2016-06-28 | A kind of electric power management circuit |
| PCT/CN2016/093262 WO2018000517A1 (en) | 2016-06-28 | 2016-08-04 | Power management circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610487946.4A CN105958799B (en) | 2016-06-28 | 2016-06-28 | A kind of electric power management circuit |
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| CN105958799A true CN105958799A (en) | 2016-09-21 |
| CN105958799B CN105958799B (en) | 2019-01-04 |
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| CN201610487946.4A Active CN105958799B (en) | 2016-06-28 | 2016-06-28 | A kind of electric power management circuit |
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| WO (1) | WO2018000517A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109270856A (en) * | 2017-07-13 | 2019-01-25 | 上海华虹挚芯电子科技有限公司 | For the electric power management circuit of low-consumption wireless chip |
| CN111327103A (en) * | 2018-12-17 | 2020-06-23 | 北京华航无线电测量研究所 | Double-module parallel output power supply system based on pressure difference control |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108683416B (en) * | 2018-07-25 | 2023-09-15 | 上海艾为电子技术股份有限公司 | Load switch control circuit |
| US11658571B2 (en) | 2020-04-01 | 2023-05-23 | Analog Devices International Unlimited Company | Low power regulator circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109270856A (en) * | 2017-07-13 | 2019-01-25 | 上海华虹挚芯电子科技有限公司 | For the electric power management circuit of low-consumption wireless chip |
| CN111327103A (en) * | 2018-12-17 | 2020-06-23 | 北京华航无线电测量研究所 | Double-module parallel output power supply system based on pressure difference control |
Also Published As
| Publication number | Publication date |
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| CN105958799B (en) | 2019-01-04 |
| WO2018000517A1 (en) | 2018-01-04 |
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