CN109240873A - A kind of memory signal testing plate - Google Patents
A kind of memory signal testing plate Download PDFInfo
- Publication number
- CN109240873A CN109240873A CN201811093879.3A CN201811093879A CN109240873A CN 109240873 A CN109240873 A CN 109240873A CN 201811093879 A CN201811093879 A CN 201811093879A CN 109240873 A CN109240873 A CN 109240873A
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- pcb substrate
- cabling
- via hole
- conductive bar
- test board
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of memory signal testing plates, are provided in the side wall of the first PCB substrate and are electrically connected the via hole for being located at first area with corresponding conductive bar with the one-to-one conductive bar of the first via hole, the first cabling；The via hole for being located at second area is electrically connected by the second cabling with corresponding conductive bar.In use, the pin of memory can be electrically connected correspondingly with the via hole in test board, and by above-mentioned first cabling and the second cabling the pin of memory is finally electrically connected with the conductive bar of test board side wall.The density of surface cabling in the first PCB substrate can be effectively reduced by the first cabling and the second cabling that are distributed in the first PCB substrate different surfaces；While each pin in memory being finally electrically connected to the conductive bar of test board side wall, and the extraction that the signal for being transmitted to conductive bar can be convenient, integrity test is carried out to memory signal to realize.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of memory signal testing plate.
Background technique
As in the past few years society is continuous progressive and the continuous development of science and technology, computer technology obtained it is considerable into
Step.And the memory techniques in computer are also an important component part in computer field.
At this stage, DDR4 particle is the memory techniques of a new generation, because DDR4 particle has more compared to DDR3 particle
Reliable transmission specification, more reliable data reliability, the performances such as more energy efficient, in server, computer etc. using increasing.
But the size of DDR4 particle is smaller, chips close degree is higher, and cabling is intensive, causes the test and comparison of DDR4 particle difficult, existing
Stage certain pins extraction seldom a part of signals can only measure from DDR4 particle, and can not be to the signal of DDR4 whole
It is completely tested, the test of DDR4 particle is caused never to be unfolded.
It is those skilled in the art that signal so how to the higher memory of chips close degree, such as in DDR4, which carries out test,
Member's urgent problem.
Summary of the invention
The object of the present invention is to provide a kind of memory signal testing plates, can be by memory signal testing plate to the letter of memory
It number is completely tested.
In order to solve the above technical problems, the present invention provides a kind of memory signal testing plate, including the first PCB substrate；
First PCB substrate includes opposite first surface and second surface, the company of being provided in first PCB substrate
Lead to multiple first via holes of the first surface Yu the second surface, the side wall of first PCB substrate be provided with mutually every
From multiple conductive bars, the conductive bar and first via hole correspond；
It is provided with a plurality of the first mutually isolated cabling in the first surface, is located at firstth area of the first PCB substrate
First via hole in domain is electrically connected by first cabling with the corresponding conductive bar；
It is provided with a plurality of the second mutually isolated cabling in the second surface, is located at secondth area of the first PCB substrate
First via hole in domain is electrically connected by second cabling with the corresponding conductive bar.
Optionally, the axis of the conductive bar is parallel to the thickness direction of first PCB substrate；The length of the conductive bar
It spends equal with the thickness of first PCB substrate.
Optionally, the conductive bar is semi- cylindrical conductive bar, and the side wall of first PCB substrate is provided with leads with described
The corresponding groove of electric item, the cambered surface of the conductive bar fit with the groove inner wall.
Optionally, the spacing between the adjacent conductive bar is equal.
Optionally, the conductive bar is copper bar.
Optionally, the test board further include:
Inside first PCB substrate, and it is parallel to the reference layer of the first surface.
Optionally, the test board further include:
Positioned at the first surface of first PCB substrate, first cabling and exposed first via hole are covered
The first transparent protective layer.
Optionally, the test board further include:
Positioned at the second surface of first PCB substrate, second cabling and exposed first via hole are covered
The second transparent protective layer.
Optionally, first PCB substrate is S7038 substrate.
Optionally, the test board further includes the second PCB substrate；
Second PCB substrate includes opposite third surface and the 4th surface, the company of being provided in second PCB substrate
Lead to multiple second via holes on the third surface Yu the 4th surface, second via hole and first via hole one are a pair of
It answers；
Pass through between the third surface of second PCB substrate and the second surface of first PCB substrate
Solder is fixedly connected, so that first via hole is electrically connected with corresponding second via hole.
A kind of memory signal testing plate provided by the present invention, be provided in the first PCB substrate it is multiple through type via hole,
Two ends of the via hole are located at two opposite surfaces in the first PCB substrate.It is provided in the side wall of the first PCB substrate
With via hole one-to-one correspondence and mutually isolated conductive bar, the first surface of the first PCB substrate is provided with a plurality of first cabling, the
The via hole for being located at first area is electrically connected by one cabling with corresponding conductive bar；It is provided in the second surface of the first PCB substrate
The via hole for being located at second area is electrically connected by a plurality of second cabling, the second cabling with corresponding conductive bar.In use, interior
The pin deposited can be electrically connected correspondingly with the via hole in test board, and be made by above-mentioned first cabling and the second cabling
The pin of memory is finally electrically connected with the conductive bar of test board side wall.Due to the pin of memory be arranged it is relatively intensive, and
It can be effectively reduced in the first PCB substrate by the first cabling and the second cabling that are distributed in the first PCB substrate different surfaces
The density of surface cabling；Each pin in memory is finally electrically connected to the conductive bar of test board side wall simultaneously, and is transmitted to
The extraction that the signal of conductive bar can be convenient, it can convenient for being tested by the conductive bar each signal in memory,
Integrity test is carried out to memory signal to realize.
Detailed description of the invention
It, below will be to embodiment or existing for the clearer technical solution for illustrating the embodiment of the present invention or the prior art
Attached drawing needed in technical description is briefly described, it should be apparent that, the accompanying drawings in the following description is only this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram of memory signal testing plate provided by the embodiment of the present invention；
Fig. 2 is the top view of memory signal testing plate in Fig. 1；
Fig. 3 is the bottom view of memory signal testing plate in Fig. 1；
Fig. 4 is a kind of structural schematic diagram of specific memory signal testing plate provided by the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of the specific memory signal testing plate of another kind provided by the embodiment of the present invention；
Fig. 6 is the top view of the second PCB substrate in Fig. 5；
Fig. 7 is the bottom view of the second PCB substrate in Fig. 5.
In figure: 1. first PCB substrates, 2. first via holes, 3. conductive bars, 4. first cablings, 5. second cablings, 6. references
Layer, 7. first transparent protective layers, 8. second transparent protective layers, 9. second PCB substrates, 10. second via holes, 11. solders.
Specific embodiment
Core of the invention is to provide a kind of memory signal testing plate.In the prior art, memory at this stage, such as
The size of DDR4 is smaller, and chips close degree is higher, and cabling is intensive, leads to not directly be directly connected to from whole pins in DDR4
Lead out, so that integrity test can not be carried out to memory, such as the signal of DDR4.
And a kind of memory signal testing plate provided by the present invention, it is provided in the first PCB substrate multiple through type mistake
Two ends in hole, the via hole are located at two opposite surfaces in the first PCB substrate.It is set in the side wall of the first PCB substrate
It is equipped with and is corresponded with via hole and mutually isolated conductive bar, the first surface of the first PCB substrate is provided with a plurality of first and walks
The via hole for being located at first area is electrically connected by line, the first cabling with corresponding conductive bar；It is set in the second surface of the first PCB substrate
It is equipped with a plurality of second cabling, the via hole for being located at second area is electrically connected by the second cabling with corresponding conductive bar.In use process
In, the pin of memory can be electrically connected correspondingly with the via hole in test board, and be walked by above-mentioned first cabling and second
Line is electrically connected the pin of memory finally with the conductive bar of test board side wall.Due to memory pin be arranged it is relatively close
Collection, and the first PCB base can be effectively reduced in the first cabling and the second cabling by being distributed in the first PCB substrate different surfaces
The density of surface cabling in plate；Each pin in memory is finally electrically connected to the conductive bar of test board side wall simultaneously, and is passed
Transport to the extraction that the signal of conductive bar can be convenient, it can convenient for surveying by the conductive bar to each signal in memory
Examination carries out integrity test to memory signal to realize.
In order to enable those skilled in the art to better understand the solution of the present invention, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.Obviously, described embodiments are only a part of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
Referring to FIG. 1, Fig. 2 and Fig. 3, Fig. 1 are a kind of structure of memory signal testing plate provided by the embodiment of the present invention
Schematic diagram；Fig. 2 is the top view of memory signal testing plate in Fig. 1；Fig. 3 is the bottom view of memory signal testing plate in Fig. 1.
Referring to Fig. 1, in embodiments of the present invention, the memory signal testing plate includes the first PCB substrate 1；Described first
PCB substrate 1 includes opposite first surface and second surface, and the connection first surface is provided in first PCB substrate 1
With multiple first via holes 2 of the second surface, the side wall of first PCB substrate 1 is provided with mutually isolated multiple conductions
Item 3, the conductive bar 3 are corresponded with first via hole 2；A plurality of mutually isolated first is provided in the first surface
Cabling 4, first via hole 2 positioned at 1 first area of the first PCB substrate pass through first cabling 4 and corresponding institute
State the electrical connection of conductive bar 3；It is provided with a plurality of the second mutually isolated cabling 5 in the second surface, is located at the first PCB base
First via hole 2 of 1 second area of plate is electrically connected by second cabling 5 with the corresponding conductive bar 3.
Above-mentioned first PCB substrate 1 is the main body of entire test board, preferably, can select in embodiments of the present invention
S7038 substrate is preferably S7038 as the first PCB substrate 1, the i.e. material of substrate.Select S7038 substrate as the first PCB base
Plate 1 can be by the impedance control of the first PCB substrate 1 in 50ohm or so, so as to which the signal for doing and transmitting in substrate is effectively reduced
Loss.Certainly, the substrate of other materials can also be selected as the first PCB substrate 1 in embodiments of the present invention, in relation to first
The specific material of PCB substrate 1 in embodiments of the present invention and is not specifically limited.
Usually there are two opposite surface, i.e., above-mentioned first surface and second surfaces for tool for above-mentioned first PCB substrate 1.?
In use process, memory would generally be fixed on the first surface of the first PCB substrate 1；And the wiring board for installing memory can be fixed on
The second surface of first PCB substrate 1 is mutually electrically connected between above-mentioned memory and wiring board by the via hole in the first PCB substrate 1
It connects.
Multiple first via holes for being connected to the first surface and the second surface are provided in above-mentioned first PCB substrate 1
2.I.e. above-mentioned first via hole 2 is penetrability via hole, and the both ends of the surface of the first via hole 2 are located at the first surface of the first PCB substrate 1
And second surface.Under normal conditions, the first via hole 2 is located at the end of first surface and distinguishes positioned at the end of second surface
For pad.Specific structure in relation to the first via hole 2 is referred to the prior art, is not detailed Jie in embodiments of the present invention
It continues.It should be noted that mutually isolated insulation between the first via hole 2 being located in the first PCB substrate 1, and the number of the first via hole 2
Amount and distribution need to correspond with the pin of memory to be tested.In use, the pin of memory can with it is corresponding
Hole is located at the end face electrical connection of 1 first surface of the first PCB substrate；And be responsible for memory power wiring board pin can with it is corresponding
Via hole is located at the end face electrical connection of 1 second surface of the first PCB substrate.
The side wall of above-mentioned first PCB substrate 1 is provided with mutually isolated multiple conductive bars 3, i.e., between conductive bar 3 mutually absolutely
Edge.And the quantity of multiple conductive bars 3 needs equal with the quantity of the first via hole 2, allows conductive bar 3 and the first via hole 2 one
One is corresponding.
In embodiments of the present invention, in order to enable the first via hole 2 with corresponding conductive bar 3 convenient for being electrically connected to each other, as
Preferably, the axis of the conductive bar 3 is parallel to the thickness direction of first PCB substrate 1；The length of the conductive bar 3 with
The thickness of first PCB substrate 1 is equal.It is parallel to each other between conductive bar 3, and the both ends of the surface of conductive bar 3 in the axial direction
It is located at the first surface and second surface of the first PCB substrate 1.
Preferably, the memory signal testing plate as provided in the application is one piece of PCB with special construction
Plate, and half Via structure can be made in pcb board, i.e., half via structure can be made at the edge of the first PCB substrate 1, with shape
At above-mentioned conductive bar 3.In half via structure, above-mentioned conductive bar 3 is semi- cylindrical conductive bar 3, i.e., the structure of conductive bar 3 is half
Cylindrical type is provided with groove corresponding with semi- cylindrical conductive bar 3 in the side wall of the first PCB substrate 1 accordingly, the groove it is interior
Wall is a cambered surface, and the cambered surface of semi- cylindrical conductive bar 3 can fit and be fixedly connected with the groove inner wall.By above-mentioned conductive bar
3 are arranged to the production that half via structure is convenient for memory signal testing plate.
Under normal conditions, for the ease of the subsequent memory in 3 surface of conductive bar setting lead to be electrically connected for test board
Signal tested, the spacing between above-mentioned conductive bar 3 is generally equal, i.e., conductive bar 3 is usually uniformly arranged on the first PCB base
The side wall of plate 1.Under normal conditions, in order to reduce cost of manufacture, above-mentioned conductive bar 3 is usually copper bar.It should be noted that
In the side wall of one PCB substrate 1, be not only provided only with the one-to-one conductive bar 3 of the first via hole 2, be also provided with conduct
The conductive bar 3 of ground wire, the conductive bar 3 are used usually as the ground wire of memory signal testing plate.
Referring to fig. 2, above-mentioned first cabling 4 is located at the first surface of the first PCB substrate 1, it should be noted that the first cabling
4 quantity needs to be less than the quantity of the first via hole 2, mutually isolated between a plurality of first cabling 4, i.e., between a plurality of first cabling 4
Mutually insulated.First cabling 4 is used to that the first via hole 2 and first via hole of first area will to be located in the first PCB substrate 1
2 corresponding conductive bars 3 are electrically connected, i.e., one end of the first cabling 4 can be with the first mistake in the first PCB substrate 1 positioned at first area
Hole 2 is in contact, at the same the other end of the first cabling 4 can conductive bar 3 corresponding with first via hole 2 be in contact.
Referring to Fig. 3, above-mentioned second cabling 5 is located at the second surface of the first PCB substrate 1, it should be noted that the second cabling
5 quantity needs to be less than the quantity of the first via hole 2, but the quantity that has altogether of the first cabling 4 and the second cabling 5 usually with the first via hole
2 quantity is equal.It is mutually isolated between a plurality of second cabling 5, i.e., mutually insulated between a plurality of second cabling 5.Described second walks
Line 5 is used to for the first via hole 2 conductive bar 3 corresponding with first via hole 2 for being located at second area in the first PCB substrate 1 being electrically connected
It connects, i.e., one end of the second cabling 5 can be in contact with the first via hole 2 for being located at second area in the first PCB substrate 1, while second
The other end of cabling 5 can conductive bar 3 corresponding with first via hole 2 be in contact.Pass through above-mentioned first cabling 4 and the second cabling
5 may be implemented the first via hole 2 is electrically connected correspondingly with conductive bar 3.
A kind of memory signal testing plate provided by the embodiment of the present invention is provided with multiple run through in the first PCB substrate 1
Type via hole, two ends of the via hole are located at two opposite surfaces in the first PCB substrate 1.In the first PCB substrate 1
Side wall is provided with to be corresponded and mutually isolated conductive bar 3 with via hole, is provided in the first surface of the first PCB substrate 1 more
The via hole for being located at first area is electrically connected by the first cabling of item 4, the first cabling 4 with corresponding conductive bar 3；In the first PCB substrate 1
Second surface be provided with a plurality of second cabling 5, the second cabling 5 will be located at second area via hole and corresponding conductive bar 3 it is electric
Connection.In use, the pin of memory can be electrically connected correspondingly with the via hole in test board, and pass through above-mentioned first
Cabling 4 and the second cabling 5 are electrically connected the pin of memory finally with the conductive bar 3 of test board side wall.Due to drawing for memory
Foot is arranged relatively intensive, and the first cabling 4 and the second cabling 5 by being distributed in 1 different surfaces of the first PCB substrate
The density of surface cabling in the first PCB substrate 1 can be effectively reduced；Each pin in memory is finally electrically connected to survey simultaneously
The conductive bar 3 of test plate (panel) side wall, and the extraction that the signal for being transmitted to conductive bar 3 can be convenient, it can convenient for passing through the conductive bar 3
Each signal in memory is tested, integrity test is carried out to memory signal to realize.
Specific structure in relation to above-mentioned memory signal testing plate will be described in detail in following inventive embodiments.
Referring to FIG. 4, Fig. 4 is a kind of structural representation of specific memory signal testing plate provided by the embodiment of the present invention
Figure.
It is different from foregoing invention embodiment, the embodiment of the present invention is on the basis of foregoing invention embodiment, further
The structure of memory signal testing plate is specifically limited.Remaining content has carried out detailed Jie in foregoing invention embodiment
It continues, is no longer repeated herein.
Referring to fig. 4, in embodiments of the present invention, the memory signal testing plate further includes being located at first PCB substrate 1
Inside, and it is parallel to the reference layer 6 of the first surface.
Above-mentioned first PCB substrate 1 is usually multi-layer compound structure, and in embodiments of the present invention, in the first PCB substrate 1
Portion is provided with one layer of reference layer 6, which is typically parallel to the first surface of the first PCB substrate 1.Called reference layer 6, i.e.,
One layer of metal layer, the metal layer can play the role of electrostatic screen in first PCB substrate 1, prevent electromagnetic radiation, avoid simultaneously
The interference being transmitted separately between 1 first surface of the first PCB substrate and the signal of second surface.It should be noted that above-mentioned ginseng
It examines and needs that there is through-hole corresponding with above-mentioned via hole in layer 6, be electrically connected with preventing from contacting between reference layer 6 and via hole.Meanwhile
Reference layer 6 usually requires and being electrically connected to ground in memory signal testing plate.Specific structure and specific material in relation to reference layer 6
Matter can refer to the prior art, in embodiments of the present invention and be not specifically limited.
Preferably, in embodiments of the present invention, the test board further includes the institute positioned at first PCB substrate 1
First surface is stated, the first transparent protective layer 7 of first cabling 4 and exposed first via hole 2 is covered.And it is located at described
The second surface of first PCB substrate 1, cover second cabling 5 and exposed first via hole 2 second are transparency protected
Layer 8.
Above-mentioned the first cabling 4 that 1 surface of the first PCB substrate is arranged in and the second cabling 5 are in addition to being used for the first via hole 2
Except the electrical connection of corresponding conductive bar 3, the first cabling 4 is arranged in first surface, and the second cabling 5 is arranged second
Surface can also observe the pin of memory is electrically connected particular by which via hole with which conductive bar 3 convenient for user,
Convenient for the observation and specific operation during the test of user.And in order to further protect above-mentioned first cabling 4, so that the
One cabling 4 is not easy to be damaged, and covering first can be arranged in the first surface of the first PCB substrate 1 in embodiments of the present invention and walk
Line 4, and the first transparent protective layer 7 of exposed first via hole 2, to guarantee while protecting the first cabling 4, so that the first via hole
2 still can be electrically connected with memory, while user being allowed to observe the link position of the first cabling 4.Related above-mentioned first
The specific material of transparent protective layer 7 in embodiments of the present invention and is not specifically limited, depending on the circumstances.
It is similar with above-mentioned first transparent protective layer 7, in order to further protect above-mentioned second cabling 5, so that the second cabling 5
It is not easy to be damaged, the second cabling 5 of covering can be set in the second surface of the first PCB substrate 1 in embodiments of the present invention, and naked
Reveal the second transparent protective layer 8 of the first via hole 2, to guarantee while protecting the second cabling 5, so that the first via hole 2 still may be used
With with the circuit board electrical connection for power supply, while user being allowed to observe the link position of the second cabling 5.It is related above-mentioned
The specific material of second transparent protective layer 8 in embodiments of the present invention and is not specifically limited, depending on the circumstances.
A kind of memory signal testing plate provided by the embodiment of the present invention is internally provided with reference layer in the first PCB substrate 1
6, electrostatic screen can be played the role of, prevent electromagnetic radiation, while avoiding being transmitted separately to 1 first surface of the first PCB substrate
Hair shaft is disturbed between the signal of second surface；First transparent protective layer 7 of 1 first surface of the first PCB substrate is set and is set
The second transparent protective layer 8 set in 1 second surface of the first PCB substrate can protect the same of the first cabling 4 and the second cabling 5
When, allow user to observe the link position of the first cabling 4 and the second cabling 5, convenient for user to the signal of memory into
Row measurement.
In specific measurement process, it is being responsible for being usually provided with other elements to the PCB surface that memory is powered, and
Said elements may hinder the setting of above-mentioned first PCB substrate 1 and hinder that lead is arranged in the side wall of the first PCB substrate 1.
It needs that the second PCB substrate is arranged in the lower section of the first PCB substrate 1 at this time, is padded the first PCB substrate 1 by the second PCB substrate
Height, to avoid obstruction of the element to the first PCB substrate 1 that assist side surface is arranged.In relation to the specific of memory signal testing plate
Content will be described in detail in following inventive embodiments.
Referring to FIG. 5, Fig. 6 and Fig. 7, Fig. 5 are that the specific memory signal of another kind provided by the embodiment of the present invention is surveyed
The structural schematic diagram of test plate (panel)；Fig. 6 is the top view of the second PCB substrate in Fig. 5；Fig. 7 is the bottom view of the second PCB substrate in Fig. 5.
It is different from foregoing invention embodiment, the embodiment of the present invention is on the basis of foregoing invention embodiment, further
The structure of memory signal testing plate is specifically limited.Remaining content has carried out detailed Jie in foregoing invention embodiment
It continues, is no longer repeated herein.
Referring to Fig. 5, in embodiments of the present invention, the memory signal testing plate further includes the second PCB substrate 9；Described
Two PCB substrates 9 include opposite third surface and the 4th surface, and the connection third table is provided in second PCB substrate 9
Multiple second via holes 10 in face and the 4th surface, second via hole 10 are corresponded with first via hole 2；Described
Connect between the third surface of two PCB substrates 9 and the second surface of first PCB substrate 1 by the way that solder 11 is fixed
It connects, so that first via hole 2 is electrically connected with corresponding second via hole 10.
Referring to Fig. 6 and Fig. 7, above-mentioned second PCB substrate 9 is for when in use by above-mentioned first PCB substrate 1 and with the
The memory of one PCB substrate, 1 first surface contact is padded.Similar with the first PCB substrate 1, the second PCB substrate 9 has opposite
Third surface and the 4th surface, and in the second PCB substrate 9, it is provided with the connection third surface and the 4th surface
Multiple second via holes 10.I.e. above-mentioned second via hole 10 is penetrability via hole, and the both ends of the surface of the second via hole 10 are located at second
The third surface and the 4th surface of PCB substrate 9.It should be noted that in embodiments of the present invention, the second via hole 10 needs and the
One via hole 2 corresponds, so that the first via hole 2 passes through the circuit board electrical connection of the second via hole 10 and power supply.
In the specific use process, the third surface of the second PCB substrate 9 can pass through solder 11 and the first PCB substrate 1
Second surface is fixedly connected, so that the first via hole 2 is electrically connected with corresponding second via hole 10.And the wiring board for being responsible for power supply can be with
4th surface of the second PCB substrate 9 is in contact, and is fixedly connected by solder 11, so that each pin of memory can pass through
Above-mentioned first via hole 2 and corresponding second via hole 10 are fixedly connected with wiring board.In relation to the specific of above-mentioned second PCB substrate 9
Material in embodiments of the present invention and is not specifically limited, depending on the circumstances.
In embodiments of the present invention, commonly interior at this stage to save as DDR4 particle, and the size of DDR4 particle is usually
13.5mm*7.5mm, accordingly in embodiments of the present invention, the size of the first PCB substrate 1 is usually 14.5mm*9mm, and first
The thickness of PCB substrate 1 then gets over Bao Yuehao.And the size of the second PCB substrate 9 provided by the embodiment of the present invention is usually with first
PCB substrate 1 is similar, also usually 14.5mm*9mm；Simultaneously in order not to introduce the Via effect being likely to occur, make signal may
Reflection back and forth occurs in the vias, and influences the quality of signal, the thickness of above-mentioned second PCB substrate 9 is usually in 1.4mm
Left and right.
A kind of memory signal testing plate provided by the embodiment of the present invention is provided in the second surface of the first PCB substrate 1
It, may be to the so as to avoid the element on setting assist side surface for the second PCB substrate 9 that the first PCB substrate 1 is padded
Obstruction caused by one PCB substrate 1.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with it is other
The difference of embodiment, same or similar part may refer to each other between each embodiment.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
A kind of memory signal testing plate provided by the present invention is described in detail above.It is used herein specifically
Principle and implementation of the present invention are described for a example, the present invention that the above embodiments are only used to help understand
Method and its core concept.It should be pointed out that for those skilled in the art, not departing from original of the invention
, can be with several improvements and modifications are made to the present invention under the premise of reason, these improvement and modification also fall into right of the present invention and want
In the protection scope asked.
Claims (10)
1. a kind of memory signal testing plate, which is characterized in that including the first PCB substrate；
First PCB substrate includes opposite first surface and second surface, and connection institute is provided in first PCB substrate
Multiple first via holes of first surface Yu the second surface are stated, the side wall of first PCB substrate is provided with mutually isolated
Multiple conductive bars, the conductive bar and first via hole correspond；
A plurality of the first mutually isolated cabling is provided in the first surface, positioned at first PCB substrate first area
First via hole is electrically connected by first cabling with the corresponding conductive bar；
A plurality of the second mutually isolated cabling is provided in the second surface, positioned at the first PCB substrate second area
First via hole is electrically connected by second cabling with the corresponding conductive bar.
2. test board according to claim 1, which is characterized in that the axis of the conductive bar is parallel to the first PCB
The thickness direction of substrate；The length of the conductive bar is equal with the thickness of first PCB substrate.
3. test board according to claim 2, which is characterized in that the conductive bar is semi- cylindrical conductive bar, described the
The side wall of one PCB substrate is provided with groove corresponding with the conductive bar, the cambered surface of the conductive bar and the groove inner wall
It fits.
4. test board according to claim 3, which is characterized in that the spacing between the adjacent conductive bar is equal.
5. test board according to claim 4, which is characterized in that the conductive bar is copper bar.
6. test board according to claim 1, which is characterized in that the test board further include:
Inside first PCB substrate, and it is parallel to the reference layer of the first surface.
7. test board according to claim 1, which is characterized in that the test board further include:
Positioned at the first surface of first PCB substrate, the of first cabling and exposed first via hole is covered
One transparent protective layer.
8. test board according to claim 1, which is characterized in that the test board further include:
Positioned at the second surface of first PCB substrate, the of second cabling and exposed first via hole is covered
Two transparent protective layers.
9. test board according to claim 1, which is characterized in that first PCB substrate is S7038 substrate.
10. according to claim 1 to test board described in any one of 9 claims, which is characterized in that the test board further includes
Second PCB substrate；
Second PCB substrate includes opposite third surface and the 4th surface, and connection institute is provided in second PCB substrate
Multiple second via holes on third surface Yu the 4th surface are stated, second via hole and first via hole correspond；
Pass through solder between the third surface of second PCB substrate and the second surface of first PCB substrate
It is fixedly connected, so that first via hole is electrically connected with corresponding second via hole.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811093879.3A CN109240873A (en) | 2018-09-19 | 2018-09-19 | A kind of memory signal testing plate |
| PCT/CN2019/093320 WO2020057216A1 (en) | 2018-09-19 | 2019-06-27 | Memory signal test board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811093879.3A CN109240873A (en) | 2018-09-19 | 2018-09-19 | A kind of memory signal testing plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109240873A true CN109240873A (en) | 2019-01-18 |
Family
ID=65058331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811093879.3A Pending CN109240873A (en) | 2018-09-19 | 2018-09-19 | A kind of memory signal testing plate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109240873A (en) |
| WO (1) | WO2020057216A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020057216A1 (en) * | 2018-09-19 | 2020-03-26 | 郑州云海信息技术有限公司 | Memory signal test board |
| CN112904180A (en) * | 2021-01-22 | 2021-06-04 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| US11933815B2 (en) | 2020-08-14 | 2024-03-19 | Changxin Memory Technologies, Inc. | Test fixture |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1422108A (en) * | 2001-11-27 | 2003-06-04 | 日本电气株式会社 | Printed circuit board with testing point formed at side |
| CN101325840A (en) * | 2007-06-15 | 2008-12-17 | 富士康(昆山)电脑接插件有限公司 | Anti-oxidization printed circuit board and gold finger thereof as well as method for manufacturing the printed circuit board |
| CN201607505U (en) * | 2010-02-25 | 2010-10-13 | 深圳市普联技术有限公司 | Test suite for testing parameters of network signal transformer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11258294A (en) * | 1998-03-12 | 1999-09-24 | Jsr Corp | Apparatus and method for inspection of circuit board |
| CN207586893U (en) * | 2018-01-02 | 2018-07-06 | 蓝思科技（长沙）有限公司 | A kind of two-sided conductive structure and touch panel |
| CN109240873A (en) * | 2018-09-19 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of memory signal testing plate |
-
2018
- 2018-09-19 CN CN201811093879.3A patent/CN109240873A/en active Pending
-
2019
- 2019-06-27 WO PCT/CN2019/093320 patent/WO2020057216A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1422108A (en) * | 2001-11-27 | 2003-06-04 | 日本电气株式会社 | Printed circuit board with testing point formed at side |
| CN101325840A (en) * | 2007-06-15 | 2008-12-17 | 富士康(昆山)电脑接插件有限公司 | Anti-oxidization printed circuit board and gold finger thereof as well as method for manufacturing the printed circuit board |
| CN201607505U (en) * | 2010-02-25 | 2010-10-13 | 深圳市普联技术有限公司 | Test suite for testing parameters of network signal transformer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020057216A1 (en) * | 2018-09-19 | 2020-03-26 | 郑州云海信息技术有限公司 | Memory signal test board |
| US11933815B2 (en) | 2020-08-14 | 2024-03-19 | Changxin Memory Technologies, Inc. | Test fixture |
| CN112904180A (en) * | 2021-01-22 | 2021-06-04 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| CN112904180B (en) * | 2021-01-22 | 2022-04-19 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| WO2022156132A1 (en) * | 2021-01-22 | 2022-07-28 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| US11846670B2 (en) | 2021-01-22 | 2023-12-19 | Changxin Memory Technologies, Inc. | Chip testing board and chip testing method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020057216A1 (en) | 2020-03-26 |
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Application publication date: 20190118 |