CN109234807B - Stretchable crystal semiconductor nanowire and preparation method thereof - Google Patents

Stretchable crystal semiconductor nanowire and preparation method thereof Download PDF

Info

Publication number
CN109234807B
CN109234807B CN201810614845.8A CN201810614845A CN109234807B CN 109234807 B CN109234807 B CN 109234807B CN 201810614845 A CN201810614845 A CN 201810614845A CN 109234807 B CN109234807 B CN 109234807B
Authority
CN
China
Prior art keywords
nanowire
stretchable
substrate
silicon
crystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810614845.8A
Other languages
Chinese (zh)
Other versions
CN109234807A (en
Inventor
余林蔚
薛兆国
董泰阁
王军转
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University
Original Assignee
Nanjing University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University filed Critical Nanjing University
Priority to EP18817489.0A priority Critical patent/EP3640374A4/en
Priority to PCT/CN2018/091544 priority patent/WO2018228543A1/en
Publication of CN109234807A publication Critical patent/CN109234807A/en
Priority to US16/714,724 priority patent/US20200118818A1/en
Application granted granted Critical
Publication of CN109234807B publication Critical patent/CN109234807B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/08—Germanium
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/42—Gallium arsenide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02645—Seed materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02653—Vapour-liquid-solid growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

The invention relates to a stretchable crystalline semiconductor nanowire and a preparation method thereof, wherein the stretchable crystalline semiconductor nanowire is provided with an elongated main body, the diameter of the nanowire is between 20 and 200 nanometers, and the nanowire is of a crystalline inorganic semiconductor structure. The stretchable crystalline semiconductor nanowire is of a bent structure and is provided with a plurality of stretchable units in the axial direction, and the stretchable units are sequentially connected, so that the stretchable crystalline semiconductor nanowire is formed. The invention adopts methods such as IP-SLS and the like to grow the nanowire guided by the channel step in PECVD and utilizes the modern micromachining technology to manufacture the spring structure crystal nanowire array. Since the cross section of the nano wire and the guide channel can be effectively adjusted, the peeling and the transfer to other flexible substrates can be further carried out. The method for preparing the spring structure crystal nanowire has wide prospects in the field of flexible electronics and the application aspect of sensors.

Description

Stretchable crystal semiconductor nanowire and preparation method thereof
Priority declaration
This application is a partial continuation of CN201710450420.3 (publication No. CN107460542A), filed 2017, 6, 15, and claiming priority thereto, the entire contents of which are hereby incorporated by reference.
Technical Field
The invention relates to the field of flexible and stretchable electronics and devices, in particular to a manufacturing method for manufacturing and forming a spring structure crystal nanowire with flexible and stretchable properties on a substrate by utilizing a channel guide plane nanowire growth technology through a micromachining process. In particular to a method for preparing a spring structure crystal nanowire by a planar semiconductor nanowire with self-positioning and self-orientation growth, transfer and electrical integration guided by a channel.
Background
With the development of the modern electronic display industry, flexible and stretchable electronic devices (especially display devices) play an increasingly important role in aspects of modern science and technology, national economy and daily life because of easier meeting of practical application requirements and flexible material characteristics, and in the research field, the growth and preparation technology of materials plays an important role.
Liquid-solid phase (SLS) growth mechanism: the mechanism of SLS growth is similar to the VLS mechanism, differing from the VLS mechanism only in that, during growth of the VLS mechanism, the required raw materials are provided from the gas phase; in the SLS mechanism growth process, the required raw materials are provided from solution, and generally, low melting point metals (such as In, Sn or Bi) are commonly used as cosolvents (fluorooligomers) In the method, which correspond to catalysts In the VLS mechanism.
The silicon-based material has no harm to human body due to wide industrial foundation, mature process and semiconductor preparation technology, and the similar properties of the carbon-based material of human body structure, and the nano-scale silicon material is easy to degrade, so that the silicon-based nano technology and the flexible stretchable electronic field are combined to obtain great utility.
The growth of materials for stretchable crystalline nanowire spring structures is the basis for flexible and stretchable electronic devices, and the prior art does not have a good solution.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a stretchable crystalline semiconductor nanowire and a method for preparing the same. In particular, planar semiconductor nanowire devices are fabricated along a particular guiding channel by directional growth, transfer and integration methods.
According to one aspect of the present invention, there is provided a stretchable crystalline semiconductor nanowire:
the stretchable crystalline semiconductor nanowires have an elongated body, the nanowires have a diameter between 20-200 nanometers, and the nanowires are crystalline inorganic semiconductor structures.
The stretchable crystalline semiconductor nanowire is of a bent structure and is provided with a plurality of stretchable units in the axial direction, and the stretchable units are sequentially connected, so that the stretchable crystalline semiconductor nanowire is formed.
Further, the stretchable unit of the stretchable crystalline semiconductor nanowire is one or more of a combination of a circular arc shape, a semicircular shape, a half-track shape, a Z shape, a V shape, and an M shape.
Further, the length in the maximum stretched state is more than 1.5 times, preferably 2 times or more, and preferably 2.7 times the length in the natural state.
In one embodiment, crystalline nanowires are grown, which are single crystal nanowires of Si, SiGe, Ge, or GaAs, or the like.
According to yet another aspect of the present invention, there is provided a method of preparing a stretchable crystalline semiconductor nanowire, comprising the steps of:
1) removing residues on the surface of a substrate by adopting a substrate comprising glass, a silicon dioxide sheet or a silicon wafer;
2) etching a step with a certain depth on the surface of the substrate, and further etching and manufacturing a specific guide channel along the step;
3) by a planar nanowire guiding growth method, the crystal nanowires are precisely grown along the guiding channel, and a catalytic metal film block is deposited at one end of the guiding channel by evaporation and serves as an initial point for forming metal droplets and an initial position of the nanowires;
4) processing the metal film by utilizing reductive plasma comprising hydrogen in a PECVD system, removing an oxide layer on the surface, and forming nano metal catalytic particles with the diameter between dozens of nanometers and one micron;
5) depositing and covering an amorphous semiconductor layer with a proper thickness as a precursor medium;
6) annealing growth is carried out in vacuum or non-oxidizing atmosphere, the temperature is above 250 ℃, so that the metal liquid drop starts to move along the guide step, the amorphous layer is absorbed, and the crystalline nanowire structure is deposited along the way.
Further, in the step 1), the silicon wafer is a P-type or N-type monocrystalline or polycrystalline silicon wafer with a surface covered with dielectric layers such as silicon dioxide or silicon nitride, the glass is common glass or quartz glass, and the polymer can be a flexible polymer which can bear certain high temperature (350 ℃) treatment and is compatible with a vacuum environment; the thickness of the silicon dioxide substrate is more than 250 nm.
Further, step 5) comprises: covering an amorphous semiconductor layer with proper thickness (from a few nanometers to a few hundred nanometers) by using a PECVD system as a precursor dielectric layer; for growing crystalline silicon, crystalline germanium or crystalline germanium-silicon alloy nanowires, correspondingly adopting amorphous silicon, amorphous germanium and amorphous germanium-silicon layers as precursors; and for other semiconductor materials, corresponding amorphous material films are adopted as precursors.
In one embodiment, further comprising step 7): the electrodes are prepared by photolithography and evaporation techniques.
In one embodiment, the method further comprises the following steps:
step 8) separating the nanowire from the substrate by etching the liquid;
and 9) transferring the detached spring nanowire array onto a flexible substrate, wherein the flexible substrate used can be any substrate with tensile property.
The substrate used for growth can be a P-type or N-type monocrystalline silicon substrate, and the surface of the substrate is provided with a silicon dioxide layer; the silicon chip can be a P-type or N-type polycrystalline silicon chip, and a silicon dioxide layer is arranged on the surface of the silicon chip; or an amorphous substrate such as ordinary glass or quartz glass.
Manufacturing a guide channel by a photoetching method; the etching method comprises the following steps of: alkaline corrosion systems such as potassium hydroxide (KOH) and sodium hydroxide (NaOH), acidic corrosion systems such as hydrofluoric acid + nitric acid (HF + HNO3) and hydrofluoric acid + nitric acid + acetic acid (HF + HNO3+ CH3COOH), and systems such as ethylenediamine pyrocatechol (ethylenediamine pyrocatechol); or dry etching, i.e. etching by ICP-RIE.
The metal electrode adopts a PT (12nm) -AL (80nm) system, can be a Ti-Au system, is Ni metal, and improves the contact performance by adopting a rapid thermal annealing process in metal contact. A thermal evaporation system, a magnetron sputtering system, or an electron beam evaporation system may be used.
And etching the surface of the substrate by using etching liquid to separate the spring structure crystal nanowire from the substrate, thereby conveniently finishing the transfer.
Spring structure crystalline nanowires are flexible high performance devices with high stretchability.
The invention has the advantages of
The invention adopts methods such as IP-SLS and the like to grow the nanowire guided by the channel step in PECVD and utilizes the modern micromachining technology to manufacture the spring structure crystal nanowire array. The IP-SLS method can grow planar nanowires, and a planar semiconductor single crystal nanowire array with high quality and a specific shape can be grown by combining a step channel guiding technology. The self-positioning and self-orientation of the growth of the nanowire can be realized through the guide channel formed by the photoetching technology and the positioned catalyst area. Since the cross section of the nano wire and the guide channel can be effectively adjusted, the nano wire can be further stripped (such as stripped by an etching method) and transferred onto other flexible substrates. Because the two ends of the nanowire array are connected with the electrodes, the integration and the use of devices can be conveniently carried out. The method for preparing the spring structure crystal nanowire has wide prospects in the field of flexible electronics and the application aspect of sensors.
The invention utilizes the characteristic that the planar nanowire can guide growth for the first time, and the results show the linear design of the ultra-flexible nanowire channel and the stretchable crystalline semiconductor nanowire structure. Taking crystalline silicon as an example, crystalline silicon itself is not stretchable and is also fragile, and crystalline silicon thin films cannot be directly applied to stretchable electronic device applications. By the technology, the existing mature crystalline silicon semiconductor technology can be expanded to the emerging flexible electronic application field, and a key technical basis is provided for greatly improving the device characteristics and stability of the flexible electronic device.
Drawings
FIG. 1 is a flow chart of a process for preparing a spring structure crystal nanowire;
FIG. 2 is a schematic diagram of a spring-structured crystal nanowire array design; in fig. 2, a schematic diagram of a design of a spring-structured crystal nanowire array, wherein blue (dark) regions are catalyst regions (a) (b) (c) (d) respectively representing four different spring-shaped curves;
FIG. 3 is an SEM topography of a spring structure crystal nanowire; in fig. 3, SEM topography of spring-structured crystalline nanowires (a) (b) (c) (d) shows four different ratios, respectively.
Fig. 4 is a diagram of the electrical properties of the spring structure crystalline silicon nanowire.
FIGS. 5(a) and (b) are in-situ SEM mechanical tensile and simultaneous electrical tests of an exemplary stretchable silicon nanowire, and FIG. 5(c) is a graph of the results of the simultaneous potential tests; fig. 5(d) and (e) SEM images of processes whereby the stretchable silicon nanowire was stretched to the elastic deformation limit of 270% and could be fully recovered.
Detailed Description
The present invention will be described in further detail with reference to specific examples in order to make the objects, technical solutions, effects, and advantages of the present invention more apparent.
As shown in fig. 2, the present invention provides a stretchable crystalline semiconductor nanowire having an elongated body. The stretchable crystalline semiconductor nanowire is of a bent structure and is provided with a plurality of stretchable units in the axial direction, and the stretchable units are sequentially connected, so that the stretchable crystalline semiconductor nanowire is formed.
Further, the diameter of the nanowire is 20-200 nanometers, and the nanowire is of a crystalline inorganic semiconductor structure.
As shown in fig. 2, the design of the crystal nanowire array is schematically illustrated, wherein the blue (dark) regions are the catalyst regions (a) (b) (c) (d) respectively representing four different spring-shaped curves; as can be seen from the figure, the nanowire has a bent structure and a plurality of connected stretchable units in the axial direction, and the stretchable units are one or more of circular arc, semicircular and hemiracetrack shapes.
Further, the stretchable unit of the stretchable crystalline semiconductor nanowire is in a circular arc shape, a semicircular shape, a half-track shape, and may also be in a Z-shape, a V-shape, an M-shape (not shown), or one or more combinations thereof.
Further, the length in the maximum stretched state is more than 1.5 times, preferably 2 times or more, and preferably 2.7 times the length in the natural state.
In one embodiment, crystalline nanowires are grown, which are single crystal nanowires of Si, SiGe, Ge, or GaAs, or the like.
The substrate used for growth can be a P-type or N-type monocrystalline silicon substrate, and the surface of the substrate is provided with a silicon dioxide layer; the silicon chip can be a P-type or N-type polycrystalline silicon chip, and a silicon dioxide layer is arranged on the surface of the silicon chip; or an amorphous substrate such as ordinary glass or quartz glass.
FIG. 3 is an SEM image of a spring-structured crystal nanowire, which is actually prepared, wherein (a) (b) the stretchable unit has a circular arc structure, and (c) (d) the stretchable unit has a hemiracetrack structure. (a) (b), (c) and (d) represent four different ratios, respectively.
Fig. 4 is an electrical property diagram of the prepared crystalline silicon nanowire with the spring structure.
As shown in fig. 5(a) (b) for example, in an in-situ sem, one of the silicon nanowires is mechanically stretched and subjected to simultaneous electrical testing under the operation of a mechanical probe. The test results are shown in fig. 5(c), which shows that the electrical properties are stable during the tensile elastic deformation of the silicon nanowires.
As shown in fig. 5(d) (e), the silicon nanowire can be mechanically stretched to the limit, the length of the silicon nanowire in the maximum stretching state is larger than 270% of the length of the silicon nanowire in the natural state, the silicon nanowire still keeps elastic deformation, and the silicon nanowire can restore the original shape after being released.
According to another aspect of the present invention, as shown in fig. 1, the present invention provides a method for preparing a stretchable crystalline semiconductor nanowire based on planar nanowire linear design and guidance, comprising the steps of:
1) the method comprises the following steps of (1) carrying out standardized cleaning on substrates such as glass, silicon dioxide sheets or silicon wafers and the like to remove organic matters and metal residues on the surfaces;
2) etching a step with a certain depth on the surface of the substrate by utilizing a photoetching technology (or a surface pattern etching technology), wherein the linear shape of the guide step can be freely and conveniently designed and defined; in order to realize a stretchable flexible crystalline semiconductor channel structure, a step line is linearly designed into a nonlinear bent spring or zigzag serpentine channel array, a spring-shaped guide channel array with the depth of about 150 +/-10 nm (no more than 350nm) and a fractal bent two-dimensional distribution structure which is communicated by a single line and is more relaxed in space are manufactured on a substrate by a photoetching technology;
3) precisely growing crystal nanowires with the diameters of about 120 +/-10 nm along the guide channel by a planar nanowire guide growth method to form a nanowire spring array; depositing a catalytic metal film block on one end of a guide channel by vapor deposition through a photoetching lift-off or mask plate technology to serve as an initial point for forming metal liquid drops and an initial position of a nanowire;
4) processing the metal film by utilizing reductive plasma such as hydrogen in a PECVD system, removing an oxide layer on the surface, and forming nano metal catalytic particles with the diameter between dozens of nanometers and one micron;
5) depositing and covering an amorphous semiconductor layer with a proper thickness as a precursor medium;
6) annealing (temperature above 250 ℃) in vacuum or non-oxidizing atmosphere to grow, so that the metal liquid drop starts to move along the guide step, absorbs the amorphous layer and deposits a crystalline nanowire structure along the way;
7) preparing electrodes at two ends of the nanowire spring array by photoetching and evaporation technology;
8) separating the nanowire spring from the substrate by etching liquid;
9) the separated spring nanowire array is transferred to a flexible substrate, so that the stretchable nanowire spring can be manufactured, and the method can be widely applied to the field of flexible electronics. The flexible nanowire springs or related structures can be transferred to a flexible stretchable polymer substrate (spin coating a thin film on the sample surface in conjunction with sacrificial layer etch transfer, and selective manipulation directly with the nanomachine).
Further, the substrate in step (1) may be a silicon wafer, glass, ceramic wafer, or polymer substrate resistant to high temperature up to 350 ℃. The silicon dioxide substrate is a common silicon dioxide substrate, and the thickness of the silicon dioxide substrate is larger than 250 nm. The silicon chip can also be a P-type or N-type monocrystalline or polycrystalline silicon chip with a surface covered with dielectric layers such as silicon dioxide or silicon nitride, the glass is common glass or quartz glass, and the polymer can be a flexible polymer which can bear certain high temperature (350 ℃) processing and is compatible with a vacuum environment.
Further, in step 3), the catalyst region is positioned on the position of the channel again by using the photoetching alignment technology, and the crystal nanowire with the diameter of about 130 +/-10 nm is precisely grown along the guide channel by a planar nanowire guide growth method to form the spring-shaped nanowire; in and Sn metal is evaporated, and a metal film pattern with the thickness of tens of nanometers is formed at a specific position of the guide channel; processing the metal film in a PECVD system by using a plasma processing technology at 350 ℃ and 2-5W to ensure that the metal film is shrunk into quasi-nano catalytic particles with the diameter of hundreds of nanometers to several micrometers; covering a layer of amorphous silicon (several nanometers to several hundred nanometers) with proper thickness by using a PECVD system as a precursor dielectric layer; and annealing in a 350 ℃ environment in a vacuum atmosphere, and growing the nanowire from the catalyst region along the guide channel by using an IP-SLS growth mode to form and obtain the nanowire with the spring structure.
Further, the catalytic metal in step (3) may be low melting point metals such as indium, tin, gallium, lead, bismuth, and their alloys and oxide materials, and noble metals such as gold, silver, copper, and the like, which are matched with the grown crystalline nanowire material.
Further, the step (2) is characterized by comprising the following steps: firstly, defining a guide step line shape of a planar nanowire on a photoresist layer by using a photoetching technology, and then etching the pattern downwards into a substrate by using a reactive plasma (RIE) or inductive plasma (ICP) etching technology, wherein the etching depth is in the range of several to hundreds of nanometers;
in one embodiment, the guide channel is manufactured by a photoetching method; the etching method comprises the following steps of: alkaline corrosion systems such as potassium hydroxide (KOH) and sodium hydroxide (NaOH), acidic corrosion systems such as hydrofluoric acid + nitric acid (HF + HNO3) and hydrofluoric acid + nitric acid + acetic acid (HF + HNO3+ CH3COOH), and systems such as ethylenediamine pyrocatechol (ethylenediamine pyrocatechol); or dry etching, i.e. etching by ICP-RIE.
In one embodiment, a spring-shaped crystal nanowire is grown, and the nanowire is made of crystal materials such as Si, Ge, SiGe and GaAs. The diameter of the crystal nanowire is 20-180nm by using any shape structure with tensile property.
Further, the characteristic step in the step (3) comprises: by utilizing photoetching or mask plate technology, a metal catalyst layer is adopted to evaporate and plate a catalytic metal layer film of indium, tin and the like through processes of thermal evaporation, magnetron sputtering, electron beam sputtering, pulse laser sputtering, atomic layer deposition and the like, so that a metal film area of a few microns is formed and is crossed with a guide step at a specific initial position of a guide channel.
Further, step (4) comprises: processing at 200-450 deg.C and power of 0.2-100W in PECVD system by plasma processing technique to make metal film spherical into nanometer catalytic particles with diameter of tens of nanometers to several micrometers;
further, the step (5) is characterized by comprising the following steps: and covering an amorphous semiconductor layer with proper thickness (several nanometers to several hundred nanometers) by using a PECVD system as a precursor dielectric layer. For growing crystalline silicon, crystalline germanium or crystalline germanium-silicon alloy nanowires, amorphous silicon, amorphous germanium and amorphous germanium-silicon layers are correspondingly adopted as precursors. And for other semiconductor materials, corresponding amorphous material films are adopted as precursors.
Further, in step (6): the growth temperature of the planar nanowires is chosen between 300 ℃ and 600 ℃ for different semiconductor materials. The nanowire growth process may be performed under inert gas, reducing gas, or vacuum conditions.
Further, in step (7): the linear shape of the grown planar nanowire is controlled by the edge of the guide step, a programmable non-linear bending spring or zigzag serpentine channel and a fractal bending two-dimensional distribution structure communicated by a single line can be obtained, and therefore the stretchable crystalline silicon semiconductor nanowire channel is realized.
In yet another embodiment, a method of fabricating a stretchable electronic device of crystalline semiconductors (including silicon, germanium, etc.) is implemented based on a linear design of planar nanowires and guided growth techniques. The method comprises the steps of manufacturing a guide step with a specific shape on a glass or crystalline silicon substrate by utilizing a conventional photoetching and etching technology or other template and surface processing technologies, taking an amorphous film (amorphous silicon, amorphous germanium and other amorphous inorganic semiconductor materials) as a precursor, absorbing the amorphous film by utilizing metal (indium, tin, gallium, bismuth and the like) catalytic particles, and growing a corresponding planar crystalline state (simple substance or alloy) nanowire structure in the process of moving along the guide step. As the guide steps can be freely programmed, a line-shape completely controllable and regular crystalline nanowire array can be customized, and a crystalline semiconductor nanowire structure with super stretchability is prepared. The technology can realize crystalline semiconductor material nanometer channels such as crystalline silicon and the like with high stretchability, and maintain excellent electrical modulatable and device stable characteristics of the crystalline semiconductor material, so that high-performance flexible semiconductor electronic applications (such as stretchable logic transistors, display control and driving devices, sensing, artificial skin and other emerging fields) can be realized.
In particular to a technique for growing and transferring a crystal nanowire with a spring structure. The method is a directional growth and transfer method under a specific channel, and comprises the following steps:
1) and (3) treating the crystal substrate covered with the oxide layer by using an acid-base hot solution or acetone, alcohol and deionized water ultrasonic treatment respectively to remove impurities attached to the surface and expose the clean surface of the crystal.
2) The spring structure guided growth channel array is defined using photolithographic etching techniques, again using photolithographic alignment techniques to define catalyst regions at specific locations of the channels. Forming a guide step with a certain depth by using a photolithography technique (or a surface pattern etching technique);
3) depositing a catalytic metal film block at one end of the guide channel by vapor deposition through a photoetching lift-off or mask plate technology; in and Sn metal is evaporated, and a metal film pattern with the thickness of tens of nanometers is formed only at a specific position of the guide channel through liftoff;
4) processing the metal film in a PECVD system by using a plasma processing technology at 350 ℃ and 2-5W to ensure that the metal film is shrunk into quasi-nano catalytic particles with the diameter of hundreds of nanometers to several micrometers;
5) and covering a layer of amorphous silicon (a few nanometers to a few hundred nanometers) with proper thickness by using a PECVD system as a precursor dielectric layer.
6) Annealing (temperature above 280 ℃) and growing in vacuum or non-oxidizing atmosphere to enable the metal liquid drop to start to move along the guide step, absorbing the amorphous layer and depositing a crystalline nanowire structure along the way; and particularly annealing in a 350 ℃ environment under a vacuum atmosphere, and growing the nanowire from the catalyst region along the specific guide channel by using an IP-SLS growth mode to form and obtain the spring-shaped nanowire.
7) And then, the photoetching alignment technology and the metal evaporation technology are utilized again, and electrodes are arranged at the two ends of the nanowire spring array.
8) And etching the surface of the sample by using HF to separate the nanowire from the substrate.
9) The array of nanowire springs detached from the substrate is transferred to a flexible substrate. The flexible nanowire springs or related structures can be transferred to a flexible stretchable polymer substrate (spin coating a thin film on the sample surface in conjunction with sacrificial layer etch transfer, and selective manipulation directly with the nanomachine).
Further, a guiding channel with a depth of about 200nm and a guiding channel of a spring structure (see fig. 1) are manufactured by photolithography and etching, wherein the spring structure can be any bending form with a stretchable property, and the distance between nodes can be 200nm to 50 um. The etching method of the channel can be wet etching: alkaline systems such as potassium hydroxide (KOH) and sodium hydroxide (NaOH), acidic systems such as hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3+ CH3COOH), and systems such as ethylenediamine pyrocatechol (ethylenediamine pyrocatechol); it may be a dry etching system, and etching is performed by ICP-RIE.
Further, the etching liquid used in the transfer step may be any liquid that can etch silicon dioxide while slowly or not etching the crystalline nanowires. The flexible substrate used for transfer may be any substrate having tensile properties.
Furthermore, the nanowires grown in the plane can be planar single crystal nanowire arrays of Si, SiGe, Ge, GaAs and the like, and the diameters of the nanowires are distributed between 20 nm and 200 nm.
Furthermore, the metal electrode is manufactured by utilizing the photoetching evaporation technology, a thermal evaporation system, an electron beam evaporation system, a magnetron sputtering system and the like can be used, a PT (12nm) -AL (80nm) system, a Ti-Au system or a Ni metal can be used for contacting the metal electrode, and the contact performance is improved by using a rapid thermal annealing process for contacting the metal electrode.
A more specific real-time example: 300nmSiO2The preparation method of the spring structure crystal nanowire on the oxide layer substrate comprises the following steps:
1) a300 nmSiO2 oxide layer substrate (a silicon wafer with an oxidized surface) is adopted, and acetone, alcohol and deionized water are respectively used for ultrasonic treatment to remove impurities attached to the surface of the substrate. The silicon wafer can be a pure monocrystalline or polycrystalline silicon wafer.
2) Defining a spring structure pattern on the surface of a substrate by using a mask photoetching technology, forming a channel on the surface by using ICP-RIE etching, and forming an array of biological probe channels after cleaning photoresist.
3) In a PECVD system, forming nano-catalytic particles with the diameter of between hundreds of nanometers and a plurality of micrometers by using a plasma treatment technology under the power of 1-50W; nano-catalytic particles with a diameter of a few hundred nanometers are formed at a temperature of 350 c.
4) Continuously covering a layer of amorphous silicon layer with proper thickness in the PECVD system as a precursor dielectric layer; covering an amorphous silicon layer with proper thickness at 300-400 deg.C. Annealing in vacuum or in non-oxidizing atmosphere such as hydrogen, nitrogen and the like at 400 ℃, and the catalytic liquid drops can absorb the surrounding amorphous silicon after being activated, so that planar silicon nanowires can be induced to grow, and the nanowires can directionally grow along the side wall of the guide channel to form the required channel.
5) And treating the residual amorphous silicon on the surface by using plasma in a hydrogen atmosphere for 15 minutes until the surface color recovers to normal color.
6) The electrode pattern was defined again using photolithography, 12nm titanium and 60nm gold were evaporated using electron beam evaporation techniques, and the photoresist and residual metal were then rinsed off.
7) And (3) spin-coating PMMA on the surface of the substrate, and etching the substrate by using an HF solution with the concentration of 4% to enable the PMMA film to carry the crystalline nanowire spring array to be separated from the substrate.
8) The PMMA film separated from the substrate and the spring structure crystal nano-wires on the PMMA film are fished up by using the PDMS film, and then the PMMA film is dissolved by using a solvent, so that the spring structure crystal nano-wires are transferred to the flexible substrate PDMS.
As described above, the present invention can be preferably realized. It will be appreciated by those skilled in the art that changes, modifications, substitutions, integrations and variations may be made in these embodiments without departing from the principles and spirit of the invention, which falls within the scope of the invention. The present invention is not limited to the specific embodiments described above, and can be practiced by any conventional technique.

Claims (8)

1. A stretchable crystalline semiconductor nanowire characterized by: the nanowire has an elongated body, the nanowire having a diameter between 20-200 nanometers;
the nano wire is a regular crystalline state inorganic semiconductor structure which is formed by precisely and directionally growing along the side wall of a guide channel etched on the substrate;
the nanowire is of a bent structure and is provided with a plurality of stretchable units in the axial direction, and the stretchable units are sequentially connected to form a stretchable crystalline semiconductor nanowire;
the stretchable unit is one or a combination of more than one of an arc shape, a semicircular shape, a half-track shape, a Z shape, a V shape and an M shape;
the length of the nanowire in the maximum stretching state is more than 2 times of the length of the nanowire in the natural state.
2. A stretchable crystalline semiconductor nanowire according to claim 1, wherein: the length of the nanowire in the maximum tensile state is 2.7 times of the length of the nanowire in the natural state.
3. A stretchable crystalline semiconductor nanowire according to any of claims 1-2, wherein: the nanowires are Si, SiGe, Ge or GaAs single crystal nanowires.
4. A stretchable crystalline semiconductor nanowire according to claim 1, characterized in that it is prepared by a method comprising the steps of:
1) removing residues on the surface of a substrate by adopting a substrate comprising polymer, glass, a silicon dioxide sheet or a silicon wafer;
2) etching a step with a certain depth on the surface of the substrate, and further etching along the step to manufacture a specific guide channel;
3) by a planar nanowire guiding growth method, the crystal nanowire can accurately grow along the guiding channel, and a catalytic metal film is deposited at one end of the guiding channel by evaporation and serves as a forming initial point of a metal liquid drop and an initial position of the nanowire;
4) processing the metal film by utilizing reductive plasma comprising hydrogen in a PECVD system, removing an oxide layer on the surface, and forming nano metal catalytic particles with the diameter between dozens of nanometers and one micron;
5) depositing and covering an amorphous semiconductor layer with a proper thickness as a precursor medium;
6) annealing growth is carried out in vacuum or non-oxidizing atmosphere, the temperature is above 250 ℃, so that the metal liquid drop starts to move along the guide step, the amorphous layer is absorbed, and the crystalline nanowire structure is deposited along the way.
5. A stretchable crystalline semiconductor nanowire according to claim 4, wherein in step 1) of the preparation method, the silicon wafer is a P-type or N-type monocrystalline or polycrystalline silicon wafer with a silicon dioxide or silicon nitride dielectric layer covered on the surface, the glass is common glass or quartz glass, and the polymer is a flexible polymer which can bear high temperature treatment of more than 350 ℃ and is compatible with a vacuum environment; the thickness of the silicon dioxide substrate is more than 250 nm.
6. Stretchable crystalline semiconductor nanowires according to claim 4, characterized in that step 5) of the preparation method comprises: covering an amorphous semiconductor layer with a proper thickness by using the PECVD system as a precursor dielectric layer; for growing crystalline silicon, crystalline germanium or crystalline germanium-silicon alloy nanowires, correspondingly adopting amorphous silicon, amorphous germanium and amorphous germanium-silicon layers as precursors; and for other semiconductor materials, corresponding amorphous material films are adopted as precursors.
7. A stretchable crystalline semiconductor nanowire according to claim 4, wherein the method of making further comprises step 7): the electrodes are prepared by photolithography and evaporation techniques.
8. A stretchable crystalline semiconductor nanowire according to claim 7, wherein the method of making further comprises the steps of: step 8) separating the nanowire from the substrate by etching the liquid; step 9) transferring the detached nanowires onto a flexible substrate, wherein the flexible substrate used can be any substrate with tensile properties.
CN201810614845.8A 2017-06-15 2018-06-14 Stretchable crystal semiconductor nanowire and preparation method thereof Active CN109234807B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP18817489.0A EP3640374A4 (en) 2017-06-15 2018-06-15 Stretchable crystalline semiconductor nanowire and preparation method thereof
PCT/CN2018/091544 WO2018228543A1 (en) 2017-06-15 2018-06-15 Stretchable crystalline semiconductor nanowire and preparation method thereof
US16/714,724 US20200118818A1 (en) 2017-06-15 2019-12-14 Stretchable crystalline semiconductor nanowire and preparation method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710450420.3A CN107460542A (en) 2017-06-15 2017-06-15 A kind of preparation method of the stretchable crystalline semiconductor nano wire based on plane nano line Alignment Design and guiding
CN2017104504203 2017-06-15

Publications (2)

Publication Number Publication Date
CN109234807A CN109234807A (en) 2019-01-18
CN109234807B true CN109234807B (en) 2020-09-01

Family

ID=60543809

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201710450420.3A Pending CN107460542A (en) 2017-06-15 2017-06-15 A kind of preparation method of the stretchable crystalline semiconductor nano wire based on plane nano line Alignment Design and guiding
CN201810614845.8A Active CN109234807B (en) 2017-06-15 2018-06-14 Stretchable crystal semiconductor nanowire and preparation method thereof

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201710450420.3A Pending CN107460542A (en) 2017-06-15 2017-06-15 A kind of preparation method of the stretchable crystalline semiconductor nano wire based on plane nano line Alignment Design and guiding

Country Status (3)

Country Link
US (1) US20200118818A1 (en)
EP (1) EP3640374A4 (en)
CN (2) CN107460542A (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018228543A1 (en) 2017-06-15 2018-12-20 南京大学 Stretchable crystalline semiconductor nanowire and preparation method thereof
CN109650330A (en) * 2018-05-31 2019-04-19 南京大学 It is the preparation method that template realizes large-area graphene nano-band array based on programmable nano wire
CN108920000A (en) * 2018-06-30 2018-11-30 昆山国显光电有限公司 Display panel and preparation method thereof
CN109280903B (en) * 2018-10-24 2020-10-20 中国科学院上海微系统与信息技术研究所 Preparation method of high-density germanium nanowire
CN109876297B (en) * 2019-03-06 2021-04-30 南京大学 Implantable photoelectric cardiac pacemaker and preparation method thereof
CN109850843B (en) * 2019-03-14 2021-01-15 南京大学 Batch preparation method of suspended nanowire manipulator
CN109950393B (en) * 2019-03-14 2021-09-10 南京大学 Preparation method of nanowire cross point array resistive random access memory device structure capable of being prepared in stacked large area
CN109911847A (en) * 2019-03-14 2019-06-21 南京大学 A method of it is discharged by transfer and obtains high density nanowire arrays
CN111724676B (en) * 2019-03-21 2022-09-02 昆山工研院新型平板显示技术中心有限公司 Stretchable wire, manufacturing method thereof and display device
CN111916338B (en) * 2019-05-08 2023-07-25 京东方科技集团股份有限公司 Silicon-based nanowire, preparation method thereof and thin film transistor
CN110544656B (en) * 2019-09-19 2021-10-26 南京大学 Method for realizing huge transfer of Micro-LED (Micro-light-emitting diode) by using super-stretchable crystalline nanowire
CN110767537B (en) * 2019-11-05 2022-06-21 南京大学 Method for preparing three-dimensional super-stretchable crystalline nanowire
EP3839644A1 (en) * 2019-12-20 2021-06-23 Nivarox-FAR S.A. Flexible timepiece component, in particular for oscillator mechanism, and clockwork comprising such a component
CN111704101A (en) * 2020-05-13 2020-09-25 中国科学院微电子研究所 Flexible sensor and preparation method thereof
CN111693444B (en) * 2020-06-24 2021-09-28 南京大学 Spring nanowire detector for cell mechanics detection and detection method thereof
CN113247860B (en) * 2020-06-24 2022-06-21 南京大学 Preparation method of embedded cross-surface growth three-dimensional nanowire spiral structure
CN111785635A (en) * 2020-07-16 2020-10-16 京东方科技集团股份有限公司 Thin film transistor, manufacturing method thereof, array substrate and display device
CN111952322B (en) * 2020-08-14 2022-06-03 电子科技大学 Flexible semiconductor film with periodically adjustable buckling structure and preparation method thereof
CN112730945B (en) * 2020-12-21 2023-05-09 上海交通大学 Flexible MEMS flow velocity sensor based on self-heating amorphous germanium thermal resistor
CN114113186B (en) * 2021-11-15 2024-05-10 哈工大机器人创新中心有限公司 Controllable bending method for nanowires

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100443893C (en) * 2005-12-29 2008-12-17 上海交通大学 Manufacturing method of microgas sensor based on one-dimension manometer material
KR101533455B1 (en) * 2006-04-06 2015-07-03 삼성전자주식회사 Nanowire composite and preparation method therof
CN101475206B (en) * 2009-01-13 2010-06-02 东华大学 Method for preparing ZnO nanorod with controllable distribution by growing in microchannel
CN105177706A (en) * 2015-08-17 2015-12-23 南京大学 Method for preparing high-quality flexible monocrystal silicon nanowire
CN105239156A (en) * 2015-09-15 2016-01-13 南京大学 Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration
CN106645357B (en) * 2016-10-17 2019-06-28 南京大学 A kind of preparation method of crystalline nanowire bioprobe device

Also Published As

Publication number Publication date
EP3640374A4 (en) 2020-07-22
EP3640374A1 (en) 2020-04-22
US20200118818A1 (en) 2020-04-16
CN109234807A (en) 2019-01-18
CN107460542A (en) 2017-12-12

Similar Documents

Publication Publication Date Title
CN109234807B (en) Stretchable crystal semiconductor nanowire and preparation method thereof
CN101567230B (en) Preparation method of transparent conductive thin film
US8683611B2 (en) High resolution AFM tips containing an aluminum-doped semiconductor nanowire
US20110215441A1 (en) Silicon nanostructures and method for producing the same and application thereof
TW201105571A (en) Method for fabricating hollow nanotube structure
WO2019180267A1 (en) Method and substrate for patterned growth on nanoscale structures
CN110767537B (en) Method for preparing three-dimensional super-stretchable crystalline nanowire
CN107086180A (en) A kind of single nano-wire multichannel is multiplexed the preparation method of film transistor device
CN109650330A (en) It is the preparation method that template realizes large-area graphene nano-band array based on programmable nano wire
CN103378236A (en) Epitaxy structural body with microstructure
CN105161617A (en) Resistive random access memory with planar structure and manufacturing method thereof
CN106645357B (en) A kind of preparation method of crystalline nanowire bioprobe device
US20140030873A1 (en) Method for fabricating patterned silicon nanowire array and silicon microstructure
CN109850843B (en) Batch preparation method of suspended nanowire manipulator
KR20070050333A (en) Method for producing nanowire using porous glass template and method for producing multi-probe
CN105223421A (en) The huge piezoresistive characteristic measurement mechanism of nano wire and manufacture method thereof
CN110752157A (en) Preparation method of semiconductor field effect transistor device with three-dimensional suspended ring gate structure and product thereof
CN111446363B (en) Self-supporting three-dimensional self-assembly magnetoelectric composite film structure and preparation method thereof
US9691849B2 (en) Ultra-long silicon nanostructures, and methods of forming and transferring the same
WO2018228543A1 (en) Stretchable crystalline semiconductor nanowire and preparation method thereof
US10147789B2 (en) Process for fabricating vertically-aligned gallium arsenide semiconductor nanowire array of large area
CN111180392A (en) Method for obtaining large-size monocrystalline silicon nano-film on basis of silicon on insulator in large batch
KR20070104034A (en) Method of manufacturing tips for field emission, tips for field emission manufactured by the same, and device comprising the same
CN109911847A (en) A method of it is discharged by transfer and obtains high density nanowire arrays
Suma et al. Effect of Process Duration on ZnO Nanowire Growth & Application for Pressure Sensing

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant