CN110767537B - Method for preparing three-dimensional super-stretchable crystalline nanowire - Google Patents
Method for preparing three-dimensional super-stretchable crystalline nanowire Download PDFInfo
- Publication number
- CN110767537B CN110767537B CN201911071316.9A CN201911071316A CN110767537B CN 110767537 B CN110767537 B CN 110767537B CN 201911071316 A CN201911071316 A CN 201911071316A CN 110767537 B CN110767537 B CN 110767537B
- Authority
- CN
- China
- Prior art keywords
- layer
- nanowire
- etching
- catalytic metal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
Abstract
A method for preparing three-dimensional super-stretchable crystalline nanowires comprises the steps of 1) depositing an insulating medium layer on a substrate by PECVD or PVD to serve as a sacrificial layer, 2) defining periodic step edge patterns by photoetching and electron beam direct writing, and etching the medium layer by using a dry method or wet method alternative etching process to form vertical step side walls; 3) treating the surface of the step with corrosive liquid to form a wavy step; 4) defining patterns vertical to the steps by using a photoetching electron beam direct writing or mask plate technology and preparing a secondary guide channel vertical to the steps by using an etching technology; 5) a band-shaped catalytic metal layer is locally deposited by photoetching, evaporation or sputtering; 6) converting the catalytic metal layer into isolated metal nanoparticles; 7) reducing the temperature below the melting point of the catalytic metal particles, and depositing and covering an amorphous semiconductor precursor film layer on the surface of the whole structure; depositing a crystalline nanowire; the nanowire will grow along the guiding channel of the undulating step.
Description
Technical Field
The invention relates to a method for obtaining a super-tensile crystalline nanowire (nanowire) by utilizing a channel guide technology, in particular to a method for forming a large-area and easily-positioned wavy guide channel by utilizing two etching processes.
Background
Semiconductor crystal silicon Nanowire (Nanowire) is a core material of modern microelectronics technology due to its advantages of high carrier mobility, high efficiency, stability and reliability of doping process, and the inventor of the present application firstly proposes a planar solid-liquid-solid (IP SLS) growth mode: amorphous silicon is used as a precursor, and the crystalline silicon nanowire structure grows by absorbing the amorphous silicon by low-melting-point metal indium and tin nanoparticles. Meanwhile, a three-dimensional nanometer step can be prepared by utilizing the twice etching technology, and the step is used as a guide, and the metal liquid drop moves along the step edge under the attraction of amorphous silicon covered at the step edge, so that the nanowire grows at the step edge, and the ultra-stretchable crystalline silicon nanowire array is realized.
However, the natural rigidity of many materials severely limits the emerging new flexible and stretchable electronic devices, and it is important to control the morphology of crystalline nanowires to have super-stretchability. Because the planar crystalline nanowire is greatly restrained by the substrate, the relaxable space is reduced, and the nanowire is very easy to be broken in the stretching process, so that a reliable flexible electronic device is difficult to prepare.
The applicant group has proposed several techniques by which nanowires will grow along three-dimensional steps. Such as CN 2018100068322.
The invention content is as follows:
the invention aims to: the invention provides a method for preparing a three-dimensional super-stretchable (namely a nanowire with a wavy or arc-shaped bent shape or structure) crystalline nanowire.
The technical scheme of the invention is as follows: a method of preparing three-dimensional super-stretchable crystalline nanowires comprising the steps of:
1) depositing an insulating dielectric layer on the substrate by using a PECVD (plasma enhanced chemical vapor deposition) or PVD (physical vapor deposition) process to be used as a sacrificial layer (about 4 +/-2 mu m);
2) defining periodic step edge patterns by utilizing photoetching, electron beam direct writing or mask plate technology, and etching the dielectric layer by utilizing a dry method or wet method alternative etching process to form a vertical step side wall (the step height is about 1 +/-0.5 mu m);
3) the step surface is processed by corrosive liquid, and as the content of silicon oxide at the sharp corner of the channel is minimum, the liquid corrosion rate is faster than that of the rest area, so that the vertical channel can be smoothly etched to form a wave-shaped step;
4) taking the wavy step formed in the previous step as a substrate, defining a pattern vertical to the step by using a photoetching electron beam direct writing or mask plate technology, and preparing a secondary guide channel vertical to the step by using an etching technology;
5) partially depositing a layer of banded catalytic metal layer on one end of the secondary guide channel on the prepared step through photoetching, evaporation or sputtering technology;
6) raising the temperature to be above the melting point of the catalytic metal, and introducing reducing gas plasma for treatment to convert the catalytic metal layer into separated metal nano particles;
7) reducing the temperature below the melting point of the catalytic metal particles, and depositing and covering an amorphous semiconductor precursor film layer on the surface of the whole structure; then raising the temperature to a proper temperature to ensure that the nano metal particles are re-melted, and the nano metal particles start to absorb an amorphous layer at the front end and deposit a crystalline nano wire at the rear end; due to the guiding effect of the three-dimensional steps, the nanowire grows along the guiding channel of the wave step;
8) removing the residual amorphous semiconductor precursor by etching processes such as hydrogen plasma, ICP (inductively coupled plasma) or RIE (reactive ion etching); obtaining the wavelike nano-wire.
9) Spin-coating a layer of film with certain viscosity on the surface of the wavy nanowire, and adhering and protecting the wavy nanowire; etching the sacrificial layer by corrosive liquid to separate the silicon nanowire from the substrate;
10) the silicon nano wire separated from the substrate is transferred to the flexible substrate, and the film is dissolved by using solution, so that the super-stretchable flexible silicon nano spring (wave-shaped nano wire) can be obtained, and the super-stretchable flexible silicon nano spring can be widely applied to the field of flexible electronics.
The substrate material in the step 1) is crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, polyimide or poly terephthalic acid (polymer-like material).
The corrosive liquid in the step 3) is an alkaline corrosion system such as potassium hydroxide (KOH), sodium hydroxide (NaOH) and the like, hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO)3+CH3COOH), etc., and systems such as ethylenediamine Pyrocatechol (Ethylene Diamine Pyrocatechol), etc.
The catalytic metal In the step 5) can be In, Sn, Bi, Ga and other metals and metal alloys).
The precursor layer in the step 7) is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or other amorphous alloy layers, and a heterogeneous laminated layer (such as a-Ge/a-Si) structure.
The invention prepares a special guide channel by two times of photoetching and utilizes a nanowire growth method of plane solid-liquid-solid (IPSLS) to prepare a super-stretchable three-dimensional crystalline nanowire spring (wave) structure, realizes array by a programming guide technology (as long as the peak-valley period of the wave and the interval of the spring wire are set by a pattern), and finally transfers the nanowire to a flexible substrate by a high molecular polymer (such as PMMA, SU8 and the like) auxiliary transfer technology. The invention is expected to break through the key technical bottleneck which limits the stretchable electronic application for a long time, and develop the high-performance flexible crystalline nanowire stretchable device.
Has the advantages that: 1) preparing a three-dimensional wave-shaped guide channel by adopting a modern micromachining technology, and growing a channel-guided crystalline nanowire with super-stretchability in PECVD (plasma enhanced chemical vapor deposition) by using methods such as IP-SLS (Internet protocol-Selective laser deposition) and the like; 2) the self-positioning and self-orientation of the growth of the nanowire can be realized through a guide channel and a positioned catalyst area which are formed by a photoetching technology; 3) after the three-dimensional stretchable nanowire is transferred to the flexible substrate, the flexible nanowire is relatively less constrained by the substrate, and has more relaxation space, so that the stretchability can be better improved. Therefore, the method for preparing the three-dimensional elastic crystalline nanowire can be widely applied to the fields of flexible electronics, sensors and the like.
Drawings
Fig. 1 is a flow chart illustrating a process for preparing a nanowire electrically connected to a high-density slope step. In the figure a-f refer to the flow. Depositing a sacrificial layer (about 4 mu m) on a substrate a in a graph 1, defining a guide pattern through photoetching, etching a straight channel (about 1 mu m) by ICP (inductively coupled plasma), processing a wave-shaped guide channel through corrosive liquid, photoetching again and ICP again in the graph 1 b, depositing a strip-shaped catalytic metal layer at one end of a step c in the graph 1, processing the catalytic metal layer by d hydrogen plasma in the graph 1 to form metal liquid drops, covering an amorphous precursor layer, etching amorphous silicon after growing a nanowire, spin-coating a PMMA film on the nanowire in the graph 1 e, etching the substrate by HF with the concentration of 4% in the graph 1 f, enabling the PMMA film to be separated from the substrate with the mesh spring structure crystal nanowire, fishing up the separated PMMA film by using PDMS, and dissolving the PMMA film by organic reagents such as acetone and the like.
FIG. 2 is a SEM diagram of an etched guide channel provided by the present invention. The left and right figures in fig. 2 correspond to different magnifications. With wave-shaped guide channels.
Fig. 3 is a SEM schematic diagram after nanowire growth provided by the present invention.
Fig. 4 is a larger scale view similar to fig. 3.
Detailed Description
In order to make the technical solution and advantages of the present invention more apparent, the present invention is further described below with reference to specific embodiments, and the flowchart is shown in fig. 1.
The method comprises the following steps: 1) using a silicon wafer, glass, aluminum foil, compound (such as silicon nitride, silicon oxide, silicon oxynitride), polymer or other metal material as a substrate, and depositing an insulating dielectric layer (about 4 μm) on the substrate by using a PECVD or PVD process; 2) defining a pattern of a step edge by utilizing photoetching, electron beam direct writing or mask plate technology, and etching a dielectric layer by utilizing an Inductively Coupled Plasma (ICP) etching or reactive plasma etching (RIE) process to form a vertical step side wall (about 1 mu m in depth); etching a step structure by using an ICP (inductively coupled plasma) or RIE (reactive ion etching) alternative cycle etching method; using C first in the etching process4F8、CF4、SF6Or mixed gas thereof, or other reactive gases having different steep characteristics and surface passivation characteristics, and alternately and cyclically using the above-mentioned C4F8、CF4、SF6Different etching atmospheres; reuse includes O2、Cl2Etching the mask layer by using reaction gas with different etching rates in the transverse direction and the longitudinal direction, and alternately and circularly etching until the mask layer is etched to form a step; 3) the step surface is processed by corrosive liquid, and as the content of silicon oxide at the sharp corner of the channel is minimum, the liquid corrosion rate is higher than that of the rest area, so that the vertical channel can be smoothly etched to form the wave-shaped step. 4) Taking the wave-shaped step formed in the previous step as a substrate, and preparing a secondary guide channel (larger than 1 mu m) by photoetching and etching technology; 5) at one end of the prepared step, by photoetching, evaporation or sputtering processPartially depositing a belt-shaped catalytic metal layer (metals such as In, Sn, Bi, Ga and the like); 6) raising the temperature to be above the melting point of the catalytic metal in PECVD, and introducing reducing gas plasma for treatment to convert the catalytic metal layer into separated metal nano-particles; 7) reducing the temperature to below the melting point of the catalytic metal particles by using a PECVD system, and depositing and covering an amorphous semiconductor precursor film layer corresponding to the nanowire to be grown on the surface of the whole structure; then raising the temperature to a proper temperature to ensure that the nano metal particles are re-melted, and the nano metal particles start to absorb an amorphous layer at the front end and deposit a crystalline nano wire at the rear end; due to the guiding effect of the three-dimensional steps, the nanowires will grow along the steps; 8) the residual amorphous semiconductor precursor can be removed by etching processes such as hydrogen plasma, ICP or RIE; 9) spin-coating a thin film with certain viscosity, and etching the sacrificial layer by corrosive liquid to enable the silicon nanowire to be separated from the substrate; 10) and transferring the separated silicon nano wire to a flexible substrate, and dissolving the film by using a solution to obtain the ultra-stretchable flexible silicon nano spring, which can be widely applied to the field of flexible electronics.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A method for preparing three-dimensional super-stretchable crystalline nanowires is characterized by comprising the following steps:
1) depositing an insulating medium layer as a sacrificial layer on the substrate by utilizing a PECVD (plasma enhanced chemical vapor deposition) or PVD (physical vapor deposition) process, wherein the thickness of the insulating medium layer is 4 +/-2 mu m;
2) defining periodic step edge patterns by utilizing photoetching, electron beam direct writing or mask plate technology, and etching the dielectric layer by utilizing a dry method or wet method alternative etching process to form a vertical step side wall, wherein the step height is 1 +/-0.5 mu m;
3) the step surface is processed by corrosive liquid, and as the content of silicon oxide at the sharp corner of the channel is minimum, the liquid corrosion rate is faster than that of the rest area, so that the vertical channel can be smoothly etched to form a wave-shaped step;
4) taking the wavy step formed in the previous step as a substrate, defining a pattern vertical to the step by using a photoetching electron beam direct writing or mask plate technology, and preparing a secondary guide channel vertical to the step by using an etching technology;
5) partially depositing a layer of banded catalytic metal layer on one end of the secondary guide channel on the prepared step through photoetching, evaporation or sputtering technology;
6) raising the temperature to be above the melting point of the catalytic metal, and introducing reducing gas plasma for treatment to convert the catalytic metal layer into separated metal nano particles;
7) reducing the temperature below the melting point of the catalytic metal particles, and depositing and covering an amorphous semiconductor precursor film layer on the surface of the whole structure; then raising the temperature to a proper temperature to ensure that the nano metal particles are re-melted, and the nano metal particles start to absorb an amorphous layer at the front end and deposit a crystalline nano wire at the rear end; due to the guiding effect of the three-dimensional steps, the nanowire grows along the guiding channel of the wave step;
8) removing the residual amorphous semiconductor precursor by hydrogen plasma, ICP or RIE etching process; namely preparing the three-dimensional super-stretchable crystalline nanowire.
2. The method as claimed in claim 1, wherein the three-dimensional super-stretchable crystalline nanowires are wavy nanowires, and a thin film with certain viscosity is spin-coated on the surface of the wavy nanowires to adhere and protect the wavy nanowires; etching the sacrificial layer by corrosive liquid to separate the wavelike nano wire from the substrate; and transferring the wavy nanowire separated from the substrate to a flexible substrate, and dissolving the film by using a solution to obtain the super-stretchable wavy nanowire.
3. The method as claimed in claim 1 or 2, wherein the substrate material in step 1) is crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, or a polymer material including polyimide or poly (terephthalic acid).
4. The method as claimed in claim 1 or 2, wherein 3) the alkaline etching system of potassium hydroxide (KOH) and sodium hydroxide (NaOH), hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO)3+CH3COOH) acid corrosion system or Ethylene Diamine Pyrocatechol (Ethylene Diamine Pyrocatechol) system to form a wave-shaped step.
5. A method according to claim 1 or 2, characterized In that In 5) at one end of the secondary guiding channel on the step a layer of a strip-like catalytic metal comprising In, Sn, Bi, Ga metals and metal alloys is deposited by means of a photolithographic, evaporation or sputtering process.
6. The method as claimed in claim 1 or 2, wherein the amorphous semiconductor precursor thin film layer in 7) is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or a hetero-stack structure including a-Ge/a-Si.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911071316.9A CN110767537B (en) | 2019-11-05 | 2019-11-05 | Method for preparing three-dimensional super-stretchable crystalline nanowire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911071316.9A CN110767537B (en) | 2019-11-05 | 2019-11-05 | Method for preparing three-dimensional super-stretchable crystalline nanowire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110767537A CN110767537A (en) | 2020-02-07 |
| CN110767537B true CN110767537B (en) | 2022-06-21 |
Family
ID=69336178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911071316.9A Active CN110767537B (en) | 2019-11-05 | 2019-11-05 | Method for preparing three-dimensional super-stretchable crystalline nanowire |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110767537B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111439722B (en) * | 2020-04-02 | 2021-06-15 | 南京大学 | Micro-bolometer and preparation method thereof |
| CN113247860B (en) * | 2020-06-24 | 2022-06-21 | 南京大学 | Preparation method of embedded cross-surface growth three-dimensional nanowire spiral structure |
| CN112599418B (en) * | 2020-12-14 | 2022-04-22 | 南京大学 | Preparation method of three-dimensional broken line nanowire array vertical field effect transistor |
| CN112645280A (en) * | 2020-12-30 | 2021-04-13 | 深圳清华大学研究院 | Processing technology of radio frequency switch |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9035408B2 (en) * | 2013-05-06 | 2015-05-19 | The United States Of America, As Represented By The Secretary Of The Navy | Nanometer-scale level structures and fabrication method for digital etching of nanometer-scale level structures |
| CN105177706A (en) * | 2015-08-17 | 2015-12-23 | 南京大学 | Method for preparing high-quality flexible monocrystal silicon nanowire |
| CN107460542A (en) * | 2017-06-15 | 2017-12-12 | 南京大学 | A kind of preparation method of the stretchable crystalline semiconductor nano wire based on plane nano line Alignment Design and guiding |
| CN108557758B (en) * | 2018-02-08 | 2020-04-28 | 南京大学 | Method for growing nanowire array by guiding steps of circularly alternately etching homogeneous multistage slope surface |
| CN109941962B (en) * | 2019-03-28 | 2021-06-01 | 南京大学 | Method for electrically connecting high-density slope step nanowires |
-
2019
- 2019-11-05 CN CN201911071316.9A patent/CN110767537B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110767537A (en) | 2020-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110767537B (en) | Method for preparing three-dimensional super-stretchable crystalline nanowire | |
| CN103224231B (en) | Transfer method of graphite film | |
| CN109234807B (en) | Stretchable crystal semiconductor nanowire and preparation method thereof | |
| US8334216B2 (en) | Method for producing silicon nanostructures | |
| US9966250B2 (en) | Method to transfer two dimensional film grown on metal-coated wafer to the wafer itself in a face-to-face manner | |
| CN109941962B (en) | Method for electrically connecting high-density slope step nanowires | |
| CN102020271B (en) | Method of manufacturing graphene and graphene manufactured by the method | |
| CN102897750B (en) | PrPrearation method for graphene film | |
| CN102447011B (en) | Method for manufacturing solar battery photoanode and product thereof | |
| US8580658B1 (en) | Methods for fabricating graphene device topography and devices formed therefrom | |
| CN105358482A (en) | Graphene with very high charge carrier mobility and preparation thereof | |
| WO2014131043A1 (en) | Methods for fabricating graphite-based structures and devices made therefrom | |
| Schlur et al. | Synthesis of zinc oxide nanorods or nanotubes on one side of a microcantilever | |
| CN105206689A (en) | Photoelectric detector preparation method based on thin-film semiconductor-graphene heterojunction | |
| CN103199004A (en) | Manufacturing method of III-group nitride nano-structure | |
| KR20090057205A (en) | Thin film solar cell | |
| US20110111202A1 (en) | Multilayer film structure, and method and apparatus for transferring nano-carbon material | |
| US9168725B2 (en) | Method for transferring nanostructures | |
| CN103668453A (en) | Two-dimensional silylene film and preparation method thereof | |
| CN101104509A (en) | Method for preparing single nano material in pore space structure | |
| CN102765695B (en) | Method of manufacturing wafer-level low-dimensional nano-structure based on self-focusing of electrostatic field singular-point | |
| CN103738939A (en) | Method for fast stripping of graphene | |
| CN114080750A (en) | Generator and method of generating an electric current | |
| CN111180392A (en) | Method for obtaining large-size monocrystalline silicon nano-film on basis of silicon on insulator in large batch | |
| CN114604865B (en) | Graphene nanoribbon composite structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |