CN109211897B - Ion sensitive field effect transistor and preparation method thereof - Google Patents

Ion sensitive field effect transistor and preparation method thereof Download PDF

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CN109211897B
CN109211897B CN201710530807.XA CN201710530807A CN109211897B CN 109211897 B CN109211897 B CN 109211897B CN 201710530807 A CN201710530807 A CN 201710530807A CN 109211897 B CN109211897 B CN 109211897B
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electrode
substrate
sensitive
drain electrode
source electrode
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CN109211897A (en
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呼红阳
毕津顺
习凯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/75—Systems in which material is subjected to a chemical reaction, the progress or the result of the reaction being investigated
    • G01N21/77—Systems in which material is subjected to a chemical reaction, the progress or the result of the reaction being investigated by observing the effect on a chemical indicator
    • G01N21/78—Systems in which material is subjected to a chemical reaction, the progress or the result of the reaction being investigated by observing the effect on a chemical indicator producing a change of colour
    • G01N21/80—Indicating pH value

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

The present invention provides an ion sensitive field effect transistor comprising: a substrate; a drain electrode and a source electrode are built inwards and tightly attached to the upper surface of the substrate, the drain electrode covers the source electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other; and/or the source electrode covers the drain electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other; the part of the epitaxial layer between the source electrode and the drain electrode is provided with a grid electrode, and the cross section of the grid electrode is U-shaped; an epitaxial layer over the substrate. The ISFET device has a U-shaped gate structure, so that the contact area of the gate and a solution to be detected is increased, and the ISFET device is more sensitive to the solution. Meanwhile, the invention also provides a preparation method of the ion sensitive field effect transistor, which has simple process flow and is compatible with the standard CMOS process.

Description

Ion sensitive field effect transistor and preparation method thereof
Technical Field
The invention relates to the field of biosensors, in particular to an ion sensitive field effect transistor and a preparation method thereof.
Background
In recent years, with the good application prospect of ISFETs in DNA sequencing, experts are receiving more and more attention. The ISFET sensor has the characteristics of small volume, high sensitivity and easy integration, and has wide application requirements and markets in the biological medical treatment and the intelligent home by carrying the integrated circuit. However, compared to CMOS (complementary metal oxide semiconductor memory) devices, due to the particularity of the ISFET gate structure, its cumbersome fabrication process is still a significant bottleneck limiting its research and production.
Disclosure of Invention
Technical problem to be solved
The present invention is directed to an ion sensitive field effect transistor and a method for fabricating the same, so as to solve at least one of the above technical problems.
(II) technical scheme
The present invention provides an Ion Sensitive Field Effect Transistor (ISFET) comprising:
a substrate;
a drain electrode and a source electrode are built inwards and tightly attached to the upper surface of the substrate, the drain electrode covers the source electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other; and/or the source electrode covers the drain electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other; the part of the epitaxial layer between the source electrode and the drain electrode is provided with a grid electrode, and the cross section of the grid electrode is U-shaped; and
an epitaxial layer over the substrate.
Optionally, the ion sensitive field effect transistor is a source-drain extension transistor.
Optionally, the epitaxial layer is sequentially an isolation layer and a sensitive layer from bottom to top, and the isolation layer is made of SiO2The sensitive layer material is Si3N4Or Al2O3。
Optionally, the substrate is a silicon substrate or a germanium substrate, and the substrate is doped with any one element of phosphorus, gallium, phosphorus, or arsenic.
Optionally, a sensitive region is disposed on the upper surface of the gate, and the sensitive region is exposed outside the package structure during packaging.
Based on the same inventive concept, the invention also provides a preparation method of the ion sensitive field effect transistor, which comprises the following steps:
a drain electrode and a source electrode are built inwards and tightly attached to the upper surface of the substrate, the drain electrode covers the source electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other; and/or the source electrode covers the drain electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other;
growing an epitaxial layer on the substrate, and setting the part of the epitaxial layer between the source electrode and the drain electrode as a grid electrode, wherein the cross section of the grid electrode is U-shaped; and
and packaging the substrate and the epitaxial layer.
Optionally, the substrate is a silicon substrate or a germanium substrate, and the substrate is doped with any one element of phosphorus, gallium, phosphorus, or arsenic.
Optionally, before the packaging, the method further comprises the steps of: plating the source electrode, the drain electrode and the grid electrode, wherein the plating method comprises the following steps: evaporation, sputtering and atomic layer deposition.
Optionally, the drain and source are constructed by diffusion or ion implantation.
Optionally, a sensitive region is disposed on the upper surface of the gate, and the sensitive region is exposed outside the package structure during packaging.
(III) advantageous effects
Compared with the prior art, the invention has the following advantages:
1. the ISFET device has a U-shaped gate structure, so that the contact area of the gate and a solution to be detected is increased, and the ISFET device is more sensitive to the solution.
2. The device with the source-drain extended structure enables the source electrode and the drain electrode to be well isolated from the grid electrode sensitive area.
3. The sensitive film material silicon nitride has ion sensitive characteristic in the grid region and can play a role in passivation and isolation for other regions.
4. In the preparation process of the ISFET device, 6 mask plates are needed at most, the process flow is simple, and the ISFET device is compatible with a standard CMOS process.
Drawings
FIG. 1 is a top view of an ISFET device according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of an ISFET device according to an embodiment of the invention;
FIG. 3 is a schematic flow chart of a method for fabricating an ISFET device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a mask according to an embodiment of the present invention;
FIG. 5A is a graph of the transfer characteristics of an ISFET device according to an embodiment of the present invention;
FIG. 5B is a graph of the output of an ISFET device according to an embodiment of the present invention;
fig. 6 is a graph showing the sensitivity characteristics of an ISFET device according to an embodiment of the present invention with respect to pH.
Detailed Description
Based on the technical problem, the invention increases the contact area between the grid and the solution to be measured through the ISFET device with the U-shaped grid structure, so that the device is more sensitive to the pH value reaction of the solution to be measured. The invention also provides a preparation method of the ISFET device with the U-shaped gate structure, the ISFET device can be prepared by only 6 mask plates at most, the process flow is simple, the method is suitable for production, and the method can be compatible with the standard CMOS process.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
In one aspect of the embodiments of the present invention, there is provided an ion sensitive field effect transistor, fig. 1 is a top view of an ISFET device according to an embodiment of the present invention, as shown in fig. 1, where an axis a is cut through the ISFET device to obtain a cross section, and fig. 2 is a schematic cross-sectional view of the ISFET device according to an embodiment of the present invention, as shown in fig. 2, the ISFET device includes: the epitaxial layer comprises two growth layers, namely an isolation layer 2 and a sensitive layer 3 from bottom to top, wherein the isolation layer 2 is made of SiO2The sensitive layer 3 is made of Si3N4Or Al2O3(example of the present invention selects Si3N4As the sensitive layer 3). The isolation layer 2 is used for isolating a source electrode and a drain electrode, and the sensitive layer 3 is directly plated on the isolation layer 2 as a sensitive film to be in contact with a solution to be tested, so that the ISFET device is more sensitive to a pH value.
The substrate 1 is a silicon substrate or a germanium substrate, and the substrate 1 is doped with any element of phosphorus, gallium, phosphorus or arsenic to form an N-channel ISFET device or a P-channel ISFET device.
In one embodiment of the present invention, the ISFET device selects a source-drain extension type structure in order to enable good source and drain isolation from the gate sensitive region. A drain and a source are built in the substrate 1 next to the upper surface of the substrate 1, so that the drain covers the source along the upper surface direction, or the source covers the drain along the upper surface direction, and the drain and the source are not in contact with each other. In the embodiment of the invention, the drain is coated by the source along the upper surface direction, the drain is arranged at the inner side, the source is arranged at the two sides of the drain along the upper surface direction, the source and the drain are led out, the U-shaped gate structure is formed at the part of the sensitive layer 3 between the source and the drain, and the cross section of the gate is U-shaped. The U-shaped gate structure is selected, so that the contact area between the gate and the solution to be detected is increased, and the device is more sensitive to the reaction of the solution to be detected. The structure of the ISFET device is not limited to a source-drain extension type, and includes other structures such as an electrode extraction type and a gate extension type.
In order to ensure the contact area between the U-shaped gate of the ISFET device and the solution to be tested, a sensitive area is arranged on the upper surface of the U-shaped gate, namely the contact surface between the U-shaped gate and the solution to be tested, the sensitive area can be square, round or in other shapes, and the sensitive area is exposed out of the packaging structure during packaging.
In another aspect of the embodiments of the present invention, a method for manufacturing an ion sensitive field effect transistor is further provided, fig. 3 is a schematic flow chart of a method for manufacturing an ISFET device according to an embodiment of the present invention, as shown in fig. 3, fig. 4 is a schematic structural diagram of a mask plate according to an embodiment of the present invention, and with reference to fig. 3 and fig. 4, the method includes the steps of:
s1, a drain electrode and a source electrode are built inwards and tightly attached to the upper surface of the substrate, the drain electrode wraps the source electrode along the direction of the upper surface, and the source electrode and the drain electrode are not contacted with each other; and/or the source electrode covers the drain electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other;
a structure that the drain electrode covers the source electrode along the direction of the upper surface of the substrate can be selected, and a structure that the source electrode covers the drain electrode along the direction of the upper surface of the substrate can also be selected, and the source electrode and the drain electrode are not contacted with each other; and because the two structures are different, the turn-on voltage of the obtained ISFET is different, so that the voltage difference between the grid and the source and the voltage on the drain are changed.
The substrate is a silicon substrate or a germanium substrate, and any element of phosphorus, gallium, phosphorus or arsenic is doped in the substrate, so that the N-channel or P-channel ISFET device is obtained.
First, source and drain windows are formed on a substrate through a photolithography process,
and constructing a source electrode and a drain electrode by a concentrated phosphorus diffusion process or ion implantation, and photoetching diffusion window holes of a source region and a drain region by adopting an M1 mask plate, wherein white is reserved, and black is an etched part.
S2, growing an epitaxial layer on the substrate, wherein the sensitive layer is provided with a grid between the source and the drain, and the cross section of the grid is U-shaped; the epitaxial layer is composed of an isolation layer and a sensitive layer from bottom to top in sequence, and the isolation layer is made of SiO2Said sensitive layerThe material is Si3N4Or Al2O3(example of the present invention selects Si3N4As a sensitive layer).
Step S2 specifically includes: cleaning the cut and polished substrate, oxidizing once, thermally growing thick SiO2The layer serves as an isolation layer to isolate the transistor from the outside. Depositing Si on the isolation layer by LPCVD (low pressure chemical vapor deposition)3N4The insulating layer is used as a sensitive layer for H in the solution to be measured+And is more sensitive.
Removing SiO2 by HF, and oxidizing by dry oxygen and wet oxygen to grow boron diffusion barrier layer. And performing concentrated boron diffusion between the drain region and the source region except the gate region to form a channel barrier layer, and eliminating any leakage path from the drain to the source by adopting an M2 mask plate so as to reduce the leakage current of the drain and the source. Cleaning with HF to obtain SiO2. Then, using M3 mask to etch off SiO2Removing the photoresist, and oxidizing with dry oxygen to grow SiO2。
Finally, the SiO at the electrode is etched twice by using an M4 mask plate, and is etched at one time2Etching away Si once3N4。
The method can also comprise the following steps: and plating the source electrode, the drain electrode and the grid electrode: evaporating aluminum to form aluminum film, and making ISFET device with reference electrode by using M5 mask, reverse etching aluminum film or alloy, or using M5 mask. The plating method comprises the following steps: evaporation, sputtering and atomic layer deposition, the plated metal is not limited to aluminum but may also be copper or other metals.
And S3, packaging the substrate and the sensitive layer.
During packaging, a sensitive area can be arranged on the upper surface of the grid electrode in a windowing mode, and the sensitive area is exposed outside the packaging structure during packaging so as to be in contact with the solution. Wherein the sensitive area may be square, circular or other shape. The packaging method is not limited to ceramic packaging, and can also be plastic packaging, PCB packaging and other packaging modes.
Firstly, putting the manufactured ISFET device into aqueous solution with pH of 6.8, and respectively scanning gate voltage by a field effect transistor analyzerAnd obtaining the transfer characteristic curve and the output curve graph of the ISFET sensor according to the drain voltage. FIG. 5A is a graph of transfer characteristics of an ISFET device according to an embodiment of the present invention, and FIG. 5B is a graph of output of an ISFET device according to an embodiment of the present invention, as shown in FIGS. 5A and 5B, V of the ISFET transfer characteristicsgsThe scanning range is-2V-8V, and it can be seen from the figure that the threshold voltage of the ISFET device is near 1V, the ISFET device has good transfer characteristics, and the output curve is smooth and stable, so that the ISFET device provided by the embodiment of the invention can be used as a sensor for detecting the pH value.
Fig. 6 is a graph showing the sensitivity characteristic of the ISFET device according to the embodiment of the present invention with respect to pH, and as shown in fig. 6, in the solutions having pH values of 4, 6.8 and 9, the threshold voltage of the ISFET device is 0.76V, 0.82V and 1.1V in sequence, and the corresponding curves of the pH value and the threshold voltage are generally linear, so that the ISFET device has a good linear relationship with the pH value of the solution, and is suitable for detecting the pH value.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (7)

1. An ion sensitive field effect transistor comprising:
a substrate;
a drain electrode and a source electrode are built inwards and tightly attached to the upper surface of the substrate, the drain electrode covers the source electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other; or the source electrode covers the drain electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other;
the epitaxial layer is positioned above the substrate and sequentially provided with an isolating layer and a sensitive layer from bottom to top, the isolating layer is used for isolating the source electrode and the drain electrode, and the sensitive layer is used as a sensitive film and directly plated on the isolating layer and is used for contacting with a solution to be detected;
the part of the epitaxial layer between the source electrode and the drain electrode is provided with a grid electrode, the cross section of the grid electrode is U-shaped, the contact surface of the upper surface of the grid electrode and the solution to be detected is provided with a sensitive area, and the sensitive area is square or circular;
the ion sensitive field effect transistor is a source-drain expanded transistor, and the sensitive region is exposed outside the packaging structure during packaging.
2. The ion sensitive field effect transistor of claim 1, wherein the spacer material is SiO2The sensitive layer material is Si3N4Or Al2O3。
3. The ion sensitive field effect transistor of claim 1, wherein the substrate is a silicon substrate or a germanium substrate, and the substrate is doped with any one of phosphorus, gallium, phosphorus or arsenic.
4. A preparation method of an ion sensitive field effect transistor comprises the following steps:
a drain electrode and a source electrode are built inwards and tightly attached to the upper surface of the substrate, the drain electrode covers the source electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other; or the source electrode covers the drain electrode along the upper surface direction, and the source electrode and the drain electrode are not contacted with each other;
growing an epitaxial layer on the substrate, wherein the epitaxial layer is sequentially provided with an isolation layer and a sensitive layer from bottom to top, the sensitive layer is used as a sensitive film and is directly plated on the isolation layer and is used for contacting with a solution to be detected, the part of the epitaxial layer between a source electrode and a drain electrode is arranged as a grid electrode, the cross section of the grid electrode is U-shaped, a sensitive area is arranged on the contact surface of the upper surface of the grid electrode and the solution to be detected, and the sensitive area is square, round or in other shapes; and
and packaging the substrate and the epitaxial layer, wherein the sensitive area is exposed outside the packaging structure.
5. The method of claim 4, wherein the substrate is a silicon substrate or a germanium substrate, and the substrate is doped with any one of phosphorus, gallium, phosphorus, or arsenic.
6. The method of claim 4, further comprising, prior to encapsulating, the steps of: plating the source electrode, the drain electrode and the grid electrode, wherein the plating method comprises the following steps: evaporation, sputtering and atomic layer deposition.
7. The method of claim 4, wherein the drain and source are constructed by diffusion or ion implantation.
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CN1059092A (en) * 1991-09-20 1992-03-04 中国科学院电子学研究所 Sensor for detecting ph value of upper digestive tract
US5321291A (en) * 1991-12-16 1994-06-14 Texas Instruments Incorporated Power MOSFET transistor
EP1729121A1 (en) * 2005-05-30 2006-12-06 Mettler-Toledo AG Electrochemical sensor
CN101872023A (en) * 2009-04-22 2010-10-27 中国科学院微电子研究所 PMOS dosimeter adopting annular grid structure
CN102636543B (en) * 2011-02-09 2015-06-10 横河电机株式会社 Sensors and methods for measuring ph, ion sensor and ion concentration determination method
CN103592353B (en) * 2013-11-13 2016-05-18 胡文闯 Based on the biology sensor of the linear channel ion sensitive field effect transistor that wriggles
CN104934475A (en) * 2015-03-12 2015-09-23 西安电子科技大学 Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology
CN106449760A (en) * 2016-11-02 2017-02-22 西安电子科技大学 SOI (silicon on insulator) substrate based ring-gate radiation-proof MOS (metal oxide semiconductor) field-effect transistor

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