CN109194393A - A kind of multi tate error code testing device and its test method - Google Patents
A kind of multi tate error code testing device and its test method Download PDFInfo
- Publication number
- CN109194393A CN109194393A CN201810974567.7A CN201810974567A CN109194393A CN 109194393 A CN109194393 A CN 109194393A CN 201810974567 A CN201810974567 A CN 201810974567A CN 109194393 A CN109194393 A CN 109194393A
- Authority
- CN
- China
- Prior art keywords
- error code
- module
- unit
- detection
- detection module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
- H04B10/0795—Performance monitoring; Measurement of transmission parameters
- H04B10/07953—Monitoring or measuring OSNR, BER or Q
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Optical Communication System (AREA)
Abstract
The present invention relates to a kind of multi tate error code testing device and its test methods, including user terminal, control module, detection module, clock crystal oscillator module, signal shaping module and optical module；User terminal is used to send operational order to detection module by control module；Clock crystal oscillator module is for generating the first reference clock or N reference clock；Detection module is used to be initialized according to the first reference clock activation system, system default the first operating mode of corresponding starting, and carries out the first error code testing or N error code testing according to operational order, sends corresponding pseudo-random code sequence to optical module；Its operation result for being also used to receive optical module transmission acquires error code data；Optical module sends operation result to detection module for receiving pseudo-random code sequence, the rear of operation.The beneficial effects of the present invention are: hardware cost is low, easy to operate, error detection is high-efficient, can be used in the error detection of the optic communication product of a variety of rates, to reduce production cost.
Description
Technical field
The present invention relates to technical field of photo communication more particularly to a kind of multi tate error code testing device and its test methods.
Background technique
As high-quality digital video and audio transmission are using more and more extensive, especially interactive network electricity in recent years
Depending on the rapid development of the broadband IP services such as (IPTV), video calling, so that demand of the user to optical transport network bandwidth is also more next
It is bigger.Modern transfers net system is to be made of many different types of devices and transmission link, including pass through communication link
Connect network and other network elements communication device, for support high-speed communication system, need to develop high speed communication device and
Subsystem, and be to guarantee quality, such devices and subsystem must all be tested before factory by a large amount of stringent examinations.
The bit error rate is an important parameter of communication device and subsystem, for active device such as transmitter, receiver, biography
Receiving module etc. is sent to be even more important.These active devices simultaneously be also constitute communication system in hardware component and subsystem in most
It first has to generate bit test pattern data, be then sent to physical communication chain in error rate test for expensive component
The pattern received is compared by road after link transmission with original pattern, is recorded as one if the two mismatches
Error code.
The bit error rate refers to the total number of measured device or the link produced error code within the unit time.Error rate test is
Using position pattern, frame synchronization and communication standard, communication system (communication device and physical communication chain are imitated for the purpose of test
Road) in actual data qualification, wherein be pseudo-random bit sequence in a kind of pattern that field of telecommunications is widely used, referred to as
PRBS, PRBS are to generate bit sequence by algorithm, and bit sequence and true the random sequence statistics having the same generated is special
Property.
Code error tester is usually a set of independent device at present, can generate and send data to device to be measured or
In communication system, the data after device or communications system transmission are then received, are counted compared with the data of transmission
The bit error rate is calculated, it can generate a variety of patterns and carry out a plurality of types of tests；However, in most circumstances, especially
For production application, one of test subset is only needed, the complex process of code error tester makes
Obtaining it becomes separate unit test equipment the most expensive in high-speed telecommunication devices production, and when signal rate is higher, price
Also more expensive, the investment cost for buying such test equipment has become the burden of device and subsystem production, to extensive portion
Administration's high-speed communication system causes very big obstacle.
Summary of the invention
The technical problem to be solved by the present invention is in view of the drawbacks of the prior art, provide a kind of multi tate error code testing dress
It sets and its test method.
The technical scheme to solve the above technical problems is that
According to one aspect of the present invention, a kind of multi tate error code testing device, including user terminal, control mould are provided
Block, detection module, clock crystal oscillator module, signal shaping module and optical module；
The user terminal is used to send operational order to the detection module by the control module, is also used to receive
The error code data that the detection module is sent；
The clock crystal oscillator module is defaulted for generating the first reference clock or N reference clock, and when system starting
Generate the first reference clock；
The detection module includes synchronous adjustment unit, for being initialized according to the first reference clock activation system,
System default the first operating mode of corresponding starting, and the first error code testing or the survey of N error code are carried out according to the operational order
Examination sends corresponding pseudo-random code sequence to the optical module and for the pattern signal of test, the synchronous adjustment unit is used
Be delayed in by the pseudo-random code sequence, so that it is synchronous with the pattern signal, wherein if the operational order be into
The first error code testing of row, then detection module configures the first operating mode of system, if the operational order is to carry out N error code to survey
Examination, then system is switched to corresponding N reference clock, and configures system N operating mode；It is also used to receive optical module transmission
Operation result, error code data are acquired from the operation result, and analyze the error code data, and by the analysis result and
Compare output by the synchronous pattern signal of delay；
Wherein, the N is natural number；
The optical module includes input interface, variable optical attenuation unit and output interface, and the input interface is for receiving
The pseudo-random code sequence, after variable optical attenuation unit operation, by the output interface to the detection module
Send operation result；
The signal shaping module is arranged between the detection module and the optical module, and the signal shaping module
Multichannel setting, for the rise and fall time of data-signal between the detection module and the optical module and output amplitude into
Row adjustment.
The beneficial effects of the present invention are: hardware cost of the present invention is low, easy to operate, error detection is high-efficient, activation system
When, defaulted by clock crystal oscillator module and generate the first reference clock, carry out system initialization, then the corresponding starting of system default the
One operating mode, and the first error code testing or N error code testing are carried out according to the operational order of user terminal, if the operation
Instruction is to carry out the first error code testing, then detection module configures the first operating mode of system, if the operational order is to carry out N
Error code testing, then system is switched to corresponding N reference clock, and configures system N operating mode, and system is carrying out error code survey
Before examination, is initialized first with defaulting the first reference clock generated, the first error code is directly then carried out according to operational order
Test, or it is switched to N operating mode, the system start-up initialisation time can be reduced, improves working efficiency, and can be used in
The error detection of the optic communication product of a variety of rates, so that the production cost of high rate optical communication products is largely reduced,
It can largely be assemblied on the production line of high rate optical communication products, the scheduling and planning for optic communication product；In addition, passing through setting
Variable optical attenuation unit can adjust the optical signal on optical fiber link, can be used for the decaying feelings of optical signal on analog optical fiber channel
Condition improves error detection accuracy；Data-signal between detection module and optical module is adjusted by signal shaping module,
The shake of data-signal can be reduced.
Based on the above technical solution, the present invention can also be improved as follows.
Further, the detection module includes detection unit, transmission unit and receiving unit；
The detection unit is used for initial according to first reference clock or the second reference clock activation system
Change, system default the first operating mode of corresponding starting, and is sent according to the operational order to the transmission unit and carry out first
Error code testing or the instruction of N error code testing, wherein if the operational order is to carry out N error code testing, system is switched to
Corresponding N reference clock and N operating mode；
The transmission unit is connect with the synchronous adjustment unit, for according to the first error code testing of carry out for receiving or
Person's N error code testing, which is instructed, sends corresponding pseudo-random code sequence to the input interface and for the pattern signal of test；
The receiving unit is connect with the synchronous adjustment unit, the operation knot sent for receiving the output interface
Fruit, and error code data are acquired according to the operation result, and send the error code data to the detection unit.
The beneficial effect of above-mentioned further scheme is: test instruction is sent to transmission unit by detection unit, by connecing
It receives unit and receives the operation result of optical module, and acquire the error code data of pseudo-random code sequence simultaneously, by detection unit to error code
Data are analyzed and Received Loss Of Signal and when losing lock corresponding alarm data, to improve the accuracy rate of error detection.
Further, the transmission unit includes that subelement occurs for pattern, subelement and the same step occur for the pattern
Whole unit connection, it is described for sending corresponding pseudo-random code sequence to the input interface and for the pattern signal of test
The pseudo-random code sequence is delayed by synchronous adjustment unit, so that it is synchronous with the pattern signal.
The beneficial effect of above-mentioned further scheme is: by sending pseudo-random code sequence to optical module and for the code of test
Type signal, to detect the error code data of optical module in the process of running.
Further, the receiving unit includes pattern detection sub-unit and alarm-monitor subelement, pattern detection
Unit is connect with the synchronous adjustment unit, the operation result sent for receiving the output interface, and according to the operation
Interpretation of result error code data, and the error code data and the pattern letter synchronous by delay are sent to the detection unit
Number, the detection unit analyzes the error code data, and the pattern signal that the analysis result is synchronous with delay is passed through
Compare output；The alarm-monitor subelement is used to analyze alarm data according to the error code data, and to the detection unit
Send the alarm data.
The beneficial effect of above-mentioned further scheme is: during optical module runs pseudo-random code sequence, pattern detection
Unit when generation Received Loss Of Signal and receives signal losing lock for counting to the error code data generated in operational process
When, alarm-monitor subelement generates corresponding alarm data.
Further, the error code data include that error code counts, current error rate and error code alert.
Further, the alarm data includes Received Loss Of Signal alarm and reception signal losing lock alarm.
Further, the priority of the alarm data is higher than the priority of the error code data.
The beneficial effect of above-mentioned further scheme is: issuing Received Loss Of Signal alarm in alarm-monitor subelement and receives
When signal losing lock alerts, the acquisition and analysis to error code data can be stopped, in time to improve the accuracy of error code data.
Further, the control module includes micro-control unit and FPGA, the micro-control unit is real by the FPGA
Now to the access control of the detection unit, the data interaction of the user terminal Yu the detection module is realized；The FPGA
For realizing the conversion of communication protocol between the micro-control unit and the detection unit.
The beneficial effect of above-mentioned further scheme is: due to cannot directly be led between micro-control unit and detection unit
Letter between micro-control unit and FPGA, uses different communication protocol between FPGA and detection unit, realize that two kinds lead to by FPGA
Believe the mutual conversion between agreement, and then realizes the data interaction between micro-control unit, user terminal and detection unit.
According to another aspect of the invention, a kind of test method of multi tate error code testing device is provided, including following
Step:
S01: clock crystal oscillator module default generates the first reference clock；
S02: detection module judges whether the first reference clock is ready to, if being not ready for, system starting failure is returned
It returns step S01 and carries out step S03 if the first reference clock is ready；
S03: the initialization of detection module activation system, system default the first operating mode of corresponding starting；
S04: detection module judges whether system initialization succeeds, if not succeeding, system starting failure, and return step
S01, if system initialization success, carries out step S05；
S05: detection module waits user terminal operations instruction, judges whether to the first error code testing, if so, carrying out
Step S06, if it is not, then carrying out step S07；
S06: if carrying out the first error code testing, detection module configures the first operating mode of system；
S07: if without the first error code testing, detection module judges whether to N error code testing, if it is not, then
Return step S05, if so, clock module switches N reference clock, detection module configures system N operating mode；
S08: detection module is to input interface transmission pseudo-random code sequence and for the pattern signal of test, synchronous adjustment list
The pseudo-random code sequence is delayed by member, so that it is synchronous with the pattern signal, optical module receives pseudo-random code sequence
And the pattern signal, and run, signal shaping module carries out signal adjustment to the pseudo-random code sequence；
S09: detection module receives the operation result that output interface is sent, and error code data are acquired from the operation result,
And the error code data are analyzed, and the analysis result is exported compared with by the synchronous pattern signal of delay；
S10: user terminal inquires error code data by control module；
Wherein, the N is natural number.
The beneficial effects of the present invention are: defaulted by clock crystal oscillator module when activation system and generate the first reference clock, into
Row system initialization, then the first operating mode of the corresponding starting of system default, and the is carried out according to the operational order of user terminal
One error code testing or N error code testing, if the operational order is to carry out the first error code testing, detection module configures system
First operating mode, if the operational order is to carry out N error code testing, system is switched to corresponding N reference clock, and
Configuration system N operating mode, system are carried out initially with defaulting the first reference clock generated first before carrying out error code testing
Change, the first error code testing is directly then carried out according to operational order, or be switched to N operating mode, the system that can reduce opens
Dynamic initialization time, working efficiency is improved, and can be used in the error detection of the optic communication product of a variety of rates, thus very great Cheng
The production cost that high rate optical communication products are reduced on degree, can largely be assemblied on the production line of high rate optical communication products, use
In the scheduling and planning of optic communication product.
Detailed description of the invention
Fig. 1 is the module principle figure of error code testing device of the present invention.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
As shown in Figure 1, a kind of multi tate error code testing device comprising user terminal, control module, detection module, when
Clock crystal oscillator module, signal shaping module and optical module；
The user terminal is used to send operational order to the detection module by the control module, is also used to receive
The error code data that the detection module is sent；
The clock crystal oscillator module is defaulted for generating the first reference clock or N reference clock, and when system starting
Generate the first reference clock；
The detection module includes synchronous adjustment unit, for being initialized according to the first reference clock activation system,
System default the first operating mode of corresponding starting, and the first error code testing or the survey of N error code are carried out according to the operational order
Examination sends corresponding pseudo-random code sequence to the optical module and for the pattern signal of test, the synchronous adjustment unit is used
Be delayed in by the pseudo-random code sequence, so that it is synchronous with the pattern signal, wherein if the operational order be into
The first error code testing of row, then detection module configures the first operating mode of system, if the operational order is to carry out N error code to survey
Examination, then system is switched to corresponding N reference clock, and configures system N operating mode；It is also used to receive optical module transmission
Operation result, error code data are acquired from the operation result, and analyze the error code data, and by the analysis result and
Compare output by the synchronous pattern signal of delay；
Wherein, the N is natural number；
The optical module includes input interface, variable optical attenuation unit and output interface, and the input interface is for receiving
The pseudo-random code sequence, after variable optical attenuation unit operation, by the output interface to the detection module
Send operation result；
The signal shaping module is arranged between the detection module and the optical module, and the signal shaping module
Multichannel setting, for the rise and fall time of data-signal between the detection module and the optical module and output amplitude into
Row adjustment.
First reference clock, first operating mode and first error code testing correspond, the N ginseng
Clock, the N operating mode and the N error code testing is examined to correspond；First operating mode and the N work
Mode respectively corresponds the operating mode under a kind of benchmark service rate, such as IEEE 802.3bm 40GE benchmark service rate, IEEE
802.3ba 100GE benchmark service rate and ITU OTL 4.4OTU4 benchmark service rate.
The detection module includes detection unit, transmission unit and receiving unit；
The detection unit is used to be initialized according to the first reference clock activation system, the corresponding starting of system default the
One operating mode, and sent according to the operational order to the transmission unit and carry out the first error code testing or the survey of N error code
Examination instruction, wherein if the operational order is to carry out N error code testing, system is switched to corresponding N reference clock, with
And N operating mode；
The transmission unit is connect with the synchronous adjustment unit, for according to the first error code testing of carry out for receiving or
Person's N error code testing, which is instructed, sends corresponding pseudo-random code sequence to the input interface and for the pattern signal of test；
The receiving unit is connect with the synchronous adjustment unit, the operation knot sent for receiving the output interface
Fruit, and error code data are acquired according to the operation result, and send the error code data to the detection unit.
The transmission unit includes that subelement occurs for pattern, and subelement occurs for the pattern and the synchronous adjustment unit connects
It connects, for sending corresponding pseudo-random code sequence to the input interface and for the pattern signal of test, the synchronous adjustment
The pseudo-random code sequence is delayed by unit, so that it is synchronous with the pattern signal.
The receiving unit includes pattern detection sub-unit and alarm-monitor subelement, the pattern detection sub-unit and institute
The connection of synchronous adjustment unit is stated, the operation result sent for receiving the output interface, and analyzed according to the operation result
Error code data, and the error code data and the pattern signal synchronous by delay, the inspection are sent to the detection unit
It surveys unit and analyzes the error code data, and the analysis result is exported compared with by the synchronous pattern signal of delay；
The alarm-monitor subelement is used to analyze alarm data according to the error code data, and sends the announcement to the detection unit
Alert data.
The error code data include that error code counts, current error rate and error code alert.
The alarm data includes Received Loss Of Signal alarm and reception signal losing lock alarm.
The priority of the alarm data is higher than the priority of the error code data.
The control module includes micro-control unit and FPGA, and the micro-control unit is realized by the FPGA to described
The access control of detection unit realizes the data interaction of the user terminal Yu the detection module；The FPGA for realizing
The conversion of communication protocol between the micro-control unit and the detection unit.
In the present embodiment, MDIO communication agreement, the microcontroller list are used between the FPGA and the detection unit
It is first that SPI communication agreement is used between the FPGA；It cannot directly be carried out between the micro-control unit and the detection unit
Communication so realizing the mutual conversion between MDIO communication agreement and SPI communication agreement by the FPGA, and then realizes that user is whole
Data interaction between end and detection unit.
It further include power module, the power module is used to power to the detection module.
A kind of test method of multi tate error code testing device comprising following steps:
S01: clock crystal oscillator module default generates the first reference clock；
S02: detection module judges whether the first reference clock is ready to, if being not ready for, system starting failure is returned
It returns step S01 and carries out step S03 if the first reference clock is ready；
S03: the initialization of detection module activation system, system default the first operating mode of corresponding starting；
S04: detection module judges whether system initialization succeeds, if not succeeding, system starting failure, and return step
S01, if system initialization success, carries out step S05；
S05: detection module waits user terminal operations instruction, judges whether to the first error code testing, if so, carrying out
Step S06, if it is not, then carrying out step S07；
S06: if carrying out the first error code testing, detection module configures the first operating mode of system；
S07: if without the first error code testing, detection module judges whether to N error code testing, if it is not, then
Return step S05, if so, clock module switches N reference clock, detection module configures system N operating mode；
S08: detection module is to input interface transmission pseudo-random code sequence and for the pattern signal of test, synchronous adjustment list
The pseudo-random code sequence is delayed by member, so that it is synchronous with the pattern signal, optical module receives pseudo-random code sequence
And the pattern signal, and run, signal shaping module carries out signal adjustment to the pseudo-random code sequence；
S09: detection module receives the operation result that output interface is sent, and error code data are acquired from the operation result,
And the error code data are analyzed, and the analysis result is exported compared with by the synchronous pattern signal of delay；
S10: user terminal inquires error code data by control module；
Wherein, the N is natural number.
Specifically, step S02 relevant operation of detection module into step S09 is carried out by detection unit；
Wherein, the concrete operations process of the step S08 is that detection unit starts transmission unit, by transmission unit
Pattern occurs subelement and to input interface sends pseudo-random code sequence and for the pattern signal of test, and synchronous adjustment unit is by institute
It states pseudo-random code sequence to be delayed, so that it is synchronous with the pattern signal, optical module receives pseudo-random code sequence and pattern
Signal, and run；
The concrete operations process of the step S09 is that receiving unit receives the operation result that output interface is sent, by pattern
Detection sub-unit acquires error code data from the operation result, and sends the error code data and process to the detection unit
Be delayed the synchronous pattern signal, and the detection unit analyzes the error code data, and the analysis result and process are prolonged
When the synchronous pattern signal compare output, by alarm-monitor subelement according to error code data analysis alarm data, and
The alarm data is sent to the detection unit；
In the step S10, the error code data that user terminal is inquired by control module include that error code is counted, currently missed
Code rate and error code alarm, moreover it is possible to inquire the alarm number including Received Loss Of Signal alerts and receives the alarm of signal losing lock
According to.
Wherein, the dedicated core of error code testing for the model VSC8248 that the detection unit is produced using Microsemi company
Piece, working principle and electric connecting relation are existing well-known technique, and details are not described herein.
In the optical module operational process, the step S09 is synchronous real time execution with the step S10.
In the step S10, if alarm-monitor subelement to alarm data, i.e., Received Loss Of Signal alarm and receives signal
Losing lock alarm, then pattern detection sub-unit stops analysis and update to error code data in the step S09, until alarm data
It disappears.
When generating Received Loss Of Signal alarm and receiving the alarm of signal losing lock, Received Loss Of Signal pair can be locked immediately
As, and reduce the influence that Received Loss Of Signal acquires error code data.
In the step S10, if user terminal inquires alarm data, user terminal can be according to Received Loss Of Signal
Alarm and reception signal losing lock warning information position the measurand to break down, and the measurand is to transport in optical module
Capable pseudo-random code sequence.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of multi tate error code testing device, it is characterised in that: brilliant including user terminal, control module, detection module, clock
Shake module, signal shaping module and optical module；
The user terminal is used to send operational order to the detection module by the control module, is also used to receive described
The error code data that detection module is sent；
For generating the first reference clock or N reference clock, and when system starting, default generates the clock crystal oscillator module
First reference clock；
The detection module includes synchronous adjustment unit, for being initialized according to the first reference clock activation system, system
Default the first operating mode of corresponding starting, and the first error code testing or N error code testing are carried out according to the operational order, to
The optical module sends corresponding pseudo-random code sequence and the pattern signal for test, and the synchronous adjustment unit is used for institute
It states pseudo-random code sequence to be delayed, so that it is synchronous with the pattern signal, wherein if the operational order is carry out first
Error code testing, then detection module configures the first operating mode of system, if the operational order is to carry out N error code testing, is
System is switched to corresponding N reference clock, and configures system N operating mode；Its operation for being also used to receive optical module transmission
As a result, acquiring error code data from the operation result, and the error code data are analyzed, and the analysis result and process are prolonged
When the synchronous pattern signal compare output；
Wherein, the N is natural number；
The optical module includes input interface, variable optical attenuation unit and output interface, and the input interface is described for receiving
Pseudo-random code sequence is sent by the output interface to the detection module after variable optical attenuation unit operation
Operation result；
The signal shaping module is arranged between the detection module and the optical module, and the signal shaping module multichannel
Setting, for being adjusted to the rise and fall time of data-signal and output amplitude between the detection module and the optical module
It is whole.
2. a kind of multi tate error code testing device according to claim 1, it is characterised in that: the detection module includes detection
Unit, transmission unit and receiving unit；
The detection unit is used to be initialized according to the first reference clock activation system, system default the first work of corresponding starting
Operation mode, and referred to according to the operational order to transmission unit transmission the first error code testing of progress or N error code testing
It enables, wherein if the operational order is to carry out N error code testing, system is switched to corresponding N reference clock and N
Operating mode；
The transmission unit is connect with the synchronous adjustment unit, for according to the first error code testing of carry out for receiving or the
N error code testing, which is instructed, sends corresponding pseudo-random code sequence to the input interface and for the pattern signal of test；
The receiving unit is connect with the synchronous adjustment unit, the operation result sent for receiving the output interface, and
Error code data are acquired according to the operation result, and send the error code data to the detection unit, and the analysis is tied
Fruit exports compared with by the synchronous pattern signal of delay.
3. a kind of multi tate error code testing device according to claim 2, it is characterised in that: the transmission unit includes pattern
Subelement occurs, the pattern occurs subelement and connect with the synchronous adjustment unit, for sending phase to the input interface
The pseudo-random code sequence answered and the pattern signal for test, the synchronous adjustment unit prolong the pseudo-random code sequence
When, so that it is synchronous with the pattern signal.
4. a kind of multi tate error code testing device according to claim 2, it is characterised in that: the receiving unit includes pattern
Detection sub-unit and alarm-monitor subelement, the pattern detection sub-unit is connect with the synchronous adjustment unit, for receiving
The operation result that the output interface is sent, and error code data are acquired according to the operation result, and send out to the detection unit
The error code data and the pattern signal synchronous by delay are sent, the detection unit analyzes the error code data, and will
The analysis result exports compared with by the synchronous pattern signal of delay；The alarm-monitor subelement is used for according to institute
Error code data analysis alarm data is stated, and sends the alarm data to the detection unit.
5. a kind of multi tate error code testing device according to claim 4, it is characterised in that: the error code data include error code
It counts, current error rate and error code alert.
6. a kind of multi tate error code testing device according to claim 5, it is characterised in that: the alarm data includes receiving
Loss of signal alarm and reception signal losing lock alarm.
7. a kind of multi tate error code testing device according to claim 6, it is characterised in that: the priority of the alarm data
Higher than the priority of the error code data.
8. a kind of multi tate error code testing device according to claim 2, it is characterised in that: the control module includes micro-control
Unit and FPGA processed, the micro-control unit are realized by the FPGA to the access control of the detection unit, described in realization
The data interaction of user terminal and the detection module；The FPGA is for realizing the micro-control unit and the detection unit
Between communication protocol conversion.
9. a kind of test method of multi tate error code testing device, which comprises the following steps:
S01: clock crystal oscillator module default generates the first reference clock；
S02: detection module judges whether the first reference clock is ready to, if being not ready for, system starting failure returns to step
Rapid S01 carries out step S03 if the first reference clock is ready；
S03: the initialization of detection module activation system, system default the first operating mode of corresponding starting；
S04: detection module judges whether system initialization succeeds, if not succeeding, system starting failure, and return step S01,
If system initialization success, carries out step S05；
S05: detection module waits user terminal operations instruction, judges whether to the first error code testing, if so, carrying out step
S06, if it is not, then carrying out step S07；
S06: if carrying out the first error code testing, detection module configures the first operating mode of system；
S07: if without the first error code testing, detection module judges whether to N error code testing, if it is not, then returning
Step S05, if so, clock module switches N reference clock, detection module configures system N operating mode；
S08: detection module sends pseudo-random code sequence to input interface and for the pattern signal of test, synchronous adjustment unit will
The pseudo-random code sequence is delayed, so that it is synchronous with the pattern signal, optical module receives pseudo-random code sequence and institute
Pattern signal is stated, and is run, signal shaping module carries out signal adjustment to the pseudo-random code sequence；
S09: detection module receives the operation result that output interface is sent, and error code data is acquired from the operation result, and divide
The error code data are analysed, and the analysis result is exported compared with by the synchronous pattern signal of delay；
S10: user terminal inquires error code data by control module；
Wherein, the N is natural number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810974567.7A CN109194393B (en) | 2018-08-24 | 2018-08-24 | Multi-rate error code testing device and testing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810974567.7A CN109194393B (en) | 2018-08-24 | 2018-08-24 | Multi-rate error code testing device and testing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109194393A true CN109194393A (en) | 2019-01-11 |
| CN109194393B CN109194393B (en) | 2022-08-12 |
Family
ID=64919823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810974567.7A Active CN109194393B (en) | 2018-08-24 | 2018-08-24 | Multi-rate error code testing device and testing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109194393B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111010241A (en) * | 2019-12-03 | 2020-04-14 | 杭州电子科技大学富阳电子信息研究院有限公司 | Multi-protocol high-speed pseudo-random signal loop test system based on FPGA |
| CN111948512A (en) * | 2020-06-19 | 2020-11-17 | 浪潮(北京)电子信息产业有限公司 | Cable signal integrity testing method and device and storage medium |
| CN114070493A (en) * | 2021-11-17 | 2022-02-18 | 四川灵通电讯有限公司 | Automatic testing device and application method for digital subscriber line equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080315928A1 (en) * | 2007-06-22 | 2008-12-25 | Khurram Waheed | Digital phase locked loop with dithering |
| CN201341143Y (en) * | 2007-11-24 | 2009-11-04 | 苏州旭创科技有限公司 | High-speed digital communication error code tester |
| CN101895353A (en) * | 2010-07-07 | 2010-11-24 | 东莞市铭普实业有限公司 | Multi-speed bite error analysis and detecting instrument capable of detecting four units |
-
2018
- 2018-08-24 CN CN201810974567.7A patent/CN109194393B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080315928A1 (en) * | 2007-06-22 | 2008-12-25 | Khurram Waheed | Digital phase locked loop with dithering |
| CN201341143Y (en) * | 2007-11-24 | 2009-11-04 | 苏州旭创科技有限公司 | High-speed digital communication error code tester |
| CN101895353A (en) * | 2010-07-07 | 2010-11-24 | 东莞市铭普实业有限公司 | Multi-speed bite error analysis and detecting instrument capable of detecting four units |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111010241A (en) * | 2019-12-03 | 2020-04-14 | 杭州电子科技大学富阳电子信息研究院有限公司 | Multi-protocol high-speed pseudo-random signal loop test system based on FPGA |
| CN111010241B (en) * | 2019-12-03 | 2021-12-14 | 杭州电子科技大学富阳电子信息研究院有限公司 | Multi-protocol high-speed pseudo-random signal loop test system based on FPGA |
| CN111948512A (en) * | 2020-06-19 | 2020-11-17 | 浪潮(北京)电子信息产业有限公司 | Cable signal integrity testing method and device and storage medium |
| CN114070493A (en) * | 2021-11-17 | 2022-02-18 | 四川灵通电讯有限公司 | Automatic testing device and application method for digital subscriber line equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109194393B (en) | 2022-08-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101442385B (en) | Test device of digital communication error rate | |
| US7539489B1 (en) | Location-based testing for wireless data communication networks | |
| US8831435B2 (en) | System and method for dual wavelength communications of a clock signal | |
| CN109194393A (en) | A kind of multi tate error code testing device and its test method | |
| CN107819483B (en) | Signal transmitting apparatus and its test equipment, repeater communication equipment | |
| CN109039450B (en) | Multi-rate error code detection device and detection method thereof | |
| CN106789430A (en) | A kind of point-to-point link fault detection method | |
| CN109639534A (en) | A kind of method, apparatus and computer storage medium of test network transmission performance | |
| CN109194391B (en) | Error code detection system and detection method thereof | |
| US6859828B1 (en) | Bi-directional test system for network analysis | |
| CN114024598B (en) | Forwarding interface test method and device | |
| CN109217921B (en) | Error code testing device and testing method thereof | |
| CN102647313B (en) | A kind of network test system | |
| CN109194392A (en) | A kind of multi tate error detection system and its detection method | |
| US20070195708A1 (en) | Framing mobile communication signals for analysis | |
| CN114844804A (en) | Network measurement method, system, electronic device and computer readable storage medium | |
| CN109194394A (en) | A kind of device for detecting code error | |
| CN112636825A (en) | Method, device and system for measuring time delay in optical transport network | |
| CN112492413A (en) | Preamble sending method and device and preamble receiving method and device | |
| US11979190B2 (en) | Passive optical network | |
| CN109067457A (en) | A kind of multi tate bit error analyzing detector | |
| CN117014341B (en) | Virtual switch testing method and system | |
| CN113541776B (en) | Method for implementing optical fiber detection and clock synchronization and related equipment | |
| KR102534572B1 (en) | Method and apparatus for testing optical tranceiver for terminal equipment of passive optical access network | |
| WO2022267699A1 (en) | Abnormal positioning method, device and system, and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |