CN109194393B - Multi-rate error code testing device and testing method thereof - Google Patents
Multi-rate error code testing device and testing method thereof Download PDFInfo
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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Abstract
The invention relates to a multi-rate error code testing device and a testing method thereof, wherein the device comprises a user terminal, a control module, a detection module, a clock crystal oscillator module, a signal shaping module and an optical module; the user terminal is used for sending an operation instruction to the detection module through the control module; the clock crystal oscillator module is used for generating a first reference clock or an Nth reference clock; the detection module is used for starting system initialization according to the first reference clock, the system defaults to correspondingly start a first working mode, carries out a first error code test or an Nth error code test according to an operation instruction, and sends a corresponding pseudo-random code sequence to the optical module; the optical module is also used for receiving the operation result sent by the optical module and acquiring error code data; the optical module is used for receiving the pseudo-random code sequence and sending an operation result to the detection module after operation. The invention has the beneficial effects that: the hardware cost is low, the operation is simple, the error code detection efficiency is high, and the method can be used for the error code detection of optical communication products with various rates, thereby reducing the production cost.
Description
Technical Field
The invention relates to the technical field of optical communication, in particular to a multi-rate error code testing device and a testing method thereof.
Background
With the application of high-quality digital video and audio transmission becoming more and more widespread, especially with the rapid development of broadband IP services such as interactive network television (IPTV), video call, etc., users have an increasing demand for bandwidth of optical transmission networks. Modern transmission network systems are composed of many different kinds of devices and transmission links, including communication devices for connecting networks and other network elements via communication links, and in order to support high-speed communication systems, high-speed communication devices and subsystems are developed, and in order to ensure quality, such devices and subsystems must pass a large number of strict examination tests before being shipped.
Bit error rate is an important parameter for communication devices and subsystems, and is particularly important for active devices such as transmitters, receivers, transmit-receive modules, and the like. In the error rate test, firstly, bit test pattern data is generated and then sent to a physical communication link, the received pattern is compared with the original pattern after the transmission of the link, and if the two are not matched, the error code is recorded.
The bit error rate is the total number of errors generated by the device under test or the link in a unit time. The bit error rate test is to simulate the actual data conditions in the communication system (communication device and physical communication link) with the purpose of testing by using a bit pattern, frame synchronization and communication standards, wherein one bit pattern widely used in the field of telecommunications is a pseudo random bit sequence, PRBS for short, which generates a bit sequence through an algorithm, and the generated bit sequence has the same statistical characteristics as a real random sequence.
The prior error code tester is usually an independent device, can generate and send data to a device to be tested or a communication system, then receives the data transmitted by the device or the communication system, compares the data with the sent data to calculate the error code rate, and can generate a plurality of code patterns and carry out a plurality of types of tests; however, in most cases, especially for production applications, only one test subset is needed, the complicated process of the error tester makes it the most expensive single test equipment in the production of high-speed communication devices, and the cost of purchasing such test equipment becomes a burden for the production of devices and subsystems, which causes a great obstacle to the large-scale deployment of high-speed communication systems.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a multi-rate error code testing device and a testing method thereof.
The technical scheme for solving the technical problems is as follows:
according to one aspect of the invention, a multi-rate error code testing device is provided, which comprises a user terminal, a control module, a detection module, a clock crystal oscillator module, a signal shaping module and an optical module;
the user terminal is used for sending an operation instruction to the detection module through the control module and receiving error code data sent by the detection module;
the clock crystal oscillator module is used for generating a first reference clock or an Nth reference clock, and when the system is started, the first reference clock is generated by default;
the detection module comprises a synchronous adjusting unit, a first working mode is started by default according to the system initialization started by the first reference clock, a first error code test or an Nth error code test is carried out according to the operation instruction, a corresponding pseudo random code sequence and a code pattern signal used for testing are sent to the optical module, the synchronous adjusting unit is used for delaying the pseudo random code sequence so as to enable the pseudo random code sequence to be synchronous with the code pattern signal, if the operation instruction is to carry out the first error code test, the detection module configures the first working mode of the system, and if the operation instruction is to carry out the Nth error code test, the system is switched to a corresponding Nth reference clock and configures the Nth working mode of the system; the system is also used for receiving an operation result sent by an optical module, acquiring error code data from the operation result, analyzing the error code data, and comparing and outputting the analysis result and the code pattern signal subjected to delay synchronization;
wherein, the N is a natural number;
the optical module comprises an input interface, a variable optical attenuation unit and an output interface, wherein the input interface is used for receiving the pseudo random code sequence, and after the pseudo random code sequence is operated by the variable optical attenuation unit, an operation result is sent to the detection module through the output interface;
the signal shaping module is arranged between the detection module and the optical module, and the signal shaping module is arranged in a multipath manner and is used for adjusting the rising and falling time and the output amplitude of the data signal between the detection module and the optical module.
The invention has the beneficial effects that: the hardware cost of the invention is low, the operation is simple, the error code detection efficiency is high, when starting the system, the first reference clock is generated by the clock crystal oscillator module by default, the system is initialized, then the system is defaulted to correspondingly start the first working mode, the first error code test or the Nth error code test is carried out according to the operation instruction of the user terminal, if the operation instruction is to carry out the first error code test, the detection module configures the first working mode of the system, if the operation instruction is to carry out the Nth error code test, the system is switched to the corresponding Nth reference clock and configures the Nth working mode of the system, before carrying out the error code test, the system is initialized by the first reference clock which is generated by default, then directly carries out the first error code test according to the operation instruction or is switched to the Nth working mode, the system starting initialization time can be reduced, and the working efficiency can be improved, the method can be used for error code detection of optical communication products with various speeds, thereby greatly reducing the production cost of the high-speed optical communication products, and can be assembled on a production line of the high-speed optical communication products in large quantity for production debugging of the optical communication products; in addition, the variable optical attenuation unit can adjust the optical signal on the optical fiber link, can be used for simulating the attenuation condition of the optical signal on the optical fiber channel and improves the error code detection accuracy; the signal shaping module adjusts the data signal between the detection module and the optical module, and the jitter of the data signal can be reduced.
On the basis of the technical scheme, the invention can be further improved as follows.
Further: the detection module comprises a detection unit, a sending unit and a receiving unit;
the detection unit is used for starting system initialization according to the first reference clock or the second reference clock, the system defaults to correspondingly start a first working mode, and sends a first error code test or Nth error code test instruction to the sending unit according to the operation instruction, wherein if the operation instruction is to carry out the Nth error code test, the system is switched to the corresponding Nth reference clock and the Nth working mode;
the sending unit is connected with the synchronous adjusting unit and used for sending a corresponding pseudo-random code sequence and a code type signal for testing to the input interface according to a received first error code test or Nth error code test instruction;
the receiving unit is connected with the synchronous adjusting unit and used for receiving the operation result sent by the output interface, acquiring error code data according to the operation result and sending the error code data to the detecting unit.
The beneficial effects of the further scheme are as follows: the detection unit sends a test instruction to the sending unit, the receiving unit receives the operation result of the optical module and acquires the error code data of the pseudo-random code sequence at the same time, and the detection unit analyzes the error code data and receives corresponding alarm data when the signal is lost and locked so as to improve the accuracy of error code detection.
Further: the sending unit comprises a code pattern generating subunit, the code pattern generating subunit is connected with the synchronous adjusting unit and is used for sending a corresponding pseudo-random code sequence and a code pattern signal for testing to the input interface, and the synchronous adjusting unit delays the pseudo-random code sequence so as to synchronize the pseudo-random code sequence with the code pattern signal.
The beneficial effects of the above further scheme are: the method comprises the steps of sending a pseudo-random code sequence and a code pattern signal for testing to an optical module to detect error code data of the optical module in the running process.
Further: the receiving unit comprises a code pattern detection subunit and an alarm monitoring subunit, the code pattern detection subunit is connected with the synchronous adjusting unit and is used for receiving the operation result sent by the output interface, analyzing error code data according to the operation result and sending the error code data and the code pattern signal subjected to delay synchronization to the detecting unit, and the detecting unit analyzes the error code data and compares the analysis result with the code pattern signal subjected to delay synchronization for output; and the alarm monitoring subunit is used for analyzing alarm data according to the error code data and sending the alarm data to the detection unit.
The beneficial effects of the further scheme are as follows: in the process of operating pseudo-random code sequence by the optical module, the code pattern detection subunit is used for counting error code data generated in the operation process, and when the loss of the received signal and the loss of the lock of the received signal are generated, the alarm monitoring subunit generates corresponding alarm data.
Further: the error data includes an error count, a current error rate, and an error alarm.
Further: the alarm data includes a received signal loss alarm and a received signal loss-of-lock alarm.
Further: the priority of the alarm data is higher than that of the error code data.
The beneficial effects of the further scheme are as follows: when the alarm monitoring subunit sends out a received signal loss alarm and a received signal lock loss alarm, the acquisition and analysis of error code data can be stopped in time so as to improve the accuracy of the error code data.
Further: the control module comprises a micro control unit and an FPGA (field programmable gate array), the micro control unit realizes access control on the detection unit through the FPGA and realizes data interaction between the user terminal and the detection module; the FPGA is used for realizing the conversion of the communication protocol between the micro control unit and the detection unit.
The beneficial effects of the further scheme are as follows: because the micro control unit and the detection unit can not be directly communicated, different communication protocols are adopted between the micro control unit and the FPGA and between the FPGA and the detection unit, the FPGA realizes the mutual conversion between the two communication protocols, and further realizes the data interaction between the micro control unit, the user terminal and the detection unit.
According to another aspect of the present invention, there is provided a method for testing a multi-rate error code testing apparatus, comprising the steps of:
s01: the clock crystal oscillator module generates a first reference clock by default;
s02: the detection module judges whether the first reference clock is ready, if not, the system fails to start, the step is returned to the step S01, and if the first reference clock is ready, the step S03 is carried out;
s03: the detection module starts system initialization, and the system defaults to correspondingly start a first working mode;
s04: the detection module judges whether the system initialization is successful, if not, the system start is failed, the step is returned to S01, and if the system initialization is successful, the step is carried out S05;
s05: the detection module waits for an operation instruction of the user terminal and judges whether a first error code test is carried out, if so, the step S06 is carried out, and if not, the step S07 is carried out;
s06: if the first error code test is carried out, the detection module configures a first working mode of the system;
s07: if not, the detection module judges whether to perform the Nth error code test, if not, the step S05 is returned, if so, the clock module switches the Nth reference clock, and the detection module configures the Nth working mode of the system;
s08: the detection module sends a pseudo-random code sequence and a code pattern signal for testing to the input interface, the synchronous adjustment unit delays the pseudo-random code sequence so as to enable the pseudo-random code sequence to be synchronous with the code pattern signal, the optical module receives the pseudo-random code sequence and the code pattern signal and operates, and the signal shaping module adjusts the pseudo-random code sequence;
s09: the detection module receives an operation result sent by an output interface, acquires error code data from the operation result, analyzes the error code data, and compares and outputs the analysis result with the code pattern signal subjected to delay synchronization;
s10: the user terminal inquires error code data through the control module;
wherein, the N is a natural number.
The invention has the beneficial effects that: when the system is started, a first reference clock is generated by a clock crystal oscillator module in a default mode to carry out system initialization, then the system is in a default corresponding starting first working mode, a first error code test or an Nth error code test is carried out according to an operation instruction of a user terminal, if the operation instruction is to carry out the first error code test, a detection module configures the first working mode of the system, if the operation instruction is to carry out the Nth error code test, the system is switched to a corresponding Nth reference clock and configures the Nth working mode of the system, before the error code test is carried out, the system is initialized by the first reference clock generated by the default first reference clock, then the first error code test is directly carried out according to the operation instruction, or the system is switched to the Nth working mode, the system starting initialization time can be reduced, the working efficiency is improved, and the system can be used for error code detection of optical communication products with various rates, therefore, the production cost of the high-speed optical communication product is reduced to a great extent, and the optical communication device can be assembled on a production line of the high-speed optical communication product in a large quantity and is used for production debugging of the optical communication product.
Drawings
Fig. 1 is a block schematic diagram of the error code testing device of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a multi-rate error code testing apparatus includes a user terminal, a control module, a detection module, a clock oscillator module, a signal shaping module, and an optical module;
the user terminal is used for sending an operation instruction to the detection module through the control module and receiving error code data sent by the detection module;
the clock crystal oscillator module is used for generating a first reference clock or an Nth reference clock, and when the system is started, the first reference clock is generated by default;
the detection module comprises a synchronous adjusting unit, a first working mode is started by default according to the system initialization started by the first reference clock, a first error code test or an Nth error code test is carried out according to the operation instruction, a corresponding pseudo random code sequence and a code pattern signal used for testing are sent to the optical module, the synchronous adjusting unit is used for delaying the pseudo random code sequence so as to enable the pseudo random code sequence to be synchronous with the code pattern signal, if the operation instruction is to carry out the first error code test, the detection module configures the first working mode of the system, and if the operation instruction is to carry out the Nth error code test, the system is switched to a corresponding Nth reference clock and configures the Nth working mode of the system; the system is also used for receiving an operation result sent by an optical module, acquiring error code data from the operation result, analyzing the error code data, and comparing and outputting the analysis result and the code pattern signal subjected to delay synchronization;
wherein, the N is a natural number;
the optical module comprises an input interface, a variable optical attenuation unit and an output interface, wherein the input interface is used for receiving the pseudo random code sequence, and after the pseudo random code sequence is operated by the variable optical attenuation unit, an operation result is sent to the detection module through the output interface;
the signal shaping module is arranged between the detection module and the optical module, and the signal shaping module is arranged in a multipath manner and is used for adjusting the rising and falling time and the output amplitude of the data signal between the detection module and the optical module.
The first reference clock, the first working mode and the first error code test are in one-to-one correspondence, and the Nth reference clock, the Nth working mode and the Nth error code test are in one-to-one correspondence; the first working mode and the nth working mode respectively correspond to working modes at a standard service rate, such as an IEEE 802.3bm 40GE standard service rate, an IEEE 802.3ba 100GE standard service rate, and an ITU OTL 4.4OTU4 standard service rate.
The detection module comprises a detection unit, a sending unit and a receiving unit;
the detection unit is used for starting system initialization according to the first reference clock, the system defaults to correspondingly start a first working mode, and sends a first error code test or Nth error code test instruction to the sending unit according to the operation instruction, wherein if the operation instruction is to carry out the Nth error code test, the system is switched to a corresponding Nth reference clock and an Nth working mode;
the sending unit is connected with the synchronous adjusting unit and used for sending a corresponding pseudo-random code sequence and a code type signal for testing to the input interface according to a received first error code test or Nth error code test instruction;
the receiving unit is connected with the synchronous adjusting unit and used for receiving the operation result sent by the output interface, acquiring error code data according to the operation result and sending the error code data to the detecting unit.
The sending unit comprises a code pattern generating subunit, the code pattern generating subunit is connected with the synchronous adjusting unit and is used for sending a corresponding pseudo-random code sequence and a code pattern signal for testing to the input interface, and the synchronous adjusting unit delays the pseudo-random code sequence so as to synchronize the pseudo-random code sequence with the code pattern signal.
The receiving unit comprises a code pattern detection subunit and an alarm monitoring subunit, the code pattern detection subunit is connected with the synchronous adjusting unit and is used for receiving the operation result sent by the output interface, analyzing error code data according to the operation result and sending the error code data and the code pattern signal subjected to delay synchronization to the detecting unit, and the detecting unit analyzes the error code data and compares the analysis result with the code pattern signal subjected to delay synchronization for output; and the alarm monitoring subunit is used for analyzing alarm data according to the error code data and sending the alarm data to the detection unit.
The error data includes an error count, a current error rate, and an error alarm.
The alarm data includes a received signal loss alarm and a received signal loss-of-lock alarm.
The priority of the alarm data is higher than that of the error code data.
The control module comprises a micro control unit and an FPGA (field programmable gate array), the micro control unit realizes access control on the detection unit through the FPGA and realizes data interaction between the user terminal and the detection module; the FPGA is used for realizing the conversion of the communication protocol between the micro control unit and the detection unit.
In this embodiment, an MDIO communication protocol is adopted between the FPGA and the detection unit, and an SPI communication protocol is adopted between the micro control unit and the FPGA; the micro control unit and the detection unit can not be directly communicated, so that the FPGA realizes the mutual conversion between an MDIO communication protocol and an SPI communication protocol, and further realizes the data interaction between the user terminal and the detection unit.
The power supply module is used for supplying power to the detection module.
A test method of a multi-rate error code test device comprises the following steps:
s01: the clock crystal oscillator module generates a first reference clock by default;
s02: the detection module judges whether the first reference clock is ready, if not, the system fails to start, the step returns to the step S01, and if the first reference clock is ready, the step S03 is carried out;
s03: the detection module starts system initialization, and the system defaults to correspondingly start a first working mode;
s04: the detection module judges whether the system initialization is successful, if not, the system start is failed, the step is returned to S01, and if the system initialization is successful, the step is carried out S05;
s05: the detection module waits for an operation instruction of the user terminal and judges whether a first error code test is carried out, if so, the step S06 is carried out, and if not, the step S07 is carried out;
s06: if the first error code test is carried out, the detection module configures a first working mode of the system;
s07: if not, the detection module judges whether to perform the Nth error code test, if not, the step S05 is returned, if so, the clock module switches the Nth reference clock, and the detection module configures the Nth working mode of the system;
s08: the detection module sends a pseudo-random code sequence and a code pattern signal for testing to the input interface, the synchronous adjustment unit delays the pseudo-random code sequence so as to enable the pseudo-random code sequence to be synchronous with the code pattern signal, the optical module receives the pseudo-random code sequence and the code pattern signal and operates, and the signal shaping module adjusts the pseudo-random code sequence;
s09: the detection module receives an operation result sent by an output interface, acquires error code data from the operation result, analyzes the error code data, and compares and outputs the analysis result with the code pattern signal subjected to delay synchronization;
s10: the user terminal inquires error code data through the control module;
wherein, N is a natural number.
Specifically, the operations related to the detection modules in steps S02 to S09 are performed by the detection unit;
the specific operation flow of step S08 is that the detection unit starts the transmission unit, the code pattern generation subunit in the transmission unit transmits the pseudo random code sequence and the code pattern signal for testing to the input interface, the synchronization adjustment unit delays the pseudo random code sequence to synchronize with the code pattern signal, and the optical module receives the pseudo random code sequence and the code pattern signal and operates;
the specific operation flow of step S09 is that the receiving unit receives the operation result sent by the output interface, the code pattern detecting subunit collects error code data from the operation result, and sends the error code data and the code pattern signal subjected to delay synchronization to the detecting unit, the detecting unit analyzes the error code data, and compares the analysis result with the code pattern signal subjected to delay synchronization for output, the alarm monitoring subunit analyzes alarm data according to the error code data, and sends the alarm data to the detecting unit;
in step S10, the error data queried by the user terminal through the control module includes an error count, a current error rate, and an error alarm, and may also query alarm data including a received signal loss alarm and a received signal out-of-lock alarm.
The detection unit adopts a special error code test chip which is manufactured by Microsmi and has the model of VSC8248, the working principle and the electrical connection relation of the detection unit are the prior known technology, and the description is omitted.
In the operation process of the light module, the step S09 and the step S10 are synchronously operated in real time.
In step S10, if the alarm monitoring subunit reaches the alarm data, that is, the received signal loss alarm and the received signal out-of-lock alarm, the code pattern detection subunit in step S09 stops analyzing and updating the error code data until the alarm data disappears.
When the received signal loss alarm and the received signal out-of-lock alarm are generated, the received signal loss object can be locked immediately, and the influence of the received signal loss on the acquisition of error code data is reduced.
In step S10, if the user terminal queries the alarm data, the user terminal may locate the faulty object according to the received signal loss alarm and the received signal loss-of-lock alarm information, where the object is the pseudo random code sequence running in the optical module.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (5)
1. A multi-rate error code testing apparatus, characterized by: the system comprises a user terminal, a control module, a detection module, a clock crystal oscillator module, a signal shaping module and an optical module;
the user terminal is used for sending an operation instruction to the detection module through the control module and receiving error code data sent by the detection module;
the clock crystal oscillator module is used for generating a first reference clock or an Nth reference clock, and when the system is started, the first reference clock is generated by default;
the detection module comprises a synchronous adjusting unit, a first working mode is started by default according to the system initialization started by the first reference clock, a first error code test or an Nth error code test is carried out according to the operation instruction, a corresponding pseudo random code sequence and a code pattern signal used for testing are sent to the optical module, the synchronous adjusting unit is used for delaying the pseudo random code sequence so as to enable the pseudo random code sequence to be synchronous with the code pattern signal, if the operation instruction is to carry out the first error code test, the detection module configures the first working mode of the system, and if the operation instruction is to carry out the Nth error code test, the system is switched to a corresponding Nth reference clock and configures the Nth working mode of the system; the system is also used for receiving an operation result sent by an optical module, acquiring error code data from the operation result, analyzing the error code data, and comparing and outputting the analysis result and the code pattern signal subjected to delay synchronization;
wherein, N is a natural number;
the optical module comprises an input interface, a variable optical attenuation unit and an output interface, wherein the input interface is used for receiving the pseudo random code sequence, and after the pseudo random code sequence is operated by the variable optical attenuation unit, an operation result is sent to the detection module through the output interface;
the signal shaping module is arranged between the detection module and the optical module, and the signal shaping module is arranged in a multi-path manner and is used for adjusting the rising and falling time and the output amplitude of a data signal between the detection module and the optical module;
the detection module comprises a detection unit, a sending unit and a receiving unit;
the detection unit is used for starting system initialization according to the first reference clock, the system defaults to correspondingly start a first working mode, and sends a first error code test or an Nth error code test instruction to the sending unit according to the operation instruction, wherein if the operation instruction is to carry out the Nth error code test, the system is switched to a corresponding Nth reference clock and an Nth working mode;
the sending unit is connected with the synchronous adjusting unit and used for sending a corresponding pseudo-random code sequence and a code type signal for testing to the input interface according to a received first error code test or Nth error code test instruction;
the receiving unit is connected with the synchronous adjusting unit and used for receiving the operation result sent by the output interface, acquiring error code data according to the operation result, sending the error code data to the detecting unit, and comparing and outputting the analysis result and the code pattern signal subjected to delay synchronization;
the receiving unit comprises a code pattern detection subunit and an alarm monitoring subunit, the code pattern detection subunit is connected with the synchronous adjusting unit and is used for receiving the operation result sent by the output interface, acquiring error code data according to the operation result and sending the error code data and the code pattern signal subjected to delay synchronization to the detecting unit, and the detecting unit analyzes the error code data and compares and outputs the analysis result and the code pattern signal subjected to delay synchronization; the alarm monitoring subunit is used for analyzing alarm data according to the error code data and sending the alarm data to the detection unit;
the error code data comprises error code counting, current error code rate and error code warning;
the alarm data comprises a received signal loss alarm and a received signal loss-of-lock alarm;
if the alarm monitoring subunit receives the alarm data, namely the received signal loss alarm and the received signal loss-of-lock alarm, the code pattern detection subunit stops analyzing and updating the error code data until the alarm data disappears.
2. A multi-rate error code testing device according to claim 1, characterized in that: the sending unit comprises a code pattern generating subunit, the code pattern generating subunit is connected with the synchronous adjusting unit and is used for sending a corresponding pseudo-random code sequence and a code pattern signal for testing to the input interface, and the synchronous adjusting unit delays the pseudo-random code sequence so as to synchronize the pseudo-random code sequence with the code pattern signal.
3. A multi-rate error code testing device according to claim 1, characterized in that: the priority of the alarm data is higher than that of the error code data.
4. A multi-rate error code testing apparatus according to claim 1, wherein: the control module comprises a micro control unit and an FPGA (field programmable gate array), the micro control unit realizes access control on the detection unit through the FPGA and realizes data interaction between the user terminal and the detection module; the FPGA is used for realizing the conversion of the communication protocol between the micro control unit and the detection unit.
5. A test method of a multi-rate error code test device is characterized by comprising the following steps:
s01: the clock crystal oscillator module generates a first reference clock by default;
s02: the detection module judges whether the first reference clock is ready, if not, the system fails to start, the step returns to the step S01, and if the first reference clock is ready, the step S03 is carried out;
s03: the detection module starts system initialization, and the system defaults to correspondingly start a first working mode;
s04: the detection module judges whether the system initialization is successful, if not, the system start is failed, the step is returned to S01, and if the system initialization is successful, the step is carried out S05;
s05: the detection module waits for an operation instruction of the user terminal and judges whether a first error code test is carried out, if so, the step S06 is carried out, and if not, the step S07 is carried out;
s06: if the first error code test is carried out, the detection module configures a first working mode of the system;
s07: if not, the detection module judges whether to perform the Nth error code test, if not, the step S05 is returned, if so, the clock module switches the Nth reference clock, and the detection module configures the Nth working mode of the system;
s08: the detection module sends a pseudo-random code sequence and a code pattern signal for testing to the input interface, the synchronous adjustment unit delays the pseudo-random code sequence so as to enable the pseudo-random code sequence to be synchronous with the code pattern signal, the optical module receives the pseudo-random code sequence and the code pattern signal and operates, and the signal shaping module adjusts the pseudo-random code sequence;
s09: the detection module receives an operation result sent by an output interface, acquires error code data from the operation result, analyzes the error code data, and compares and outputs the analysis result with the code pattern signal subjected to delay synchronization;
s10: the user terminal inquires error code data through the control module;
wherein, the N is a natural number.
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| CN201341143Y (en) * | 2007-11-24 | 2009-11-04 | 苏州旭创科技有限公司 | High-speed digital communication error code tester |
| CN101895353A (en) * | 2010-07-07 | 2010-11-24 | 东莞市铭普实业有限公司 | Multi-speed bite error analysis and detecting instrument capable of detecting four units |
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| CN201341143Y (en) * | 2007-11-24 | 2009-11-04 | 苏州旭创科技有限公司 | High-speed digital communication error code tester |
| CN101895353A (en) * | 2010-07-07 | 2010-11-24 | 东莞市铭普实业有限公司 | Multi-speed bite error analysis and detecting instrument capable of detecting four units |
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