CN109192823A - A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof - Google Patents
A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof Download PDFInfo
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- CN109192823A CN109192823A CN201811135614.5A CN201811135614A CN109192823A CN 109192823 A CN109192823 A CN 109192823A CN 201811135614 A CN201811135614 A CN 201811135614A CN 109192823 A CN109192823 A CN 109192823A
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- 238000002360 preparation method Methods 0.000 title description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 107
- 239000002184 metal Substances 0.000 claims abstract description 107
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 31
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 9
- 238000005566 electron beam evaporation Methods 0.000 claims abstract description 4
- 150000002739 metals Chemical class 0.000 claims abstract description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 22
- 229910052697 platinum Inorganic materials 0.000 claims description 22
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000012670 alkaline solution Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 230000003139 buffering effect Effects 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000009514 concussion Effects 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 229920003023 plastic Polymers 0.000 claims description 3
- 229910001220 stainless steel Inorganic materials 0.000 claims description 3
- 239000010935 stainless steel Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000003698 laser cutting Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract description 19
- 239000005416 organic matter Substances 0.000 abstract description 3
- 239000010931 gold Substances 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical group 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- USHAGKDGDHPEEY-UHFFFAOYSA-L potassium persulfate Chemical compound [K+].[K+].[O-]S(=O)(=O)OOS([O-])(=O)=O USHAGKDGDHPEEY-UHFFFAOYSA-L 0.000 description 1
- 235000019394 potassium persulphate Nutrition 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a kind of production methods of light emitting diode (LED) chip with vertical structure, including provide light emitting structure, and the light emitting structure includes the first substrate, the first semiconductor layer, active layer, the second semiconductor layer and metallic reflector;The first bonding buffer layer and the first bonding metal layer are sequentially formed on metallic reflector;The second bonding buffer layer and the second bonding metal layer are sequentially formed on the second substrate;It binds together the first bonding metal layer and the bonding of the second bonding layer metals to form connection;Remove the first substrate;Hard mask is placed in the surface of the first semiconductor layer, first electrode is formed using the method for electron beam evaporation or magnetron sputtering on the first semiconductor layer;Form single light emitting diode (LED) chip with vertical structure.Correspondingly, the present invention also provides a kind of light emitting diode (LED) chip with vertical structure.Production method of the invention does not need to be improved production efficiency and cost of manufacture using photoetching process, reduced pollution of the organic matter generated in photoetching process to environment.
Description
Technical field
The present invention relates to LED technology fields more particularly to a kind of light emitting diode (LED) chip with vertical structure and preparation method thereof.
Background technique
LED is increasingly valued by people as a kind of novel green illumination light source, with energy conservation and environmental protection, is shone
Efficiently, many advantages, such as antistatic, long service life, various illumination places are applied to.Existing LED chip is broadly divided into just
Assembling structure, inverted structure and vertical structure three categories.A kind of photoetching can be all used in the production method of three categories conventional LED chip
Technique.Photoetching process is an important step in process for fabrication of semiconductor device, and the step is using exposure and imaging in photoetching
Geometric figure structure is portrayed on glue-line, then by etching technics by the pattern transfer on photomask on substrate.
Photoetching process includes coating photoresist, exposure and imaging these three steps, is exposure mask to produce using photoresist
The film layer of various shapes needed.Wherein, some chemical reagent be will use in three steps of photoetching process, if photoresist is one
High-molecular compound is planted, the developer solution used in developing process is a kind of alkali electroless reagent, and it is expensive, at high cost, no
Correct recovery processing can also pollute our environment.For these problems, the invention patent provides a kind of system of innovation
Method is made, is a kind of manufacturing method of unglazed carving technology in full manufacturing process.This manufacturing method is primarily directed to vertical structure
LED chip because light emitting diode (LED) chip with vertical structure structure has the characteristics that high directivity be a kind of film perpendicular on horizontal plane
The cumulative structure of layer.This design feature is suitable for the implementation of the non-lithography manufacturing method of the present invention.
Summary of the invention
Technical problem to be solved by the present invention lies in provide a kind of production method of light emitting diode (LED) chip with vertical structure, do not need
Photoetching is carried out to chip.
Technical problem to be solved by the present invention lies in provide a kind of light emitting diode (LED) chip with vertical structure, structure is simple.
In order to solve the above-mentioned technical problems, the present invention provides a kind of production methods of light emitting diode (LED) chip with vertical structure, comprising:
Light emitting structure is provided, the light emitting structure includes the first substrate, the first semiconductor layer, active layer, the second semiconductor
Layer and metallic reflector;
The first bonding buffer layer and the first bonding metal layer are sequentially formed on metallic reflector;
The second bonding buffer layer and the second bonding metal layer are sequentially formed on the second substrate;
It binds together the first bonding metal layer and the bonding of the second bonding layer metals to form connection;
Remove the first substrate;
Hard mask is placed in the surface of the first semiconductor layer, using the method for electron beam evaporation or magnetron sputtering first
First electrode is formed on semiconductor layer, wherein the hard mask is equipped with the through-hole to match with first electrode size and shape;
Using the second substrate of laser cutting and light emitting structure, single light emitting diode (LED) chip with vertical structure is formed.
As an improvement of the above scheme, the first bonding buffer layer and/or the second bonding buffer layer by Cr, Ni, Ti and
One or more of Pt is made.
As an improvement of the above scheme, the structure of the first bonding buffer layer and/or the second bonding buffer layer is Cr/
Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/Pt or Cr/Ti/Pt/Ni/Pt.
As an improvement of the above scheme, first bonding metal layer and/or the second bonding metal layer by Au or Sn or
AuSn is made.
As an improvement of the above scheme, using the method for thermocompression bonding binding that the first bonding metal layer and the second bonding is golden
Belong to layer to bind together to form connection, wherein pressure 900-1400kg, temperature are 280-300 DEG C, time 10-30min.
As an improvement of the above scheme, the hard mask is aluminium sheet, stainless steel plate, glass or plastics.
As an improvement of the above scheme, it after removing the first substrate, is formed before first electrode, further includes following step
It is rapid:
Light emitting structure is placed in the alkaline solution that temperature is 60-80 DEG C and is shaken, the concussion time is 3-7 minutes;
Wash with water light emitting structure;
Light emitting structure is spin-dried for.
Correspondingly, it the present invention also provides a kind of light emitting diode (LED) chip with vertical structure, including the second bonding buffer layer, is sequentially arranged in
The second bonding metal layer, the first bonding metal layer, the first bonding buffer layer, metallic reflector, the on second bonding buffer layer
Two semiconductor layers, active layer, the first semiconductor layer and first electrode.
As an improvement of the above scheme, the first bonding buffer layer and/or the second bonding buffer layer by Cr, Ni, Ti and
One or more of Pt is made.
As an improvement of the above scheme, the structure of the first bonding buffer layer and/or the second bonding buffer layer is Cr/
Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/Pt or Cr/Ti/Pt/Ni/Pt.
The invention has the following beneficial effects:
The present invention is improved by the production method to light emitting diode (LED) chip with vertical structure, and each important film layer is carried out layer stackup
The advantages of mode added forms integrated vertical chip big circular slice, recycles laser that can cut gallium nitride with a step, realizes vertical
The physical separation of fabric chip small size, overall process do not use photoetching process, eliminate numerous in conventional LED chips manufacturing process
Miscellaneous photoetching process improves production efficiency and cost of manufacture, reduces pollution of the organic matter generated in photoetching process to environment,
Really realize environmentally protective light source.
Detailed description of the invention
Fig. 1 is the production flow diagram of light emitting diode (LED) chip with vertical structure of the present invention;
Fig. 2 is the structural schematic diagram of light emitting diode (LED) chip with vertical structure of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, the present invention is made into one below in conjunction with attached drawing
Step ground detailed description.
It is the production flow diagram of light emitting diode (LED) chip with vertical structure of the present invention, a kind of vertical junction provided by the invention referring to Fig. 1, Fig. 1
The production method of structure LED chip, comprising the following steps:
S101, light emitting structure is provided, the light emitting structure includes the first substrate, the first semiconductor layer, active layer, the second half
Conductor layer and metallic reflector.
The material of first substrate can be sapphire, silicon carbide or silicon, or other semiconductor materials, this hair
The first bright substrate preferentially selects Sapphire Substrate.
It is grown on substrate using MOCVD technique and forms epitaxial layer.The epitaxial layer includes first of setting on substrate
Active layer on the first semiconductor layer is arranged in semiconductor layer, and the second semiconductor layer being arranged on active layer.The present invention
The first semiconductor layer be n type gallium nitride layer, active layer is multiple quantum well layer, and the second semiconductor layer is p-type gallium nitride layer.
Metallic reflector is formed on the second semiconductor layer using the method for magnetron sputtering or vapor deposition, in the ring of nitrogen protection
By furnace tube high temperature annealing or the high annealing of quick anneal oven under border, form metallic reflector with the second semiconductor layer good
Good Ohmic contact.
The metallic reflector is made of one or more of Al, Ag and Ni.
It should be noted that the light emitting structure further includes the buffering being arranged between the first substrate and the first semiconductor layer
Layer.The buffer layer is nitride buffer layer.
S102, the first bonding buffer layer and the first bonding metal layer are sequentially formed on metallic reflector.
The first bonding buffer layer is formed on metallic reflector using the method for magnetron sputtering or vapor deposition.Of the invention first
The stress that bonding buffer layer is used to generate when eliminating the first bonding metal layer of binding and the second bonding metal layer.In addition, of the invention
First bonding buffer layer the metal of the first bonding metal layer and the second bonding metal layer can also be prevented excessive, due to the first key
Metal layer and the second metal bonding layer are made of the metal of low melting point, and when binding bonding, low-melting-point metal is easy to overflow.
Specifically, the first bonding buffer layer is made of one or more of Cr, Ni, Ti and Pt.Of the invention
One bonding buffer layer is made of the low metal of above-mentioned resistivity, can not only be eliminated the stress generated when bonding binding, be prevented
Metal overflows, and can also reduce the voltage of chip.
Preferably, the structure of the first bonding buffer layer is Cr/Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/Pt
Or Cr/Ti/Pt/Ni/Pt.
First bonding metal layer is formed on the first bonding buffer layer using the method for magnetron sputtering or vapor deposition.Described first
Bonding metal layer and/or the second bonding metal layer are made of Au or Sn or AuSn.
S103, the second bonding buffer layer and the second bonding metal layer are sequentially formed on the second substrate.
The material of second substrate can be sapphire, silicon carbide or silicon, or other semiconductor materials, this hair
The second bright substrate preferentially selects silicon substrate.
The second bonding buffer layer is formed on the second substrate using the method for magnetron sputtering or vapor deposition.The present invention second is bonded
Buffer layer is used for the stress generated when eliminating the first bonding metal layer of binding and the second bonding metal layer.In addition, of the invention
Two bonding buffer layers can also prevent the metal of the first bonding metal layer and the second bonding metal layer excessive, due to the first bonding gold
Belong to layer and the second metal bonding layer is made of the metal of low melting point, when binding bonding, low-melting-point metal is easy to overflow.
Specifically, the second bonding buffer layer is made of one or more of Cr, Ni, Ti and Pt.Of the invention
Two bonding buffer layers are made of the low metal of above-mentioned resistivity, can not only be eliminated the stress generated when bonding binding, be prevented
Metal overflows, and can also reduce the voltage of chip.
Preferably, the structure of the second bonding buffer layer is Cr/Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/Pt
Or Cr/Ti/Pt/Ni/Pt.
Second bonding metal layer is formed on the second bonding buffer layer using the method for magnetron sputtering or vapor deposition.Described first
Bonding metal layer and/or the second bonding metal layer are made of Au or Sn or AuSn.
S104, it binds together the first bonding metal layer and the bonding of the second bonding layer metals to form connection.
The first bonding metal layer and the second bonding metal layer are bound together and to be formed using the method that thermocompression bonding is bound
Connection, wherein pressure 900-1400kg, temperature are 280-300 DEG C, time 10-30min.In order to eliminate stress, temperature from
Room temperature is progressively heated at 280-300 DEG C, after the completion of bonding binding, temperature is gradually decreased for after room temperature, pressure is removed.
Specifically, the metal meeting when bonding temperature is higher than 300 DEG C, in the first bonding metal layer and the second bonding metal layer
Excessive spilling is come, and sticks on the side wall of light emitting structure, causes chip that short circuit occurs;When bonding temperature is less than 280 DEG C, the
Metal in one bonding metal layer and the second bonding metal layer cannot melt, it is difficult to carry out bonding binding.Work as bonding pressure
When less than 900kg, can there are gap and micropore between the first bonding metal layer and the second metal bonding layer, the two cannot be completely
It links together, will increase the voltage of chip;When bonding pressure is greater than 1400kg, the pressure mistake that is applied on light emitting structure
Greatly, it is broken light emitting structure, influences the photoelectric properties of light emitting structure, in addition, pressure is excessive to will increase the first bond wire
The spill-out of metal in layer and the second metal bonding layer causes chip short-circuit, further, the first bonding metal layer and the second key
The thickness of metal layer can be reduced, and influence the connection of the two.
Preferably, bonding temperature is 280 DEG C, 285 DEG C, 290 DEG C, 295 DEG C or 300 DEG C;Bonding pressure be 900kg,
950kg, 1000kg, 1050kg, 1100kg, 1150kg, 1200kg, 1250kg, 1300kg, 1350kg or 1400kg.
S105, the first substrate of removal.
The first substrate of removing is used a laser to, buffer layer is exposed.It further include following step after removing the first substrate
It is rapid:
Large area etching, etching depth to the first semiconductor layer are carried out to buffer layer using inductively coupled plasma method;
Processing is patterned to the first semiconductor layer, its surface is made to form irregular, not of uniform size spike, is improved
The light extraction efficiency of light emitting structure.
It is shaken specifically, light emitting structure is placed in the alkaline solution that temperature is 60-80 DEG C, the concussion time is 3-
7 minutes, light emitting structure is then washed with water, is finally spin-dried for light emitting structure.
Wherein, the alkaline solution is potassium hydroxide and/or potassium peroxydisulfate.In order to improve roughening efficiency, while not damaging again
Hurt light emitting structure, the concentration of the alkaline solution is 10-15%.
S106, the surface that hard mask is placed in the first semiconductor layer, using the method for electron beam evaporation or magnetron sputtering
First electrode is formed on the first semiconductor layer, wherein the hard mask is equipped with to match with first electrode size and shape
Through-hole.
Preferably, the hard mask be aluminium sheet, stainless steel plate, glass or plastics, but not limited to this.
The electrode of existing chip is all made of photoetching process to make, and the hard mask that the present invention uses is one and has designed
The mold of shape is put into inside board when electrode evaporation with light emitting structure together, and hard mask can be recycled.
S107, the light emitting diode (LED) chip with vertical structure for forming single.
It is thinned specifically, the second substrate is carried out grinding, using laser by increasing the method for laser energy to second
Substrate carries out regular separation by laser, forms single light emitting diode (LED) chip with vertical structure.
The present invention is improved by the production method to light emitting diode (LED) chip with vertical structure, and each important film layer is carried out layer stackup
The advantages of mode added forms integrated vertical chip big circular slice, recycles laser that can cut gallium nitride with a step, realizes vertical
The physical separation of fabric chip small size, overall process do not use photoetching process, eliminate numerous in conventional LED chips manufacturing process
Miscellaneous photoetching process improves production efficiency and cost of manufacture, reduces pollution of the organic matter generated in photoetching process to environment,
Really realize environmentally protective light source.
Specifically, production method of the invention passes through the first bonding buffer layer, the first metal bonding layer, the second bonding first
The mutual cooperation of buffer layer and the second metal bonding layer enables the second metal bonding layer to have and is directly superimposed upon the first metal bonding
On layer, it is possible to reduce a photoetching process, secondly, the present invention to form first electrode using hard mask to be deposited, it is possible to reduce
Photoetching process, again, the present invention use a laser to the second substrate of cutting and light emitting structure, form single vertical structure LED
Chip reduces by a photoetching process again.If directlying adopt laser to cut the second substrate and light emitting structure, the first metallic bond
The metal closed in layer and the second metal bonding layer easily adheres on the side wall of chip, causes to leak electricity, but the present invention passes through to be formed
First bonding buffer layer and second is bonded buffer layer to protect the first bonding metal layer and the second bonding metal layer, and chip is avoided to send out
Raw electric leakage, from without carrying out photoetching process.
Correspondingly, as shown in Fig. 2, the present invention also provides a kind of light emitting diode (LED) chip with vertical structure, including the second bonding buffer layer
10, the second bonding metal layer 20, the first bonding metal layer 30, first being sequentially arranged on the second bonding buffer layer 10 are bonded buffering
Layer 40, metallic reflector 50, the second semiconductor layer 60, active layer 70, the first semiconductor layer 80 and first electrode 90.
First bonding buffer layer 40 of the invention is for eliminating the first bonding metal layer 30 of binding and the second bonding metal layer
The stress generated when 20.In addition, the first bonding buffer layer 40 of the invention can also prevent the first bonding metal layer 30 and second
The metal of bonding metal layer 20 is excessive, since the first bonding metal layer 30 and the second metal bonding layer 20 are by the made of metal of low melting point
At when binding bonding, low-melting-point metal is easy to overflow.
Specifically, the first bonding buffer layer 40 is made of one or more of Cr, Ni, Ti and Pt.Of the invention
First bonding buffer layer is made of the low metal of above-mentioned resistivity, can not only be eliminated the stress generated when bonding binding, be prevented
Only metal overflows, and can also reduce the voltage of chip.
Preferably, the structure of the first bonding buffer layer 40 is Cr/Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/
Pt or Cr/Ti/Pt/Ni/Pt.
The present invention second is bonded buffer layer 10 for eliminating the first bonding metal layer 30 of binding and the second bonding metal layer 20
When the stress that generates.In addition, the second bonding buffer layer 10 of the invention can also prevent the first bonding metal layer 30 and the second key
The metal of metal layer 20 is excessive, since the first bonding metal layer 30 and the second metal bonding layer 20 are by the made of metal of low melting point
At when binding bonding, low-melting-point metal is easy to overflow.
Specifically, the second bonding buffer layer 10 is made of one or more of Cr, Ni, Ti and Pt.Of the invention
Second bonding buffer layer is made of the low metal of above-mentioned resistivity, can not only be eliminated the stress generated when bonding binding, be prevented
Only metal overflows, and can also reduce the voltage of chip.
Preferably, the structure of the second bonding buffer layer 10 is Cr/Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/
Pt or Cr/Ti/Pt/Ni/Pt.
First bonding metal layer 30 and/or the second bonding metal layer 20 are made of Au or Sn or AuSn.
The metallic reflector 50 is made of one or more of Al, Ag and Ni.
Light emitting diode (LED) chip with vertical structure of the invention is eliminated by the first bonding buffer layer of setting and the second bonding buffer layer
The stress generated when binding the first bonding metal layer and the second bonding metal layer.In addition, first bonding buffer layer of the invention and
Second bonding, which is changed from layer, can also prevent the metal of the first bonding metal layer and the second bonding metal layer excessive, improve the good of chip
Rate.
Further, the present invention is designed by the structure to the second bonding buffer layer, can not only be eliminated bonding and be tied up
The stress that timing generates, prevents metal from overflowing, can also reduce the voltage of chip.
Above disclosed is only a preferred embodiment of the present invention, cannot limit the power of the present invention with this certainly
Sharp range, therefore equivalent changes made in accordance with the claims of the present invention, are still within the scope of the present invention.
Claims (10)
1. a kind of production method of light emitting diode (LED) chip with vertical structure characterized by comprising
There is provided light emitting structure, the light emitting structure include the first substrate, the first semiconductor layer, active layer, the second semiconductor layer and
Metallic reflector;
The first bonding buffer layer and the first bonding metal layer are sequentially formed on metallic reflector;
The second bonding buffer layer and the second bonding metal layer are sequentially formed on the second substrate;
It binds together the first bonding metal layer and the bonding of the second bonding layer metals to form connection;
Remove the first substrate;
Hard mask is placed in the surface of the first semiconductor layer, is led using the method for electron beam evaporation or magnetron sputtering the first half
First electrode is formed on body layer, wherein the hard mask is equipped with the through-hole to match with first electrode size and shape;
Using the second substrate of laser cutting and light emitting structure, single light emitting diode (LED) chip with vertical structure is formed.
2. the production method of light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that the first bonding buffering
Layer and/or the second bonding buffer layer are made of one or more of Cr, Ni, Ti and Pt.
3. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 2, which is characterized in that the first bonding buffering
The structure of layer and/or the second bonding buffer layer is Cr/Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/Pt or Cr/Ti/Pt/
Ni/Pt。
4. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 3, which is characterized in that first bond wire
Layer and/or the second bonding metal layer are made of Au or Sn or AuSn.
5. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 4, which is characterized in that bound using thermocompression bonding
Method bind together the first bonding metal layer and the second bonding metal layer to form connection, wherein pressure 900-
1400kg, temperature are 280-300 DEG C, time 10-30min.
6. the production method of light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that the hard mask is aluminium
Plate, stainless steel plate, glass or plastics.
7. the production method of light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that remove the first substrate it
Afterwards, it is formed before first electrode, further comprising the steps of:
Light emitting structure is placed in the alkaline solution that temperature is 60-80 DEG C and is shaken, the concussion time is 3-7 minutes;
Wash with water light emitting structure;
Light emitting structure is spin-dried for.
8. a kind of light emitting diode (LED) chip with vertical structure, which is characterized in that including the second bonding buffer layer, be sequentially arranged in the second bonding buffering
The second bonding metal layer, the first bonding metal layer on layer, metallic reflector, the second semiconductor layer, have the first bonding buffer layer
Active layer, the first semiconductor layer and first electrode.
9. light emitting diode (LED) chip with vertical structure as claimed in claim 8, which is characterized in that the first bonding buffer layer and/or second
Bonding buffer layer is made of one or more of Cr, Ni, Ti and Pt.
10. light emitting diode (LED) chip with vertical structure as claimed in claim 9, which is characterized in that the first bonding buffer layer and/or the
The structure of two bonding buffer layers is Cr/Ti/Pt/Ti/Pt/Ti/Pt or Cr/Ni/Pt/Ni/Pt or Cr/Ti/Pt/Ni/Pt.
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