CN109166899B - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
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- CN109166899B CN109166899B CN201811025591.2A CN201811025591A CN109166899B CN 109166899 B CN109166899 B CN 109166899B CN 201811025591 A CN201811025591 A CN 201811025591A CN 109166899 B CN109166899 B CN 109166899B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention provides a display substrate, a manufacturing method thereof and a display device, and belongs to the technical field of display. The display substrate comprises a thin film transistor and a passivation layer covering the thin film transistor, wherein the passivation layer is provided with an organic film, and the organic film comprises a hollow part at least corresponding to the first area. By the technical scheme, the yield of the display substrate can be improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method thereof and a display device.
Background
In the prior art, when a display substrate is manufactured, after a passivation layer covering a thin film transistor is formed, an organic film is formed on the passivation layer, and a pixel electrode is formed on the organic film. The thickness of the organic film is large and reaches the micron level. The distance between the thin film transistor and the pixel electrode of the display substrate can be increased through the organic film, and the parasitic capacitance of the display substrate is reduced, so that the power consumption of the display substrate is reduced.
However, charges are easily accumulated on the organic film at the routing area of the display substrate, at the crossing position of the gate line and the data line, and once the charges are accumulated too much, the charges are discharged to generate an ESD (Electro-Static discharge) phenomenon, so that the overall yield of the display substrate is reduced.
Disclosure of Invention
The invention provides a display substrate, a manufacturing method thereof and a display device, which can improve the yield of the display substrate.
To solve the above technical problem, embodiments of the present invention provide the following technical solutions:
in one aspect, a display substrate is provided, where a routing area of the display substrate includes a first area at a crossing position of a gate line and a data line and a second area except the first area, the display substrate includes a thin film transistor and a passivation layer covering the thin film transistor, an organic film is disposed on the passivation layer, and the organic film includes a hollow portion at least corresponding to the first area.
Further, the minimum distance between the boundary of the first area and the boundary of the hollow-out part is larger than a preset threshold value.
Further, the preset threshold is 350 um.
Further, an electrostatic guide pattern is disposed between a boundary of the hollow portion and a boundary of the first region.
Furthermore, the hollowed-out part comprises a first boundary and a second boundary which are adjacent to each other, an included angle between the first boundary and the second boundary is a right angle, the electrostatic guiding pattern close to the first boundary and the second boundary comprises a first conductive pattern parallel to the first boundary, a second conductive pattern parallel to the second boundary and a conductive connecting part for connecting the first conductive pattern and the second conductive pattern, and the conductive connecting part is arc-shaped; or the conductive connecting part comprises a plurality of conductive line segments which are sequentially connected end to end, and the included angle formed by adjacent conductive line segments is an obtuse angle; or the included angle formed by the conductive connecting part and the first conductive pattern is an obtuse angle, and the included angle formed by the conductive connecting part and the second conductive pattern is an obtuse angle.
The embodiment of the invention also provides a display device which comprises the display substrate.
The embodiment of the invention also provides a manufacturing method of a display substrate, wherein the wiring area of the display substrate comprises a first area at the crossing position of the grid line and the data line and a second area except the first area, and the manufacturing method comprises the following steps:
forming a thin film transistor and a passivation layer covering the thin film transistor;
and forming an organic film on the passivation layer, wherein the organic film comprises a hollow part at least corresponding to the first area.
Further, the forming of the organic film on the passivation layer includes:
forming a layer of photosensitive organic material on the passivation layer;
exposing the organic material by utilizing a mask plate, wherein the mask plate comprises a light-tight pattern at least corresponding to the first area and a light-transmitting pattern except the light-tight pattern;
and removing the organic material shielded by the opaque pattern after development.
Further, the method further comprises:
an electrostatic guide pattern is formed between a boundary of the hollow portion and a boundary of the first region.
Further, the hollowed-out portion includes a first boundary and a second boundary which are adjacent to each other, an included angle between the first boundary and the second boundary is a right angle, and the forming of the electrostatic guiding pattern near the first boundary and the second boundary includes:
forming a first conductive pattern parallel to the first boundary, a second conductive pattern parallel to the second boundary, and a conductive connection part connecting the first conductive pattern and the second conductive pattern, wherein the conductive connection part is arc-shaped; or the conductive connecting part comprises a plurality of conductive line segments which are sequentially connected end to end, and the included angle formed by adjacent conductive line segments is an obtuse angle; or the included angle formed by the conductive connecting part and the first conductive pattern is an obtuse angle, and the included angle formed by the conductive connecting part and the second conductive pattern is an obtuse angle.
The embodiment of the invention has the following beneficial effects:
in the scheme, the organic film is not arranged at the crossing position of the grid line and the data line in the wiring area of the display substrate, so that the probability of accumulating electric charges at the crossing position of the grid line and the data line is reduced, the probability of ESD (electro-static discharge) of the display substrate in the wiring area can be reduced, and the yield of the display substrate is improved.
Drawings
FIG. 1 is a diagram illustrating a trace area of a conventional display substrate;
FIG. 2 is a schematic diagram of a conventional display substrate with ESD;
FIG. 3 is a schematic view illustrating a trace area of a display substrate according to an embodiment of the invention;
fig. 4 is a schematic view illustrating a trace area of a display substrate according to another embodiment of the invention.
Reference numerals
1 grid line
2 data line
3 organic film
4 location of ESD occurrence
5 hollowed-out part
51 first boundary
52 second boundary
6 Electrostatic guide Pattern
61 first conductive line segment
62 second conductive line segment
63 third conductive line segment
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic view of a routing area of a conventional display substrate, and as shown in fig. 1, the routing area is provided with a gate line 1 and a data line 2, wherein an organic film 3 covers a crossing position of the gate line 1 and the data line 2, a step exists at the crossing position of the gate line 1 and the data line 2, and during a coating process of the organic film 3, due to an influence of the step, charge accumulation is easily generated at the crossing position of the gate line 1 and the data line 2, and once the charge accumulation is excessive, a charge release is formed to generate an ESD phenomenon, as shown in fig. 2, 4 is a position where ESD occurs, the position where ESD occurs is generally located in a coating direction of the organic film 3, and the ESD phenomenon will cause a reduction in yield of the display substrate.
In order to solve the above problems, embodiments of the present invention provide a display substrate, a method for manufacturing the same, and a display device, which can improve the yield of the display substrate.
The embodiment of the invention provides a display substrate, wherein a wiring area of the display substrate comprises a first area at the crossing position of a grid line and a data line and a second area except the first area, the display substrate comprises a thin film transistor and a passivation layer covering the thin film transistor, an organic film is arranged on the passivation layer, and the organic film comprises a hollow part at least corresponding to the first area.
In this embodiment, in the routing area of the display substrate, the organic film is not disposed at the intersection of the gate line and the data line, so that the probability of electric charge accumulation at the intersection of the gate line and the data line is reduced, the probability of ESD occurring in the routing area of the display substrate can be reduced, and the yield of the display substrate is improved.
Further, the minimum distance between the boundary of the first area and the boundary of the hollow-out part is larger than a preset threshold value. The organic film should be disposed as far away from the first region as possible, and the farther the organic film is disposed from the first region, the lower the probability of occurrence of ESD.
Preferably, the preset threshold is 350um, that is, the minimum distance between the boundary of the setting region of the organic film and the boundary of the first region is greater than 350um, so that the distance between the setting region of the organic film and the first region is relatively long, and the probability of occurrence of ESD is greatly reduced.
In order to further reduce the electric charge accumulated in the routing area, an electrostatic guiding pattern is arranged between the boundary of the hollow part and the boundary of the first area, the electrostatic guiding pattern is made of a conductive material and is connected with a grounding point on the display substrate or a preset grounding point outside the display substrate, the electric charge accumulated in the routing area can be guided away, the condition of accumulated electric charge caused by the fluctuation of other hardware in the organic film coating process is eliminated, and the probability of ESD in the routing area is further reduced.
In a specific embodiment, the hollowed-out portion includes a first boundary and a second boundary which are adjacent to each other, an included angle between the first boundary and the second boundary is a right angle, the electrostatic guiding pattern close to the first boundary and the second boundary includes a first conductive pattern parallel to the first boundary, a second conductive pattern parallel to the second boundary, and a conductive connection portion connecting the first conductive pattern and the second conductive pattern, and the conductive connection portion is an arc; or the conductive connecting part comprises a plurality of conductive line segments which are sequentially connected end to end, and the included angle formed by adjacent conductive line segments is an obtuse angle; or the included angle formed by the conductive connecting part and the first conductive pattern is an obtuse angle, and the included angle formed by the conductive connecting part and the second conductive pattern is an obtuse angle.
Because the probability of ESD occurring in the sharp-angled area is higher, the static guiding graph is designed not to include a right angle and a sharp angle, so that static electricity can be effectively conducted away, the condition of accumulated charges caused by the fluctuation of other hardware in the organic film coating process is eliminated, and the probability of ESD occurring in the wiring area is reduced.
The display substrate of the present invention is further described with reference to the following drawings and specific embodiments:
as shown in fig. 3, the routing area of the display substrate is provided with a gate line 1 and a data line 2, the display substrate includes a first area at the intersection of the gate line 1 and the data line 2 and a second area other than the first area, in addition, the display substrate is further provided with an organic film 3, the organic film 3 includes a hollow portion 5 corresponding to the first area, wherein the corresponding meaning is that the orthographic projection of the first area on the display substrate falls into the orthographic projection of the hollow portion 5 on the display substrate. Wherein, the interval d between the border of fretwork portion 5 and the border of first region all is greater than 350um, can make the distance ratio of setting up the region of organic membrane and first region far away like this, greatly reduced takes place the probability of ESD.
In order to further reduce the charges accumulated in the trace area, as shown in fig. 4, an electrostatic guiding pattern 6 is disposed between the boundary of the hollow portion 5 and the boundary of the first area, and the electrostatic guiding pattern 6 may be connected to a ground point on the display substrate or a ground point outside the display substrate, so as to guide away the charges accumulated in the trace area. As shown in fig. 4, the hollowed-out portion 5 includes a first boundary 51 and a second boundary 52 which are adjacent to each other, an included angle between the first boundary 51 and the second boundary 52 is a right angle, the electrostatic guiding pattern 6 includes a first conductive line segment 61, a second conductive line segment 62 and a third conductive line segment 63 which are connected end to end in sequence, wherein the first conductive line segment 61 and the third conductive line segment 63 are respectively parallel to the first boundary 51 and the second boundary 52, the included angle between the first conductive line segment 61 and the second conductive line segment 62 is an obtuse angle, the included angle between the third conductive line segment 63 and the second conductive line segment 62 is an obtuse angle, since the probability of ESD occurring in the sharp-angled region is high, the electrostatic leading pattern 6 is designed not to include right angles and acute angles, and extend along the border of fretwork portion 5, both can effectively lead away the electric charge that gathers at organic film edge, can also effectively reduce the probability that takes place ESD in the line region.
In this embodiment, through designing the structure of the display substrate, the crossing position of the gate line and the data line is not provided with the organic film, so that the organic film is far away from the crossing position of the gate line and the data line, and the electrostatic guide pattern is designed to guide away the charges in time, thereby greatly reducing the probability of occurrence of ESD in the wiring area of the display substrate, and improving the product yield of the display substrate.
The embodiment of the invention also provides a display device which comprises the display substrate. The display device may be: the display device comprises a television, a display, a digital photo frame, a mobile phone, a tablet personal computer and any other product or component with a display function, wherein the display device further comprises a flexible circuit board, a printed circuit board and a back plate.
The embodiment of the invention also provides a manufacturing method of a display substrate, wherein the wiring area of the display substrate comprises a first area at the crossing position of the grid line and the data line and a second area except the first area, and the manufacturing method comprises the following steps:
forming a thin film transistor and a passivation layer covering the thin film transistor;
and forming an organic film on the passivation layer, wherein the organic film comprises a hollow part at least corresponding to the first area.
In this embodiment, in the routing area of the display substrate, the organic film is not disposed at the intersection of the gate line and the data line, so that the probability of electric charge accumulation at the intersection of the gate line and the data line is reduced, the probability of ESD occurring in the routing area of the display substrate can be reduced, and the yield of the display substrate is improved.
The shape of the organic film can be changed by improving the pattern of a mask plate for manufacturing the organic film. When the organic film is made of negative photosensitive material, the mask plate comprises an opaque pattern at least corresponding to the first area and a transparent pattern except the opaque pattern, and the forming of the organic film on the passivation layer comprises:
forming a layer of photosensitive organic material (negative photosensitive material) on the passivation layer;
exposing the organic material by utilizing a mask plate, wherein the mask plate comprises a light-tight pattern at least corresponding to the first area and a light-transmitting pattern except the light-tight pattern;
and removing the organic material shielded by the opaque pattern after development.
Of course, the organic film is not limited to be made of a negative photosensitive material, but may also be made of a positive photosensitive material, when the organic film is made of a positive photosensitive material, the mask includes a transparent pattern at least corresponding to the first region and an opaque pattern except the transparent pattern, and the forming of the organic film on the passivation layer includes:
forming a layer of photosensitive organic material (positive photosensitive material) on the passivation layer;
exposing the organic material by utilizing a mask plate, wherein the mask plate comprises a light-transmitting pattern at least corresponding to the first area and a light-tight pattern except the light-transmitting pattern;
and after development, the organic material shielded by the opaque pattern is remained, and the exposed organic material is removed.
Further, the method further comprises:
an electrostatic guide pattern is formed between a boundary of the hollow portion and a boundary of the first region.
In order to further reduce the electric charge accumulated in the routing area, an electrostatic guiding pattern is arranged between the boundary of the hollow part and the boundary of the first area, the electrostatic guiding pattern is made of a conductive material and is connected with a grounding point on the display substrate or a preset grounding point outside the display substrate, the electric charge accumulated in the routing area can be guided away, the condition of accumulated electric charge caused by the fluctuation of other hardware in the organic film coating process is eliminated, and the probability of ESD in the routing area is further reduced.
In a specific embodiment, the hollowed-out portion includes a first boundary and a second boundary that are adjacent to each other, an included angle between the first boundary and the second boundary is a right angle, and the forming the electrostatic guiding pattern near the first boundary and the second boundary includes:
forming a first conductive pattern parallel to the first boundary, a second conductive pattern parallel to the second boundary, and a conductive connection part connecting the first conductive pattern and the second conductive pattern, wherein the conductive connection part is arc-shaped; or the conductive connecting part comprises a plurality of conductive line segments which are sequentially connected end to end, and the included angle formed by adjacent conductive line segments is an obtuse angle; or the included angle formed by the conductive connecting part and the first conductive pattern is an obtuse angle, and the included angle formed by the conductive connecting part and the second conductive pattern is an obtuse angle.
Because the probability of ESD occurring in the sharp-angled area is higher, the static guiding graph is designed not to include a right angle and a sharp angle, so that static electricity can be effectively conducted away, the condition of accumulated charges caused by the fluctuation of other hardware in the organic film coating process is eliminated, and the probability of ESD occurring in the wiring area is reduced.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. The display substrate is characterized in that a wiring area of the display substrate comprises a first area and a second area, the first area is located at the position where a grid line and a data line intersect, the second area is located outside the first area, the display substrate comprises a thin film transistor and a passivation layer covering the thin film transistor, an organic film is arranged on the passivation layer, the organic film comprises a hollow-out portion at least corresponding to the first area, and an electrostatic guide pattern is arranged between the boundary of the hollow-out portion and the boundary of the first area.
2. The display substrate according to claim 1, wherein a minimum distance between a boundary of the first region and a boundary of the hollow portion is greater than a preset threshold.
3. The display substrate of claim 2, wherein the predetermined threshold is 350 um.
4. The display substrate according to claim 1, wherein the hollowed-out portion comprises a first boundary and a second boundary which are adjacent to each other, an included angle between the first boundary and the second boundary is a right angle, the electrostatic guiding pattern adjacent to the first boundary and the second boundary comprises a first conductive pattern parallel to the first boundary, a second conductive pattern parallel to the second boundary, and a conductive connection portion connecting the first conductive pattern and the second conductive pattern, and the conductive connection portion is arc-shaped; or the conductive connecting part comprises a plurality of conductive line segments which are sequentially connected end to end, and the included angle formed by adjacent conductive line segments is an obtuse angle; or the included angle formed by the conductive connecting part and the first conductive pattern is an obtuse angle, and the included angle formed by the conductive connecting part and the second conductive pattern is an obtuse angle.
5. A display device comprising the display substrate according to any one of claims 1 to 4.
6. A manufacturing method of a display substrate is characterized in that a wiring area of the display substrate comprises a first area at the crossing position of a grid line and a data line and a second area except the first area, and the manufacturing method comprises the following steps:
forming a thin film transistor and a passivation layer covering the thin film transistor;
forming an organic film on the passivation layer, the organic film including a hollowed-out portion corresponding to at least the first region; an electrostatic guide pattern is formed between a boundary of the hollow portion and a boundary of the first region.
7. The method of claim 6, wherein the forming an organic film on the passivation layer comprises:
forming a layer of photosensitive organic material on the passivation layer;
exposing the organic material by utilizing a mask plate, wherein the mask plate comprises a light-tight pattern at least corresponding to the first area and a light-transmitting pattern except the light-tight pattern;
and removing the organic material shielded by the opaque pattern after development.
8. The method of claim 6, wherein the opening comprises a first boundary and a second boundary adjacent to each other, an included angle between the first boundary and the second boundary is a right angle, and forming the electrostatic guiding pattern near the first boundary and the second boundary comprises:
forming a first conductive pattern parallel to the first boundary, a second conductive pattern parallel to the second boundary, and a conductive connection part connecting the first conductive pattern and the second conductive pattern, wherein the conductive connection part is arc-shaped; or the conductive connecting part comprises a plurality of conductive line segments which are sequentially connected end to end, and the included angle formed by adjacent conductive line segments is an obtuse angle; or the included angle formed by the conductive connecting part and the first conductive pattern is an obtuse angle, and the included angle formed by the conductive connecting part and the second conductive pattern is an obtuse angle.
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| CN201811025591.2A CN109166899B (en) | 2018-09-04 | 2018-09-04 | Display substrate, manufacturing method thereof and display device |
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| CN104704546A (en) * | 2012-10-02 | 2015-06-10 | 夏普株式会社 | Semiconductor device, and display device |
| CN105793772A (en) * | 2013-11-21 | 2016-07-20 | 夏普株式会社 | Display device |
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| CN108169962A (en) * | 2018-01-08 | 2018-06-15 | 信利（惠州）智能显示有限公司 | The method and liquid crystal display device of friction matching |
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| KR100729046B1 (en) * | 2005-12-09 | 2007-06-14 | 삼성에스디아이 주식회사 | static electricity discharge structure for organic display device and fabricating method of there |
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| CN101566765A (en) * | 2009-05-27 | 2009-10-28 | 昆山龙腾光电有限公司 | Liquid crystal display device mother board |
| CN104704546A (en) * | 2012-10-02 | 2015-06-10 | 夏普株式会社 | Semiconductor device, and display device |
| CN105793772A (en) * | 2013-11-21 | 2016-07-20 | 夏普株式会社 | Display device |
| CN107863359A (en) * | 2017-11-30 | 2018-03-30 | 武汉天马微电子有限公司 | A kind of display panel and display device |
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