CN109164864A - A kind of line construction and control method reducing LDO power supply quiescent current - Google Patents
A kind of line construction and control method reducing LDO power supply quiescent current Download PDFInfo
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- CN109164864A CN109164864A CN201811151184.6A CN201811151184A CN109164864A CN 109164864 A CN109164864 A CN 109164864A CN 201811151184 A CN201811151184 A CN 201811151184A CN 109164864 A CN109164864 A CN 109164864A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
A kind of line construction and control method for reducing LDO power supply quiescent current of the present invention, it is ensured that lesser power supply quiescent current can be obtained when working under device fully loaded transportation condition, reduce oneself power consumption, improve power efficiency when application.The line construction, including starting module, loop back control module, the power output route and Current limited Control route for reducing power supply quiescent current；Reduce the power output line construction of power supply quiescent current as power output tube using lateral PNP, when device work is under fully loaded transportation condition, substantially it can ignore the Injection Current due to the low introducing of Q1 amplification factor, greatly reduce power supply quiescent current, improve the output power efficiency of device.It is low to overcome the Semi-active suspension amplification factor based on the production of domestic Flouride-resistani acid phesphatase bipolar process, leads to the shortcomings that there are larger power supply quiescent currents in the case where heavy duty is exported.Occurs the case where end Vout voltage is higher than supply voltage Vin when Q10 prevents device from applying.
Description
Technical field
The present invention relates to IC design technical field, specially a kind of route knot for reducing LDO power supply quiescent current
Structure and control method.
Background technique
Power tube is essential comprising modules in bipolar high power LD O device chip, using Semi-active suspension as defeated
Device input and output voltage (Low Dropout voltage) can be reduced to 600mV hereinafter, even lower by power tube out.
In the prior art, as shown in Figure 1, using line of the Semi-active suspension as output power pipe for certain external model circuit
Line structure.The route is mainly made of starting module, loop back control module, power output route and Current limited Control route.Wherein,
Power output route is made of positive-negative-positive bipolar transistor Q1 (power output tube), Q3, Q4 and npn type bipolar transistor Q7, current limliting
Control line routing resistance R1, positive-negative-positive bipolar transistor Q2 and npn type bipolar transistor Q5, Q6 composition, loop control block module are removed
Loop controls route, further includes the line constructions such as band-gap reference, error amplifier.Vin is supply voltage, and Vout is output
End, ADG is adjustment end.Output voltage is adjustable, is realized by outer connecting resistance r1 and r2 partial pressure:
Vout=VADG× (r1+r2)/r1, wherein VADG=1.275V
But power output line construction has the following disadvantages: in Fig. 1
The amplification factor of Semi-active suspension is lower, and the level of country's Flouride-resistani acid phesphatase bipolar process is 10~30 at present.Even if passing through
The mode for sacrificing pressure resistance (increases the area p+ implantation concentration in manufacturing process and reinforces the control of PNP base width in layout design
System), it is also difficult to it has a distinct increment to the amplification factor of Semi-active suspension.Therefore, the Base injection of power tube (using lateral PNP)
Electric current can not be ignored, and cause device quiescent current big since Semi-active suspension amplification factor is low, especially when device works in heavily loaded item
Under part, most power supply quiescent current derives from the Base injection electric current of power tube, increases the power consumption of device itself, significantly
Reduce the power efficiency of device output.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention provides a kind of line construction for reducing LDO power supply quiescent current
And control method, it is ensured that lesser power supply quiescent current can be obtained when working under device fully loaded transportation condition, oneself power consumption is reduced, mention
Power efficiency when height application.
The present invention is to be achieved through the following technical solutions:
A kind of line construction reducing LDO power supply quiescent current, including starting module, loop back control module, reduction power supply
The power output route and Current limited Control route of quiescent current；
The power output route of the described reduction power supply quiescent current by positive-negative-positive bipolar transistor Q1, Q3, Q4, Q8 and Q9,
And R2 and npn type bipolar transistor Q7 and Q10 are formed,
The end the E emitter of positive-negative-positive bipolar transistor Q3 is connected with supply voltage Vin, and B end group pole is connected with starting module, C
Hold collector bipolar with the B end group pole of positive-negative-positive bipolar transistor Q1, the B end group pole of positive-negative-positive bipolar transistor Q4, positive-negative-positive respectively
The end the E emitter of transistor Q8, the end the E emitter of positive-negative-positive bipolar transistor Q9 are connected with one end of resistance R2；
The end the E emitter of positive-negative-positive bipolar transistor Q1 is connected with supply voltage Vin, the C-terminal of positive-negative-positive bipolar transistor Q1
Collector is connected with output end vo ut；
The end the E emitter of positive-negative-positive bipolar transistor Q4 is connected with supply voltage Vin, the C-terminal of positive-negative-positive bipolar transistor Q4
Collector respectively with the B end group pole of positive-negative-positive bipolar transistor Q9, the end positive-negative-positive bipolar transistor Q9C collector, resistance R2 it is another
One end, the B end group pole of positive-negative-positive bipolar transistor Q8 are connected with the C-terminal collector of npn type bipolar transistor Q7；
The B end group pole of npn type bipolar transistor Q7 is connected with Current limited Control route and loop back control module respectively, NPN type
The end the E emitter of bipolar transistor Q7 is connected with GND.
The C-terminal collector of positive-negative-positive bipolar transistor Q8 respectively with the B end group pole of npn type bipolar transistor Q10 and NPN type
Bipolar transistor Q10C end collector is connected, and the end the E emitter of npn type bipolar transistor Q10 is connected with output end vo ut.
Preferably, Current limited Control line routing resistance R1, positive-negative-positive bipolar transistor Q2 and the npn type bipolar transistor
Q5, Q6 composition；
The end the E emitter of positive-negative-positive bipolar transistor Q2 is connected with supply voltage Vin, the end B of positive-negative-positive bipolar transistor Q2
The base stage bipolar crystalline substance of C-terminal collector, positive-negative-positive with the B end group pole of positive-negative-positive bipolar transistor Q1, positive-negative-positive bipolar transistor Q3 respectively
The B end group pole of body pipe Q4, the end the E emitter of positive-negative-positive bipolar transistor Q8, positive-negative-positive bipolar transistor Q9 the end E emitter, electricity
One end of resistance R2 is connected with one end of resistance R1；
The other end of the R1 B end group with the C-terminal collector of npn type bipolar transistor Q5, npn type bipolar transistor Q5 respectively
Pole is extremely connected with the B end group of npn type bipolar transistor Q6；The end the E emitter of npn type bipolar transistor Q5 is connected with GND；NPN
The C-terminal collector of type bipolar transistor Q6 is connected with the B end group pole of npn type bipolar transistor Q7 and loop back control module respectively,
The end the E emitter of npn type bipolar transistor Q6 is connected with GND.
Preferably, the loop control block module includes loop control route, and is connected to loop control line road
Band-gap reference route and error amplifier.
Preferably, adjustment end ADG is provided in the loop control block module；Adjustment end ADG connects through outer connecting resistance r1
Output end vo ut is met, through outer connecting resistance r1 connection supply voltage Vin；The voltage of output end vo ut passes through outer connecting resistance r1 and r2 points
Pressure is realized adjustable.
A kind of control method reducing LDO power supply quiescent current, using line construction described in above-mentioned any one, circuit
After starting works normally, the Injection Current from positive-negative-positive bipolar transistor Q1 is double by positive-negative-positive bipolar transistor Q8 and positive-negative-positive
Gated transistors Q9 flows to GND and output end vo ut respectively, passes through control positive-negative-positive bipolar transistor Q8 and positive-negative-positive bipolar transistor
The mirroring ratios of Q9 adjust the current component of GND and output end vo ut.
Further, when load current is larger, pass through the mirror of positive-negative-positive bipolar transistor Q8 and positive-negative-positive bipolar transistor Q9
As Proportionality design, the Injection Current of positive-negative-positive bipolar transistor Q1 is passed through into the contribution to greatest extent of positive-negative-positive bipolar transistor Q8 pipe
To load.
Compared with prior art, the invention has the following beneficial technical effects:
The present invention reduces the power output line construction of power supply quiescent current using lateral PNP as power output tube, when
Device works under fully loaded transportation condition, i.e. Vin provides biggish electric current to output end vo ut by the end E of Q1, C-terminal, at this time Q1
Injection Current can flow to Vout by the path of Q8 and Q10, by designing Q9 and Q8 mirroring ratios, can ignore substantially since Q1 is put
The Injection Current of the low introducing of big multiple, greatly reduces power supply quiescent current, improves the output power efficiency of device.It overcomes
Based on domestic Flouride-resistani acid phesphatase bipolar process production Semi-active suspension amplification factor it is low, cause heavy duty export under there are larger electricity
The shortcomings that source static electric current.Wherein, Q10 effect is diode characteristic, occurs the end Vout voltage when preventing device from applying and is higher than electricity
The case where source voltage Vin.The characteristics of according to the application environment of device and device itself, can enable or short-circuit at design initial stage
Q10。
Detailed description of the invention
Fig. 1 is power tube outlet line structural circuit figure employed in certain external model circuit in the prior art.
Fig. 2 is a kind of line construction circuit diagram of reduction LDO power supply quiescent current described in present example.
Specific embodiment
Below with reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
Line construction of the present invention using lateral PNP as the reduction LDO power supply quiescent current of power output tube, including open
Dynamic model block, loop back control module, the power output route and Current limited Control route for reducing power supply quiescent current.Wherein, reduce electricity
The power output route of source static electric current is by positive-negative-positive bipolar transistor Q1, Q3, Q4, Q8, Q9, R2 and npn type bipolar transistor
Q7, Q10 composition, Current limited Control line routing resistance R1, positive-negative-positive bipolar transistor Q2 and npn type bipolar transistor Q5, Q6 composition,
Loop control block module controls route in addition to loop, further includes the line constructions such as band-gap reference, error amplifier.Vin is power supply
Voltage, Vout are output end, and ADG is adjustment end.Output voltage is adjustable, is realized by outer connecting resistance r1 and r2 partial pressure.
In the power output route of the reduction power supply quiescent current:
The end E of Q3 is connected with supply voltage Vin, and the end B is connected with starting module, the end B of C-terminal and Q1, the end B of Q4, Q8 E
End, the end E of Q9, one end of R2 are connected.
The end E of Q1 is connected with supply voltage Vin, and the C-terminal of Q1 is connected with output end vo ut.
The end E of Q4 is connected with supply voltage Vin, the C-terminal of Q4 and the end B of Q9 and C-terminal, the other end of R2, the end B of Q8, Q7
C-terminal be connected.
The end B of Q7 is connected with the C-terminal of Q6, loop back control module, and the end E of Q7 is connected with GND.
The C-terminal of Q8 is connected with the end B of Q10 and C-terminal, and the end E of Q10 is connected with output end vo ut.
In the Current limited Control route:
The end E of Q2 is connected with supply voltage Vin, the end B and the end B of Q1, the C-terminal of Q3, the end B of Q4, the end E of Q8, Q9 of Q2
The end E, one end of R2, R1 one end be connected.
The other end of R1 is connected with the end B of the C-terminal of Q5 and the end B, Q6；The end E of Q5 is connected with GND；The C-terminal of Q6 and the B of Q7
End, loop back control module are connected, and the end E is connected with GND.
One embodiment of the present invention is as shown in Figure 2.The course of work of circuit shown in Fig. 2 is analyzed below, to say
Its bright function and effect.
Power supply quiescent current line construction of the present invention is mainly by positive-negative-positive bipolar transistor Q8, Q9, Q10, NPN type
Bipolar transistor Q7, R2 composition, in which:
The end E of Q9 is connected with the end B of Q1, and the end the B end E of Q9 is shorted to be connected with the C-terminal of Q7；
The end E of Q8 is connected with the end B of Q1, and the end B of Q8 is connected with the end E of Q9, and the C-terminal of Q8 is connected with the end C-terminal E of Q10,
The end E of Q10 connects Vout；
The both ends R2 are separately connected the end E and the end B of Q8, Q9；
Vin is input supply voltage, and Vout is output end, and ADG is reference voltage adjustment end.
On line construction, Q8 and Q9 are that the end mirror B is connected with the C-terminal of Q7；
After circuit start works normally, the Injection Current from power tube Q1 flows to GND and Vout by Q8 and Q9 respectively
(i.e. the collector current of the collector current of Q8 and Q9), the current component of the two depend on the mirroring ratios of Q8 and Q9.When negative
It when load electric current is larger, is designed by the mirroring ratios of Q8 and Q9, can all be contributed the Injection Current of Q1 by Q8 pipe substantially
To load, quantization is illustrated below:
Assuming that the mirroring ratios that the amplification factor of load current 1A, Q1, Q8, Q9 are 25, Q8 and Q9 are 50:1, ignore Q3's
The Injection Current of collector current and Q4 and Q2, then:
ICQ8=IEQ8-IBQ8
Wherein:
That is:
ICQ8=37.65mA
Above-mentioned calculating is it is found that the Injection Current of Q1 is 40mA, and wherein 37.65mA contributes to output end, and only 2.35mA passes through
Q7 flows to GND.Line construction compared to Fig. 1, the line construction substantially reduce power supply quiescent current.
Above-mentioned institute's content of the discussions only shows the present invention and is used in a kind of mode applied in power output tube line construction,
Its application range is not limited by power output tube line construction in Fig. 1.
In conclusion the present invention solves the problems, such as to cause device quiescent current big since Semi-active suspension amplification factor is low,
Device oneself power consumption is reduced, device output power efficiency is improved.In addition, the removable value of thought of the invention is in other route knots
In structure, designer can be according to chip area flexible design Q9 and Q8 mirroring ratios, while can also be special according to application environment and device
Point flexibly uses the purposes of Q10.The entirely appropriate domestic Anti -irradiation line of line construction, has good economic and army in advance
Scape.
Claims (6)
1. it is a kind of reduce LDO power supply quiescent current line construction, which is characterized in that including starting module, loop back control module,
Reduce the power output route and Current limited Control route of power supply quiescent current；
The power output route of the described reduction power supply quiescent current by positive-negative-positive bipolar transistor Q1, Q3, Q4, Q8 and Q9, and
R2 and npn type bipolar transistor Q7 and Q10 composition,
The end the E emitter of positive-negative-positive bipolar transistor Q3 is connected with supply voltage Vin, and B end group pole is connected with starting module, C-terminal collection
Electrode respectively with the B end group pole of positive-negative-positive bipolar transistor Q1, the B end group pole of positive-negative-positive bipolar transistor Q4, positive-negative-positive bipolar transistor
The end the E emitter of pipe Q8, the end the E emitter of positive-negative-positive bipolar transistor Q9 are connected with one end of resistance R2；
The end the E emitter of positive-negative-positive bipolar transistor Q1 is connected with supply voltage Vin, the C-terminal current collection of positive-negative-positive bipolar transistor Q1
Pole is connected with output end vo ut；
The end the E emitter of positive-negative-positive bipolar transistor Q4 is connected with supply voltage Vin, the C-terminal current collection of positive-negative-positive bipolar transistor Q4
Pole respectively with the B end group pole of positive-negative-positive bipolar transistor Q9, the end positive-negative-positive bipolar transistor Q9C collector, resistance R2 the other end,
The B end group pole of positive-negative-positive bipolar transistor Q8 is connected with the C-terminal collector of npn type bipolar transistor Q7；
The B end group pole of npn type bipolar transistor Q7 is connected with Current limited Control route and loop back control module respectively, bipolar npn
The end the E emitter of transistor Q7 is connected with GND；
The C-terminal collector of positive-negative-positive bipolar transistor Q8 respectively with the B end group pole of npn type bipolar transistor Q10 and bipolar npn
Transistor Q10C end collector is connected, and the end the E emitter of npn type bipolar transistor Q10 is connected with output end vo ut.
2. a kind of line construction for reducing LDO power supply quiescent current according to claim 1, which is characterized in that described
Current limited Control line routing resistance R1, positive-negative-positive bipolar transistor Q2 and npn type bipolar transistor Q5, Q6 composition；
The end the E emitter of positive-negative-positive bipolar transistor Q2 is connected with supply voltage Vin, the B end group pole of positive-negative-positive bipolar transistor Q2
Respectively with the B end group pole of positive-negative-positive bipolar transistor Q1, the C-terminal collector of positive-negative-positive bipolar transistor Q3, positive-negative-positive bipolar transistor
The B end group pole of Q4, the end the E emitter of positive-negative-positive bipolar transistor Q8, positive-negative-positive bipolar transistor Q9 the end E emitter, resistance R2
One end be connected with one end of resistance R1；
The other end of R1 respectively with the C-terminal collector of npn type bipolar transistor Q5, npn type bipolar transistor Q5 B end group pole and
The B end group of npn type bipolar transistor Q6 is extremely connected；The end the E emitter of npn type bipolar transistor Q5 is connected with GND；NPN type is double
The C-terminal collector of gated transistors Q6 is connected with the B end group pole of npn type bipolar transistor Q7 and loop back control module respectively, NPN type
The end the E emitter of bipolar transistor Q6 is connected with GND.
3. a kind of line construction for reducing LDO power supply quiescent current according to claim 1, which is characterized in that described
Loop control block module includes loop control route, and is connected to the band-gap reference route of loop control line road and error is put
Big device.
4. a kind of line construction for reducing LDO power supply quiescent current according to claim 1, which is characterized in that described
Adjustment end ADG is provided in loop control block module；Adjustment end ADG is through outer connecting resistance r1 connection output end vo ut, through external electricity
Hinder r1 connection supply voltage Vin；The voltage of output end vo ut is realized adjustable by outer connecting resistance r1 and r2 partial pressure.
5. a kind of control method for reducing LDO power supply quiescent current, which is characterized in that use claim 1-4 any one institute
The line construction stated, after circuit start works normally, the Injection Current from positive-negative-positive bipolar transistor Q1 is bipolar by positive-negative-positive
Transistor Q8 and positive-negative-positive bipolar transistor Q9 flow to GND and output end vo ut respectively, by controlling positive-negative-positive bipolar transistor Q8
The current component of GND and output end vo ut are adjusted with the mirroring ratios of positive-negative-positive bipolar transistor Q9.
6. a kind of control method for reducing LDO power supply quiescent current according to claim 5, which is characterized in that work as load
When electric current is larger, designed by the mirroring ratios of positive-negative-positive bipolar transistor Q8 and positive-negative-positive bipolar transistor Q9, positive-negative-positive is bipolar
The Injection Current of transistor Q1 contributes to load by positive-negative-positive bipolar transistor Q8 pipe to greatest extent.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| US8878510B2 (en) * | 2012-05-15 | 2014-11-04 | Cadence Ams Design India Private Limited | Reducing power consumption in a voltage regulator |
| CN104656733A (en) * | 2015-02-12 | 2015-05-27 | 天津大学 | LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way |
| CN204650334U (en) * | 2015-04-13 | 2015-09-16 | 南京中科微电子有限公司 | A kind of linear voltage regulator of ultra low quiescent power consumption |
| CN105468082A (en) * | 2015-12-29 | 2016-04-06 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| EP3051378A1 (en) * | 2015-01-28 | 2016-08-03 | ams AG | Low dropout regulator circuit and method for controlling a voltage of a low dropout regulator circuit |
| CN107272808A (en) * | 2017-08-11 | 2017-10-20 | 何金昌 | A kind of LDO circuit applied to integrated chip |
| US20180120879A1 (en) * | 2016-10-27 | 2018-05-03 | Qualcomm Incorporated | Voltage regulator with enhanced power supply rejection ratio and load-transient performance |
| CN108062139A (en) * | 2018-02-06 | 2018-05-22 | 上海毅栈半导体科技有限公司 | A kind of LDO circuit of the LDO circuit of ultra low quiescent power consumption and the ultra low quiescent power consumption of driving heavy load |
-
2018
- 2018-09-29 CN CN201811151184.6A patent/CN109164864B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| US8878510B2 (en) * | 2012-05-15 | 2014-11-04 | Cadence Ams Design India Private Limited | Reducing power consumption in a voltage regulator |
| EP3051378A1 (en) * | 2015-01-28 | 2016-08-03 | ams AG | Low dropout regulator circuit and method for controlling a voltage of a low dropout regulator circuit |
| CN104656733A (en) * | 2015-02-12 | 2015-05-27 | 天津大学 | LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way |
| CN204650334U (en) * | 2015-04-13 | 2015-09-16 | 南京中科微电子有限公司 | A kind of linear voltage regulator of ultra low quiescent power consumption |
| CN105468082A (en) * | 2015-12-29 | 2016-04-06 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| US20180120879A1 (en) * | 2016-10-27 | 2018-05-03 | Qualcomm Incorporated | Voltage regulator with enhanced power supply rejection ratio and load-transient performance |
| CN107272808A (en) * | 2017-08-11 | 2017-10-20 | 何金昌 | A kind of LDO circuit applied to integrated chip |
| CN108062139A (en) * | 2018-02-06 | 2018-05-22 | 上海毅栈半导体科技有限公司 | A kind of LDO circuit of the LDO circuit of ultra low quiescent power consumption and the ultra low quiescent power consumption of driving heavy load |
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