CN109143204B - Peak value holding and automatic discharging circuit of digital control ping-pong structure - Google Patents

Peak value holding and automatic discharging circuit of digital control ping-pong structure Download PDF

Info

Publication number
CN109143204B
CN109143204B CN201811047068.XA CN201811047068A CN109143204B CN 109143204 B CN109143204 B CN 109143204B CN 201811047068 A CN201811047068 A CN 201811047068A CN 109143204 B CN109143204 B CN 109143204B
Authority
CN
China
Prior art keywords
peak value
value holding
module
automatic discharging
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811047068.XA
Other languages
Chinese (zh)
Other versions
CN109143204A (en
Inventor
段发阶
李旭
蒋佳佳
傅骁
叶德超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin University
Original Assignee
Tianjin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University filed Critical Tianjin University
Priority to CN201811047068.XA priority Critical patent/CN109143204B/en
Publication of CN109143204A publication Critical patent/CN109143204A/en
Application granted granted Critical
Publication of CN109143204B publication Critical patent/CN109143204B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4861—Circuits for detection, sampling, integration or read-out
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Optical Radar Systems And Details Thereof (AREA)

Abstract

The invention relates to the field of peak value sampling measurement, and provides a digitally-controlled peak value holding and automatic discharging circuit with a ping-pong structure. The circuit can realize the holding and automatic discharging of multiple dense echo signal peak values and reduce the requirement on the conversion speed of a post-stage AD conversion circuit. The digital control ping-pong peak value holding and automatic discharging circuit comprises a rising edge detection module, a shift control module, a controller, an AD conversion module and N paths of peak value holding and automatic discharging circuits, wherein each path of peak value holding and automatic discharging circuit comprises an inverter, a transconductance type peak value holding module, a channel switch, a discharging switch and 2 driving modules. The peak value sampling method is mainly applied to peak value sampling measurement occasions.

Description

Peak value holding and automatic discharging circuit of digital control ping-pong structure
Technical Field
The invention relates to the field of peak value sampling measurement, in particular to the field of laser ranging echo peak value sampling measurement. And more particularly to peak hold and auto-discharge circuits for digitally controlled ping-pong architectures.
Background
Laser radar is widely applied to the fields of three-dimensional shape measurement, unmanned aerial vehicle obstacle avoidance, unmanned vehicles and the like from the appearance to the present, and the most prominent laser radar is applied to the unmanned vehicles in the civil field. Along with the continuous development and maturity of the unmanned technology, the indexes such as the range measurement range, the angle resolution and the range measurement precision of the laser radar are also continuously improved, in addition, the requirements of the unmanned technology on the laser radar are not limited in the aspect of distance measurement, and the identification technology of the measured object is more and more concerned by people.
However, in the laser ranging process, because the emitted laser beam is monochromatic laser, and the photoelectric detector has certain band limitation, the identification of the target cannot depend on information such as color of the target, the reflectivity of the target object can be determined only by detecting the monochromatic gray value of the reflected echo, namely the intensity of the reflected echo, and the detected object is classified according to different reflected intensities, so that the identification of the target is realized. Therefore, the laser radar should obtain the intensity information of the corresponding laser echo while obtaining the time of flight of the laser pulse.
In order to retain the echo intensity information and realize the acquisition of the echo intensity, a currently common method is to design a peak holding circuit, hold the peak value of the echo for a period of time, and perform analog-to-digital conversion (hereinafter referred to as AD conversion) to obtain the echo intensity information, thereby obtaining the monochrome gray value of the target echo. Meanwhile, the peak holding circuit should realize automatic discharge after the AD conversion is completed, ready for holding the next peak. However, when the object to be detected is a tree or a semitransparent obstacle, the same emission beam can obtain more than two echoes, and peak intensity information of not less than two echo pulses is acquired in order to ensure the accuracy of target identification. While the multiple echoes of the same transmit pulse tend to have very small time intervals, it is assumed that the time intervals of the two echoes are 20ns when the different measured objects measured by the two adjacent echoes are 3m apart. At present, the general scheme of sampling the continuous pulse peak value is to control the continuous pulse peak value through a single chip microcomputer, namely when AD conversion is completed, the single chip microcomputer controls a peak value holding circuit to discharge. In order to acquire the strength information of the multiple echoes with extremely short time intervals, extremely high requirements are put forward on the AD conversion speed and the single chip microcomputer processing speed, and more importantly, the traditional peak holding circuit can hardly hold the adjacent two pulse peaks of the multiple dense echoes. At present, researchers also propose a peak holding circuit with a digital + analog structure to solve the problem, the peak holding circuit utilizes a plurality of D flip-flop chips to realize the switching of holding channels, but the circuit structure is complex, the number of the required D flip-flop chips is large, and the D flip-flop chips are not easy to cascade.
Therefore, in order to improve the accuracy of laser radar target identification and take circuit cost, feasibility and expansibility into consideration, a digitally-controlled peak holding and automatic discharging circuit of a ping-pong structure is designed.
Disclosure of Invention
Aiming at overcoming the defects of the prior art and aiming at the characteristics of multiple times and density of laser ranging echoes, the invention aims to provide a digitally-controlled peak holding and automatic discharging circuit with a ping-pong structure. The circuit can realize the holding and automatic discharging of multiple dense echo signal peak values and reduce the requirement on the conversion speed of a post-stage AD conversion circuit. The peak value holding and automatic discharging circuit of the digital control ping-pong structure comprises a rising edge detection module, a shift control module, a controller, an AD conversion module and N paths of peak value holding and automatic discharging circuits, wherein each path of peak value holding and automatic discharging circuit comprises an inverter, a transconductance type peak value holding module, a channel switch, a discharging switch and 2 driving modules; wherein:
the rising edge detection module detects the amplified voltage pulse signal, and the output signal of the rising edge detection module enables the 1 st bit of the shift control module to output Vout1Is high;
further, the 1 st bit of the shift control module outputs Vout1The discharge switch is not conducted through an inverter and a driving module in the 1 st path of peak value holding and automatic discharge circuit, and at the moment, a transconductance type peak value holding module in the 1 st path of peak value holding and automatic discharge circuit holds a pulse peak value to obtain a peak value of the 1 st pulse and hold the peak value for a period of time;
furthermore, the rising edge detection module detects a second rising edge of the amplified voltage pulse signal, and the output signal of the second rising edge makes the 2 nd bit output V of the shift control moduleout2High, and no other bit output is changed;
further, the 2 nd bit outputs Vout2The 1 st path peak value holding and automatic discharging circuit is internally provided with another driving module, so that a channel switch in the 1 st path peak value holding and automatic discharging circuit is conducted, and a transconductance type peak value holding module in the 1 st path peak value holding and automatic discharging circuit does not receive new pulses;
further, the 2 nd bit outputs Vout2The power discharging switch in the 2 nd path peak value holding and automatic discharging circuit is not conducted through an inverter in the 2 nd path peak value holding and automatic discharging circuit and a driving module in the 2 nd path peak value holding and automatic discharging circuit, at the moment, a transconductance type peak value holding module in the 2 nd path peak value holding and automatic discharging circuit holds a pulse peak value, and the peak value of the 2 nd pulse is obtained and held for a period of time;
furthermore, the same situation occurs in the 3 rd to N th peak holding and automatic discharging circuits in turn;
and the transconductance type peak value holding module in the peak value holding and automatic discharging circuit is output through the AD conversion module.
The channel switch and the discharge switch are complementary metal oxide semiconductor switches, the phase inverter is a NOT gate circuit, and the controller is a single chip microcomputer or a programmable gate array FPGA.
The invention has the characteristics and beneficial effects that:
1) the multi-path peak value holding circuit works alternately, the defect that the traditional peak value holding circuit can only hold a single pulse peak value is overcome, the sampling of multiple times of dense pulse signal peak values is realized, and the information integrity of the pulse signals is ensured.
2) The peak values of the multiple and dense pulse signals are respectively kept by the multi-path peak value keeping circuit, so that the requirement on the conversion speed of the AD conversion circuit can be obviously reduced, the design standard of the AD conversion circuit is relaxed, and the cost is reduced.
3) The shift control module is adopted to switch the multi-path peak holding circuit, so that the cost and complexity of the circuit are greatly reduced, the anti-interference capability is stronger, and the cascade connection is easier.
Description of the drawings:
fig. 1 is a multi-path peak-hold and auto-discharge circuit of a digitally controlled ping-pong architecture.
In fig. 1, 1 is a rising edge detection module, 2 is a shift control module, 3 is an inverter, 4 is a transconductance type peak holding module, 5 is a channel switch, 6 is a discharge switch, 7 is a driving module, and 8 is a controller.
Detailed Description
The invention provides a multi-path peak holding and automatic discharging circuit of a digital control ping-pong structure, which comprises: rising edge detection module 1 (1), shift control module 2(1, the passageway that is used for control to open and close), inverter 3 (1 in every way), transconductance type peak value keeps module 4 (1 in every way), channel switch 5 (1 in every way, corresponding route does not receive the echo when switching on), discharge switch 6 (1 in every way, corresponding route keeps the electric capacity to realize discharging when switching on), drive module 7 (2 in every way), controller 8 (1).
Before measurement begins, all control output ends of a shift control module 2 are all 0, all channel switches 5 are not conducted, all discharge switches 6 are conducted, and all transconductance type peak value holding modules 4 receive pulses but do not hold pulse peak values.
After the laser echo is detected, the signal is converted into a voltage pulse signal through the transimpedance amplification module and the secondary amplification module.
Further, the rising edge detection module 1 detects the voltage pulse signal after twice amplification, and the output signal thereof makes the 1 st bit output V of the shift control moduleout1Is high.
Further, the 1 st bit of the shift control module outputs Vout1The 1 st path of inverter 3 and the driving module 7 make the discharging switch 6 not conduct, and at this time, the 1 st path of transconductance type peak value holding module 4 holds the pulse peak value, obtains the peak value of the 1 st pulse and holds for a period of time.
Further, after the 1 st path transconductance type peak value holding module 4 obtains the first pulse peak value, the rising edge detection module 1 detects the second rising edge, and the output signal thereof enables the shift control module 2 to output the 2 nd bit Vout2High and the other bit outputs are not changed.
Further, the 2 nd bit outputs Vout2The 1 st channel switch 5 is turned on by the 1 st driving module 7, and the 1 st transconductance type peak holding module 4 does not receive a new pulse.
Further, the 2 nd bit output Vout2The 2 nd path of discharge switch 6 is not conducted through the 2 nd path of inverter 3 and the 2 nd path of driving module 7, and at this time, the 2 nd path of transconductance type peak value holding module 4 holds the pulse peak value, obtains the peak value of the 2 nd pulse and holds the peak value for a period of time.
Further, the same occurs in the 3 rd to the N th routes in order.
Further, the AD conversion circuit completes AD conversion of the peak value within the time held by all the N transconductance type peak holding modules 4.
The rising edge detection module 1 can adopt a high-speed voltage comparison circuit, and the threshold voltage of the inverting input end of the high-speed voltage comparison circuit is set to be V0Positive phase input terminalThe amplitude of the amplified laser echo signal is VsWhen V is satisfieds>V0The rising edge detection module 1 detects the transmitted signal.
The shift control module 2 can adopt a shift register with high speed and serial input and parallel output, the output signal of the rising edge detection module 1 is used as the clock signal, when the rising edge of the laser echo signal is detected every time, the high level of the output end moves one bit to high position, namely when the rising edge of the laser echo signal of the nth time is detected, the front n outputs of the shift register are all high, and the switching of channels is realized.
The inverter 3 may be a not gate circuit, and obtain a value opposite to the corresponding bit output signal of the shift control module 2.
The transconductance type peak holding module 4 may adopt a transconductance type peak holding circuit, select a capacitor C with a small capacitance value as a holding capacitor, increase the charging speed, and complete the holding of the peak value in a very short time.
The channel switch 5 can be a high-speed complementary metal oxide semiconductor switch (hereinafter referred to as a CMOS switch), has extremely short turn-on and turn-off time, and realizes high-speed channel switching.
The discharge switch 6 can be a high-speed CMOS switch, has extremely short turn-on and turn-off time, assists in realizing high-speed channel switching, and quickly completes discharge of the holding capacitor in the transconductance type peak holding module 5 after AD conversion is completed.
The driving module 7 can adopt a CMOS driving chip to drive the channel switch 5 and the discharge switch 6, so as to realize high switching speed.
The controller 8 can adopt a single chip microcomputer or an FPGA and the like to control the timing control module 2, provide an enabling signal and a zero clearing signal for the timing control module, and determine the peak holding time length.
In order to achieve the above object, a two-way or multi-way peak-hold and automatic discharge circuit of a digitally controlled ping-pong architecture is devised, comprising: the device comprises 1 (1) rising edge detection module, 2(1 in each path except the 1 st path) falling edge detection module, 3 (1 in each path) monostable trigger module, 4 (1 in each path) transconductance type peak value holding module, 5 (1 in each path) channel switches and 6 (1 in each path) discharge switches.
The rising edge detection module 1 can adopt a high-speed voltage comparison circuit, and the threshold voltage of the inverting input end of the high-speed voltage comparison circuit is set to be V0Can be designed as V00.5V, the amplitude of the laser echo signal at the positive phase input end is V after amplificationsWhen V is satisfieds>V0The rising edge detection module 1 detects the transmitted signal.
The shift control module 2 can adopt a shift register with high speed and serial input and parallel output, the output signal of the rising edge detection module 1 is used as the clock signal, when the rising edge arrives, the high level moves one bit to the high level, the corresponding path discharge switch 7 is not conducted, and the previous path channel switch 6 is conducted.
The inverter 3 may be a not gate circuit, and obtain a value opposite to the corresponding bit output signal of the shift control module 2.
The transconductance type peak value holding module 4 may adopt a transconductance type peak value holding circuit, select a capacitor with a small capacitance value as a holding capacitor, improve the charging speed, complete the holding of the peak value in a very short time, and select a holding capacitor of 100 pF.
The channel switch 5 can adopt a high-speed CMOS switch, has extremely short turn-on and turn-off time, and realizes high-speed channel switching.
The discharge switch 6 can be a high-speed CMOS switch, has extremely short turn-on and turn-off time, assists in realizing high-speed channel switching, and quickly completes discharge of the holding capacitor in the transconductance type peak holding module 4 after AD conversion is completed.
The driving module 7 can adopt a CMOS driving chip to drive the channel switch 5 and the discharge switch 6, so as to realize high switching speed.
The controller 8 can adopt a single chip microcomputer or an FPGA and the like to control the timing control module 2, provide an enabling signal and a zero clearing signal for the timing control module, and determine the peak holding time length.

Claims (2)

1. The peak value holding and automatic discharging circuit of the digital control ping-pong structure is characterized by comprising a rising edge detection module, a shift control module, a controller, an AD conversion module and N paths of peak value holding and automatic discharging circuits, wherein each peak value holding and automatic discharging circuit comprises an inverter, a transconductance type peak value holding module, a channel switch, a discharging switch and 2 driving modules; wherein:
the rising edge detection module detects the amplified voltage pulse signal, and the output signal of the rising edge detection module enables the 1 st bit of the shift control module to output Vout1Is high;
the rising edge detection module adopts a high-speed voltage comparison circuit, and the threshold voltage of the inverting input end of the high-speed voltage comparison circuit is set to be V0The amplitude of the laser echo signal at the positive phase input end after amplification is VsWhen V is satisfieds>V0When the signal is transmitted, the rising edge detection module detects the transmitted signal;
further, the 1 st bit of the shift control module outputs Vout1The discharge switch is not conducted through an inverter and a driving module in the 1 st path of peak value holding and automatic discharge circuit, and at the moment, a transconductance type peak value holding module in the 1 st path of peak value holding and automatic discharge circuit holds a pulse peak value to obtain a peak value of the 1 st pulse and hold the peak value for a period of time;
furthermore, the rising edge detection module detects a second rising edge of the amplified voltage pulse signal, and the output signal of the rising edge detection module enables the 2 nd bit of the shift control module to output Vout2High, and no other bit output is changed;
further, the 2 nd bit outputs Vout2The 1 st path peak value holding and automatic discharging circuit is internally provided with another driving module, so that a channel switch in the 1 st path peak value holding and automatic discharging circuit is conducted, and a transconductance type peak value holding module in the 1 st path peak value holding and automatic discharging circuit does not receive new pulses;
further, the 2 nd bit outputs Vout2The 2 nd path peak value holding and automatic discharging circuit internal inverter and the 2 nd path peak value holding and automatic discharging circuit internal driving module are used for making the 2 nd path peak value holding and automatic discharging circuit internal discharge switch not be conducted, at this moment, the 2 nd path peak value holding and automatic discharging circuit internal transconductance type peak value holding module holds the pulse peak value, and the 2 nd pulse peak value is obtained and held for a period of time;
further, the same condition occurs in the 3 rd path to the N th path of peak holding and automatic discharging circuits in sequence;
and the transconductance type peak value holding module in the peak value holding and automatic discharging circuit is output through the AD conversion module.
2. The peak-hold and auto-discharge circuit of digitally controlled ping-pong architecture as claimed in claim 1 wherein said channel switch, said discharge switch are cmos switches, said inverter is not gate, and said controller is a single-chip or a programmable gate array FPGA.
CN201811047068.XA 2018-09-08 2018-09-08 Peak value holding and automatic discharging circuit of digital control ping-pong structure Active CN109143204B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811047068.XA CN109143204B (en) 2018-09-08 2018-09-08 Peak value holding and automatic discharging circuit of digital control ping-pong structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811047068.XA CN109143204B (en) 2018-09-08 2018-09-08 Peak value holding and automatic discharging circuit of digital control ping-pong structure

Publications (2)

Publication Number Publication Date
CN109143204A CN109143204A (en) 2019-01-04
CN109143204B true CN109143204B (en) 2022-05-20

Family

ID=64824103

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811047068.XA Active CN109143204B (en) 2018-09-08 2018-09-08 Peak value holding and automatic discharging circuit of digital control ping-pong structure

Country Status (1)

Country Link
CN (1) CN109143204B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109995242A (en) * 2019-04-08 2019-07-09 深圳市航嘉驰源电气股份有限公司 A kind of controlled resonant converter
CN113406602B (en) * 2021-05-21 2024-04-26 中山大学 Pulse peak hold circuit and control method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101222211A (en) * 2007-01-09 2008-07-16 冲电气工业株式会社 Peak-hold circuit and signal strength indicator using the peak-hold circuit
CN206349978U (en) * 2016-11-25 2017-07-21 湖北三江航天万峰科技发展有限公司 A kind of peak holding circuit of laser pulse signal
CN107255808A (en) * 2017-07-13 2017-10-17 西安理工大学 A kind of narrow pulse peak energy monitor of laser radar outgoing
CN107276569A (en) * 2017-07-19 2017-10-20 清华大学 Short pulse amplitude measurement method based on multiple pulses peak holding and realize circuit
CN209148866U (en) * 2018-09-08 2019-07-23 天津大学 The peak holding and automatic discharge circuit of numerically controlled ping-pong structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501539B2 (en) * 2001-03-15 2002-12-31 Asia Optical Co., Inc. High precision laser range finder with an automatic peak control loop

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101222211A (en) * 2007-01-09 2008-07-16 冲电气工业株式会社 Peak-hold circuit and signal strength indicator using the peak-hold circuit
CN206349978U (en) * 2016-11-25 2017-07-21 湖北三江航天万峰科技发展有限公司 A kind of peak holding circuit of laser pulse signal
CN107255808A (en) * 2017-07-13 2017-10-17 西安理工大学 A kind of narrow pulse peak energy monitor of laser radar outgoing
CN107276569A (en) * 2017-07-19 2017-10-20 清华大学 Short pulse amplitude measurement method based on multiple pulses peak holding and realize circuit
CN209148866U (en) * 2018-09-08 2019-07-23 天津大学 The peak holding and automatic discharge circuit of numerically controlled ping-pong structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
高速窄脉冲峰值保持电路设计与实现;张健;《电子设计工程》;20140531;第22卷(第9期);第117-119页 *

Also Published As

Publication number Publication date
CN109143204A (en) 2019-01-04

Similar Documents

Publication Publication Date Title
CN105652259B (en) Laser ranging readout sequence circuit and method based on Geiger mode angular position digitizer (APD) array
CN109143204B (en) Peak value holding and automatic discharging circuit of digital control ping-pong structure
CN110161519B (en) Macro-pulse photon counting laser radar
CN108008402B (en) Single photon avalanche diode detector array for laser ranging
CN109901177B (en) Method and device for improving laser radar ranging capability
WO2021233137A1 (en) Ranging method and ranging system of multi-gradient time bin
CN107632298B (en) High-sensitivity receiving circuit applied to pulse type laser radar system
WO2021213443A1 (en) Photoelectric sensing and acquisition module, photoelectric sensing and distance measurement method and distance measurement device
CN109581333A (en) Laser radar reading circuit based on the reconstruct of pulse echo ultra-high speed sampling
US11693098B2 (en) Shared sample and convert capacitor architecture
CN108614255A (en) A kind of reading circuit
WO2023103310A1 (en) Laser radar, and method and system thereof for measuring reflectivity of target
CN110658716B (en) Time-to-digital conversion system based on synchronous time sequence
CN109407075A (en) Automatic gain control circuit based on echo priori features
CN209514059U (en) Ping-pong structure peak holding and automatic discharge circuit based on simulation control
CN109521413A (en) Full wave shape suitable for laser radar obtains circuit
CN109521666B (en) Time-to-digital converter based on delay locked loop
CN109085559B (en) Table tennis structure peak value holding and automatic discharging circuit based on analog control
CN105403892A (en) Semiconductor laser distance measuring device based on switched capacitor array sampling
CN209148866U (en) The peak holding and automatic discharge circuit of numerically controlled ping-pong structure
CN113009455A (en) Method and system for improving pulse laser ranging precision
CN113765520A (en) Method for sampling full waveform of echo of multi-path high-speed ADC (analog to digital converter) sampling FPGA (field programmable gate array)
Watanabe et al. All-digital ADC/TDC using TAD architecture for highly-durable time-measurement ASIC
Xia et al. A novel TDC/ADC hybrid reconstruction ROIC for LiDAR
CN115755076A (en) Laser ranging system and method for improving distance resolution measurement capability

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant