CN113765520A - Method for sampling full waveform of echo of multi-path high-speed ADC (analog to digital converter) sampling FPGA (field programmable gate array) - Google Patents
Method for sampling full waveform of echo of multi-path high-speed ADC (analog to digital converter) sampling FPGA (field programmable gate array) Download PDFInfo
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Abstract
The method for sampling the echo full waveform of the FPGA by the multi-path high-speed ADC comprises the following steps: 1): the laser emits a pulse signal, and the laser irradiates a target to be detected to generate an echo signal; 2): the APD photoelectric searchlight converts echo signals diffusely reflected by a target to be detected into electric signals; 3): amplifying the electric signal in the step (2) by using AGC; 4): the method comprises the following steps that a plurality of paths of clock signals with the same frequency and set fixed phase difference output by a high-frequency clock source chip are simultaneously sent to a high-speed ADC to serve as sampling clocks, and sampling is simultaneously carried out by the plurality of paths of high-speed ADCs to splice sampling data of the plurality of paths of high-speed ADCs into ADC sampling data; 5): storing the spliced ADC sampling data in FIFO of the FPGA processor again; the invention realizes ADC data interpolation by adopting a multi-path ADC parallel sampling mode, realizes higher data acquisition rate similar to an ultra-high-speed ADC by adopting a high-speed ADC sampling mode, reduces design difficulty, reduces ADC cost and ensures the high-speed data sampling rate.
Description
Technical Field
The invention belongs to the field of photoelectric detection, and particularly relates to a method for sampling full waveforms of echoes of a multi-path high-speed ADC sampling FPGA.
Background
The laser scanner has the advantages of high distance measurement precision, long measurement distance and the like, and is widely applied to the fields of measurement and mapping, ground disaster monitoring, bridge and tunnel construction monitoring, auxiliary driving and the like. The time interval measurement is to calculate the distance by measuring the flight time between the laser emission pulse signal start and the echo signal stop, but the method is greatly influenced by the jitter of a pulse leading edge judging circuit of a front-end analog receiving circuit, and the precision of laser ranging is directly influenced.
In order to solve the problem, full-waveform sampling is adopted, the leading edge of the waveform is restored, the higher the point density is, the lower the waveform distortion degree is, and therefore, the higher the sampling rate is, the better the requirement is. However, the ultra-high speed ADC cargo source is affected by the technical bottleneck in China and banning abroad, the single high-speed ADC cannot meet the requirement of high-bandwidth narrow-echo pulse full-waveform acquisition, and the influence of circuit layout, the time sequence constraint source of a post-stage processing chip and the bandwidth limits the single-path acquisition data.
Disclosure of Invention
In order to overcome the existing defects, the invention aims to provide a method for realizing high-speed ADC sampling by adopting a multi-path high-speed ADC parallel multiplexing mode and generating a plurality of paths of clocks with the same frequency and fixed phase delay through a clock source so as to obtain an echo signal with high sampling density and restore the front edge of an echo with high precision.
The purpose of the invention is realized by adopting the following technical scheme. The invention provides a method for sampling full waveforms of echoes of a multi-path high-speed ADC sampling FPGA, which comprises the following steps:
1): the laser emits a pulse signal, and the laser irradiates a target to be detected to generate an echo signal;
2): the APD photoelectric searchlight converts echo signals diffusely reflected by a target to be detected into electric signals;
3): amplifying the electric signal in the step (2) by using AGC;
4): the method comprises the following steps that a plurality of paths of clock signals with the same frequency and set fixed phase difference output by a high-frequency clock source chip are simultaneously sent to a high-speed ADC to serve as sampling clocks, and sampling is simultaneously carried out by the plurality of paths of high-speed ADCs to splice sampling data of the plurality of paths of high-speed ADCs into ADC sampling data;
5): and storing the spliced ADC sampling data in FIFO of the FPGA processor again.
Further, the FPGA processor configures the high-speed ADC, and configures the sampling mode and the sampling rate of the high-speed ADC.
Furthermore, the FPGA configures a high-frequency clock source and outputs a plurality of clock signals with the same frequency and fixed phase difference.
Furthermore, the high-speed ADC sampling clock is provided by a clock source chip, and the multi-path high-speed ADC sampling clock is respectively a clock with the same frequency and different phases.
Further, the FPGA processor performs real-time sampling data splicing on the sampling data of the ADC according to the timing sequence relation of the multi-path high-speed ADC sampling clock in the step (3).
Further, the spliced ADC sampling data in the step (5) is full waveform data.
Furthermore, the multi-path high-speed ADC sampling data are respectively stored in FIFO of the FPGA processor.
By means of the technical scheme, the invention has the advantages that: the invention realizes ADC data interpolation by adopting a multi-path ADC parallel sampling mode, realizes higher data acquisition rate similar to an ultra-high-speed ADC by adopting a high-speed ADC sampling mode, reduces the design difficulty and the ADC cost, and simultaneously ensures the high-speed data sampling rate.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understandable, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of parallel operation of high-speed ADCs in the method for sampling full waveforms of echoes of an FPGA by using a plurality of paths of high-speed ADCs;
FIG. 2 is a high-speed ADC parallel echo reconstruction principle in the method for multi-path high-speed ADC sampling FPGA echo full-waveform sampling.
Detailed Description
The invention will be better understood by those skilled in the art from the following description of specific embodiments thereof, taken in conjunction with the accompanying drawings.
The method for sampling the echo full waveform of the FPGA by the multi-path high-speed ADC comprises the following specific steps:
1): the laser emits a pulse signal with a certain repetition frequency to drive the laser to generate laser, the laser hits on a target to be detected to generate an echo signal, and the echo signal is a weak optical signal;
2): the APD photoelectric searchlight converts a weak optical signal diffusely reflected by a target to be detected into an electric signal;
3): pre-amplifying the electric signal converted by the APD photoelectric searchlight in the step (2) by using AGC, and naming the amplified signal as S1;
4): the FPGA processor configures a high-frequency clock source, outputs a plurality of paths of clock signals with the same frequency and fixed phase difference, outputs the clock signals to the high-speed ADCs with the same type at the same time to be used as sampling clocks, samples S1 in parallel and at the same time by using the plurality of paths of high-speed ADCs under the clock signals with the same frequency and different phases generated by the high-speed clock source chip to obtain a plurality of paths of high-speed ADC conversion data, and performs real-time sampling data splicing on the data acquired by the high-speed ADCs by the FPGA processor according to the time sequence relation of the plurality of paths of high-speed ADC sampling clocks to obtain full waveform data;
the FPGA processor configures the high-speed ADC, and configures the sampling mode and the sampling rate of the high-speed ADC, wherein a high-speed ADC sampling clock is provided by a clock source chip, and a plurality of paths of high-speed ADC sampling clocks are clocks with the same frequency and different phases; the high-speed clock source generates a plurality of paths of clock signals with fixed phase difference, or generates a path of clock source through the high-speed clock source and sends the clock signal to the PGA, and the FPGA processor generates a plurality of paths of clock signals with fixed phase difference to be used as clock sources of the plurality of paths of ADC sampling chips;
the mode adopts the high-speed ADC with low cost to replace the high-cost ultrahigh-speed ADC, technical blockade is avoided, the design difficulty is reduced, the multi-path high-speed ADC data are spliced into full waveform data according to the sampling time sequence to achieve high sampling rate, real-time sampling is realized, and the full waveform acquisition efficiency is improved.
5): and (4) storing the full waveform data spliced in the step (4) in FIFO of the FPGA processor again.
In the embodiment, the FPGA processor adopts an array series 10AS048 chip of Altera corporation, the highest IO bandwidth of the chip is 700MHZ, the high-speed ADC chip adopts AD9434, and the sampling rate is 500 MSPS. Referring to fig. 2, the clock source chip has low phase noise, and the PLL chip AD9522-3 with a 2GHZ vco integrated therein has an aperture jitter 242fs, which can output four LVDS differential clock signals simultaneously. The clock source chip generates 4 paths of clock signals with the frequency of 500MHZ, the phase difference of four paths of clocks is 900, and four paths of clocks with the same frequency and different phases are respectively used as sampling clocks for four paths of high-speed ADCs. The points acquired by the ADC1 are a11, a12, a13.. A1n, the points acquired by the ADC2 are a21, a22, a23.. A2n, the points acquired by the ADC3 are a31, a32, a33.. A3n, the points acquired by the ADC4 are a41, a42, and a43.. A4n, the points acquired by the four ADCs are points of the same waveform at different times, and the data acquired by the four ADCs are stored in an FIFO of the FPGA processor. The four-way ADCs have the same sampling clock frequency, the ADC1 has a sampling clock of clk1, the ADC2 has a sampling clock of clk2, the ADC3 has a sampling clock of clk3, the ADC4 has a sampling clock of clk4, and the four-way ADCs have different sampling clocks and have a phase difference of 900, so that data sampled by the four-way ADCs can be reconstructed into a11, a21, a31, a41, a12, a22, a32, a42, a13, a23, a33, a43.
The invention adopts the parallel multiplexing ADC sampling chip to realize the echo full waveform sampling of the laser scanner, solves the problems that the high-speed ADC goods source is restricted by the domestic technical bottleneck and the overseas banning, realizes the real-time high-speed acquisition of the narrow pulse full waveform, and reduces the requirements of circuit layout, the time sequence constraint source of a post-stage processing chip and the bandwidth.
The above description is only a preferred embodiment of the present invention, and any person skilled in the art can make any simple modification, equivalent change and modification to the above embodiments according to the technical essence of the present invention without departing from the scope of the present invention, and still fall within the scope of the present invention.
Claims (7)
1. The method for sampling the full waveform of the echo of the FPGA by the multi-path high-speed ADC is characterized by comprising the following steps of: the method comprises the following steps:
1): the laser emits a pulse signal, and the laser irradiates a target to be detected to generate an echo signal;
2): the APD photoelectric searchlight converts echo signals diffusely reflected by a target to be detected into electric signals;
3): amplifying the electric signal in the step (2) by using AGC;
4): the method comprises the following steps that a plurality of paths of clock signals with the same frequency and set fixed phase difference output by a high-frequency clock source chip are simultaneously sent to a high-speed ADC to serve as sampling clocks, and sampling is simultaneously carried out by the plurality of paths of high-speed ADCs to splice sampling data of the plurality of paths of high-speed ADCs into ADC sampling data;
5): and storing the spliced ADC sampling data in FIFO of the FPGA processor again.
2. The method for multi-path high-speed ADC sampling FPGA echo full-waveform sampling according to claim 1, characterized in that: and the FPGA processor configures the high-speed ADC, and configures the sampling mode and the sampling rate of the high-speed ADC.
3. The method for multi-path high-speed ADC sampling FPGA echo full-waveform sampling according to claim 1, characterized in that: the FPGA configures a high-frequency clock source and outputs a plurality of clock signals with the same frequency and fixed phase difference.
4. The method for multi-path high-speed ADC sampling FPGA echo full-waveform sampling according to claim 1, characterized in that: the high-speed ADC sampling clock is provided by a clock source chip, and the multi-path high-speed ADC sampling clock is clocks with the same frequency and different phases.
5. The method for multi-path high-speed ADC sampling FPGA echo full-waveform sampling according to claim 1, characterized in that: and (4) splicing the sampled data of the ADC by the FPGA processor according to the time sequence relation of the sampling clocks of the multi-path high-speed ADC in real time in the step (3).
6. The method for multi-path high-speed ADC sampling FPGA echo full-waveform sampling according to claim 1, characterized in that: and (5) the spliced ADC sampling data in the step (5) is full waveform data.
7. The method for multi-path high-speed ADC sampling FPGA echo full-waveform sampling according to claim 1, characterized in that: and the multi-path high-speed ADC sampling data are respectively stored in FIFO of the FPGA processor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115372984A (en) * | 2022-10-25 | 2022-11-22 | 东莞市森威电子有限公司 | Pulse laser ranging method based on phase-shifting sampling interpolation method |
| CN117459064A (en) * | 2023-12-25 | 2024-01-26 | 武汉市品持科技有限公司 | Multipath ADC sampling method, device and equipment |
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