CN117459064A - Multipath ADC sampling method, device and equipment - Google Patents
Multipath ADC sampling method, device and equipment Download PDFInfo
- Publication number
- CN117459064A CN117459064A CN202311791716.3A CN202311791716A CN117459064A CN 117459064 A CN117459064 A CN 117459064A CN 202311791716 A CN202311791716 A CN 202311791716A CN 117459064 A CN117459064 A CN 117459064A
- Authority
- CN
- China
- Prior art keywords
- sampling
- data
- adc
- time sequence
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 255
- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000009466 transformation Effects 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 13
- 230000000630 rising effect Effects 0.000 claims description 13
- 238000004891 communication Methods 0.000 claims description 8
- 238000001228 spectrum Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 230000001131 transforming effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/60—Analogue/digital converters with intermediate conversion to frequency of pulses
Abstract
The invention discloses a multipath ADC sampling method, device and equipment, wherein the method comprises the following steps: acquiring a data source clock signal and a plurality of sampling clock signals with the same frequency and fixed phase difference; respectively sending each path of sampling clock signal to a plurality of paths of ADC channels; each path of ADC channel samples the target according to the corresponding sampling clock signal and a preset sampling mode to obtain sampling information; each path of ADC channel transmits the acquired sampling information to a data receiving module; the data receiving module combines the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence; the clock signal period is greater than the data source clock signal period. The invention ensures that the phase difference Tdelay of Sync_CLKn and Sync_CLK (n-1) is fixed by setting the sampling clock signals with the same multipath frequency and fixed phase difference, thereby realizing that a plurality of ADCs can be synchronously adopted and obtaining higher sampling frequency and higher sampling resolution.
Description
Technical Field
The invention belongs to the field of photoelectric detection, and particularly relates to a multi-channel ADC sampling method, a multi-channel ADC acquisition device and equipment adopting the multi-channel ADC sampling method or device.
Background
With the development of technology, the requirements of various industries on detection speed and precision are continuously increased, and the improvement of the speed and precision of data acquisition is one of the necessary means for improving the detection speed and precision. At present, the function of an ADC (analog-to-digital converter) chip in data sampling is increasingly important, the demand for the ADC chip is also increasing, and a high-speed and high-precision data acquisition system has become a solution for a plurality of scene applications such as medical equipment, unmanned operation, high-precision navigation and the like.
In the prior art, the low-speed ADC chip is difficult to meet the requirements of a high-speed and high-precision data acquisition system, so that when the low-speed ADC chip is used as an ADC acquisition channel, how to increase the sampling rate of the sampling system is a technical problem to be solved.
Disclosure of Invention
In view of this, the present invention aims to solve the problem that the prior art rate is difficult to meet the requirement of a high-speed and high-precision data acquisition system, and improves the sampling rate of the sampling system by using a plurality of low-speed ADC chips as ADC acquisition channels.
In order to solve the above-mentioned problems, the present invention adopts the following technical scheme:
the invention relates to a multipath ADC sampling method, which comprises the following steps:
acquiring a data source clock signal and a plurality of sampling clock signals with the same frequency and fixed phase difference;
respectively sending each path of sampling clock signal to a plurality of paths of ADC channels;
each path of ADC channel samples the target according to the corresponding sampling clock signal and a preset sampling mode to obtain sampling information;
each path of ADC channel sends the acquired sampling information to a data receiving module according to time sequence through the same communication bus;
the data receiving module combines the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence;
wherein the number of sampling clock signals is the same as the ADC channels; the clock signal period is greater than the data source clock signal period.
Preferably, the phase difference of the sampling clock signals of the two adjacent paths is equal to the period of the data source clock signal.
Preferably, the rising edge of each ADC channel sampling waveform is at least partially aligned with the rising edge of the data source waveform.
Preferably, the process of combining the sampling information acquired by each path of ADC channels into final sampling data by the data receiving module according to the time sequence includes the following steps:
acquiring a time sequence of source data, performing linear interpolation on the source data according to the time sequence of the source data, and performing Fourier transformation to obtain a frequency domain signal of the source data;
acquiring the time sequence of sampling information, performing linear interpolation on the sampling information according to the time sequence of the sampling information, and performing Fourier transformation to obtain a frequency domain signal of the sampling information;
and obtaining final sampling data based on inverse Fourier transform according to the frequency domain signal of the source data and the frequency domain signal of the sampling information.
Preferably, the process of obtaining final sampling data based on inverse fourier transform according to the frequency domain signal of the source data and the frequency domain signal of the sampling information includes:
acquiring a first time sequence corresponding to a frequency domain signal of source data and a second time sequence corresponding to a frequency domain signal of sampling information, and calculating to obtain a third time sequence according to the first time sequence and the second time sequence;
performing inverse Fourier transform on the third time sequence to obtain an inversion sequence;
and acquiring an element with the largest real part in the inversion sequence, and splicing to obtain final sampling data.
Preferably, the process of performing fourier transform on the source data after performing linear interpolation according to the time sequence of the source data to obtain the frequency domain signal of the source data includes:
setting the number k1 of linear interpolation, and inserting k1 linear interpolation between the data of two adjacent channels;
fourier transforming the interpolated data source:
taking the conjugate sequence of the data source after Fourier transformation as a frequency domain signal of the data source.
Preferably, the process of performing fourier transform on the sampling information after performing linear interpolation according to the time sequence of the sampling information to obtain the frequency domain signal of the sampling information includes:
setting the number k2 of linear interpolation, and uniformly inserting the k2 linear interpolation between two adjacent sampling information;
and carrying out Fourier transformation on the sampling information after the offline interpolation to obtain a frequency spectrum signal of the sampling information.
In order to achieve the object of the present invention, the present invention further provides a multi-channel ADC sampling device, including:
the clock module is used for acquiring a data source clock signal and sampling clock signals with the same multipath frequency and fixed phase difference;
and a sending module: the sampling clock signals are respectively sent to the multiple ADC channels;
the acquisition module is used for sampling the targets according to the corresponding sampling clock signals of the ADC channels to obtain sampling information;
the synchronous module is used for sending the acquired sampling information of each path of ADC channels to the data receiving module through the same communication bus according to time sequence;
the data receiving module is used for combining the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence;
wherein the number of sampling clock signals is the same as the ADC channels; the clock signal period is greater than the data source clock signal period.
In order to achieve the object of the present invention, the present invention also provides a sampling apparatus to which the sampling method described in the above embodiments can be applied or a sampling apparatus including the sampling device in the above embodiments, the sampling apparatus including: the device comprises a laser transmitter, a laser receiver and an ADC sampling device, wherein the laser transmitter is used for transmitting laser; the laser receiver is used for receiving reflected laser to form a data source and sending the data source to the ADC sampling device; the ADC sampling device samples by using the multi-channel ADC sampling method described in any one of the above embodiments.
The ADC sampling device is the multi-channel ADC sampling device described in the above embodiment.
The invention has the beneficial effects that:
compared with the prior art, the invention discloses a multipath ADC sampling method, which comprises the following steps: acquiring a data source clock signal and a plurality of sampling clock signals with the same frequency and fixed phase difference; respectively sending each path of sampling clock signal to a plurality of paths of ADC channels; each path of ADC channel samples the target according to the corresponding sampling clock signal and a preset sampling mode to obtain sampling information; each path of ADC channel sends the acquired sampling information to a data receiving module according to time sequence through the same communication bus; the data receiving module combines the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence; wherein the number of sampling clock signals is the same as the number of ADC channels; the clock signal period is greater than the data source clock signal period. The invention sets the sampling clock signals with the same multipath frequency and fixed phase difference, so that the time phase difference of two adjacent sampling signals is fixed, thereby realizing that a plurality of ADCs can be adopted synchronously according to the sequence, and obtaining higher sampling frequency and higher sampling resolution.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the following brief description of the drawings will make it apparent that the drawings in the following description relate only to some embodiments of the invention and are not limiting of the invention.
FIG. 1 is a flow chart of a sampling method according to a preferred embodiment of the invention;
FIG. 2 is a schematic diagram of a multi-channel ADC sampling structure according to a preferred embodiment of the present invention;
FIG. 3 is a timing diagram of two-channel ADC channel sampling according to a preferred embodiment of the present invention;
fig. 4 is a block diagram of a multi-channel ADC channel sampling apparatus according to a preferred embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the attached drawings: it should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.
Referring to fig. 1-3, the present embodiment provides a multi-channel ADC sampling method, which includes the following steps:
step S1, acquiring a data source clock signal and sampling clock signals with the same multipath frequency and fixed phase difference. Referring to fig. 3, it is possible to take charge of generating a Data source clock signal data_clk supplied to the Data source Sensor and synchronizing clocks sync_clk1 to sync_clkn supplied to the respective ADC channels by a clock and synchronizing module. Where n is a positive integer, which represents the number of ADC channels. Each ADC channel has clock signals with the same frequency and a fixed phase difference, and synchronous clocks Sync_CLK1-Sync_CLKn are used as sampling clocks of each channel of ADC, so that each channel of ADC is subjected to parallel sampling, and each channel of ADC is used for simultaneously acquiring data and improving the data acquisition rate. Wherein: sampling clocks of the ADC channels are clocks with the same frequency and different phases respectively, but have the same phase difference; the period of the sampling clock signal may be Ts and the time phase difference of adjacent channels may be the period of the data source clock signal.
And step S2, respectively sending each path of sampling clock signal to a plurality of paths of ADC channels. Referring to fig. 3, the Data source Sensor outputs source Data according to a Data source clock signal data_clk. The source Data is sent to all ADC channels.
And S3, each path of ADC channel samples the target according to a preset sampling mode according to the corresponding sampling clock signal to obtain sampling information. The ADC starts synchronously according to its corresponding synchronization clock sync_clkx (x=1, 2..n), and respectively sampling according to the time sequence to respectively obtain respective sampling information. So as to achieve the aim of synchronous sampling of a plurality of ADCs according to time sequence. Data_clk, data, sync_clkx (x=1, 2..n) follow a certain timing sequence, and the timing chart is shown in fig. 3. In the embodiment shown in fig. 3, two ADC channels are used as an illustration, and the clock of the Data source (the Data source timing) is data_clk, and the period is Td, so the source Data output period is Td. As shown in fig. 3, the predetermined sampling manner may be set to rising edge sampling.
And S4, each path of ADC channel sends the acquired sampling information to the data receiving module through the same communication bus according to time sequence. Each path of ADC channel can send sampling information to the data receiving module through the same communication bus, and the sent sampling information can be sent according to a certain time sequence. The sampling information may include timing information, and the timing information may be that the source data Sensor is set to sync_clkx (x=1, 2..n) according to the positions of the respective ADC channels or a predetermined order, respectively.
S5, the data receiving module combines the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence; wherein the number of sampling clock signals is the same as the ADC channels; the clock signal period is greater than the data source clock signal period. The data receiving module may be an FPGA chip. And the data receiving module performs real-time sampling data splicing on sampling information sent by the ADC channels according to the sampling clock timing relation of each path of ADC to obtain final sampling data.
As a preferred embodiment, to increase the sampling rate of the ADC channels, the sampling clock signals of two adjacent ADC channels have a phase difference equal to the data source clock signal period, so that the multiple ADC channels have clock signals with a fixed phase difference. The clock signal of the multiple ADC channels with a fixed phase difference can be generated by a clock and synchronization module as a clock source for the multiple ADC channels. Assuming that n ADC channels are involved in the synchronization, the clock signal for sampling information may be a period ts=2td of sync_clkx (x=1, 2..n). Wherein at least the rising edge of the first ADC channel sync_clk1 is aligned with the rising edge of data_clk, the phase difference tdelay=td between sync_clk2 and sync_clk1, and so on, the phase difference Tdelay between sync_clkn and sync_clk (n-1) time is Td. As can be seen from the timing diagram 3, multiple ADC synchronizations with lower frequencies can be utilized to increase the sampling rate of the overall sampling system. The schematic diagram only demonstrates that two ADC channels are synchronized, increasing the sampling rate of the system to twice as much as before. The sampling rate can be increased by more than twice by n channels. The timing sequence of the first ADC channel is Sync_CLK1, the timing sequence of the second ADC channel is Sync_CLK2, and so on, and the timing sequence of the nth ADC channel is Sync_CLKn. The phase difference between two adjacent channels in the n ADC channels is fixed, which may be that at least part of the rising edge of the sampling information in the n ADC channels is aligned with the rising edge of the source data, so that the sampled data can be spliced into complete data after sampling along the rising edge, thereby improving the sampling rate and efficiency. Wherein the data source clock signal period is Td.
To improve the efficiency of the acquisition of each ADC channel, the rising edge of the sampling waveform of each ADC channel is at least partially aligned with the rising edge of the data source waveform. By sampling along the rising edge, the sampling information of each path of ADC channels can be formed into final sampling data according to time sequence, so that the sampling rate is improved.
As a preferred embodiment, the process of combining the sampling information acquired by each path of ADC channels into final sampling data by the data receiving module according to the time sequence includes the following steps:
acquiring source data of a data source, performing linear interpolation on the source data according to the time sequence of the source data, and performing Fourier transformation to obtain a frequency domain signal of the source data;
acquiring the time sequence of sampling information, performing linear interpolation on the sampling information according to the time sequence of the sampling information, and performing Fourier transformation to obtain a frequency domain signal of the sampling information;
and obtaining final sampling data based on inverse Fourier transform according to the frequency domain signal of the source data and the frequency domain signal of the sampling information.
As a preferred embodiment, the process of obtaining final sampling data based on inverse fourier transform according to the frequency domain signal of the source data and the frequency domain signal of the sampling information includes: acquiring a first time sequence corresponding to a frequency domain signal of source data and a second time sequence corresponding to a frequency domain signal of sampling information, and calculating to obtain a third time sequence according to the first time sequence and the second time sequence; performing inverse Fourier transform on the third time sequence to obtain an inversion sequence; and acquiring an element with the largest real part in the inversion sequence, and splicing according to the element with the largest real part in the inversion sequence to obtain final sampling data.
The calculating the third time sequence according to the first time sequence and the second time sequence may be that the third time sequence is obtained by multiplying the first time sequence and the second time sequence.
The process of splicing the elements with the largest real parts in the inversion sequence to obtain the final sampling data can be as follows: and splicing the sampling information according to the sequence obtained after inversion, or multiplying the period of a data source by the element with the largest real part in the inversion sequence and adding a random delay time to obtain final sampling data, namely a detection result. The random delay time is the corresponding random delay time before the data source transmits.
Performing fourier transform on the source data after performing linear interpolation to obtain a frequency domain signal of the source data, including:
taking the number k1 of linear interpolation, and inserting k1 linear interpolation between the data of two adjacent channels;
fourier transforming the interpolated data source:
taking the conjugate sequence of the data source after Fourier transformation as a frequency domain signal of the data source.
The performing the linear interpolation on the sampling information and then performing the spectrum transformation to obtain a spectrum signal of the sampling information includes:
taking the number k2 of linear interpolation, and uniformly inserting the k2 linear interpolation between two adjacent sampling information;
and carrying out Fourier transformation on the sampling information after the offline interpolation to obtain a frequency spectrum signal of the sampling information.
Wherein, K2 can be equal to K1. Taking K2 as an example, K1 linear interpolation is inserted into two adjacent time sequences sync_clk (x) and sync_clk (x+1), and K2 points are inserted between two adjacent sampling information according to the time sequence, so as to obtain new sequences sync_clk (x), sync_clk (x, 1), sync_clk (x, 2) … sync_clk (x, K), and sync_clk (x+1).
The invention ensures that the phase difference Tdelay of Sync_CLKn and Sync_CLK (n-1) is fixed by setting the sampling clock signals with the same multipath frequency and fixed phase difference, thereby realizing that a plurality of ADCs can be synchronously adopted and obtaining higher sampling frequency and higher sampling resolution by utilizing the principle of oversampling.
Referring to fig. 4, the present invention further provides a multi-channel ADC sampling apparatus, including: the device comprises a clock module, a sending module, an acquisition module, a synchronization module and a data receiving module. The clock module is used for acquiring a data source clock signal and sampling clock signals which have the same multipath frequency and have fixed phase difference; the sending module is used for sending each path of sampling clock signals to a plurality of paths of ADC channels respectively; the acquisition module is used for sampling the targets according to a preset sampling mode to obtain sampling information according to the corresponding sampling clock signals of each path of ADC channels; the synchronous module is used for sending the sampling information acquired by each path of ADC channels to the data receiving module through the same communication bus according to time sequence; the data receiving module is used for combining the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence; wherein the number of sampling clock signals is the same as the ADC channels; the clock signal period is greater than the data source clock signal period. The clock module and the synchronization module may together constitute the clock and synchronization module shown in fig. 2. The number of the sampling clock signals is the same as that of the ADC channels, and each ADC channel corresponds to one sampling clock signal. The clock signal period is equal to two or more times the data source clock signal period.
The data receiving module further comprises a frequency domain signal calculating module of source data, a frequency domain signal calculating module of sampling information and a final sampling data obtaining module. The frequency domain signal calculation module of the source data is used for acquiring the time sequence of the source data, performing linear interpolation on the source data according to the time sequence of the source data, and then performing Fourier transformation to obtain a frequency domain signal of the source data;
the frequency domain signal calculation module of the sampling information is used for acquiring the time sequence of the sampling information, performing linear interpolation on the sampling information according to the time sequence of the sampling information, and then performing Fourier transformation to obtain a frequency domain signal of the sampling information; the final sampling data acquisition module is used for obtaining final sampling data based on inverse Fourier transform according to the frequency domain signal of the source data and the frequency domain signal of the sampling information.
The process of obtaining final sampling data based on inverse fourier transform according to the frequency domain signal of the source data and the frequency domain signal of the sampling information comprises the following steps: acquiring a first time sequence corresponding to a frequency domain signal of source data and a second time sequence corresponding to a frequency domain signal of sampling information, and calculating to obtain a third time sequence according to the first time sequence and the second time sequence; performing inverse Fourier transform on the third time sequence to obtain an inversion sequence; and acquiring an element with the largest real part in the inversion sequence, and splicing to obtain final sampling data.
The process of performing fourier transform on the source data after performing linear interpolation according to the time sequence of the source data to obtain the frequency domain signal of the source data comprises the following steps: setting the number k1 of linear interpolation, and inserting k1 linear interpolation between the data of two adjacent channels; fourier transforming the interpolated data source: taking the conjugate sequence of the data source after Fourier transformation as a frequency domain signal of the data source. The process of performing fourier transform on the sampling information after performing linear interpolation according to the time sequence of the sampling information to obtain the frequency domain signal of the sampling information comprises the following steps: setting the number k2 of linear interpolation, and uniformly inserting the k2 linear interpolation between two adjacent sampling information; and carrying out Fourier transformation on the sampling information after the offline interpolation to obtain a frequency spectrum signal of the sampling information.
The invention also provides sampling equipment, a laser transmitter, a laser receiver and an ADC sampling device, wherein the laser transmitter is used for transmitting laser; the laser receiver is used for receiving the electric signal formed by the reflected laser and can be the data source, and the data source is sent to the ADC sampling device; the ADC sampling device samples by using the multi-channel ADC sampling method described in any one of the above embodiments.
The laser of the sampling device emits laser, and the laser receiver can receive the reflected laser after the laser is reflected by the object to be detected. The laser receiver may use the reflected laser generated electrical signal it receives as a data source. The data source may be sent to a multi-channel ADC sampling device.
The sampling method, the device and the equipment adopt the mode of combining a plurality of low-frequency ADCs to replace a high-cost ultra-high-speed ADC, avoid technical blockade, reduce design difficulty, combine multiple paths of ADC data into final sampling data according to a sampling time sequence order so as to achieve high sampling rate, realize real-time sampling and improve full waveform acquisition efficiency.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or an implicit indication of the number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
It should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
It will be apparent to those skilled in the art from this disclosure that various other changes and modifications can be made which are within the scope of the invention as defined in the appended claims.
Claims (10)
1. The multi-channel ADC sampling method is characterized by comprising the following steps of:
acquiring a data source clock signal and a plurality of sampling clock signals with the same frequency and fixed phase difference;
respectively sending each path of sampling clock signal to a plurality of paths of ADC channels;
sampling the target according to a preset sampling mode by each path of ADC channels according to the corresponding sampling clock signals to obtain sampling information, wherein each path of ADC channels adopts a mode with the same frequency and a fixed phase difference for sampling;
each path of ADC channel sends the acquired sampling information to a data receiving module according to time sequence through the same communication bus;
the data receiving module combines the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence;
wherein the number of sampling clock signals is the same as the ADC channels; the clock signal period is greater than the data source clock signal period.
2. The multi-channel ADC sampling method according to claim 1, wherein the sampling clock signal phase difference of two adjacent channels is equal to the data source clock signal period.
3. A multi-channel ADC sampling method according to claim 1 or claim 2, in which the rising edge of each channel of ADC sampling waveforms is at least partially aligned with the rising edge of the data source waveform.
4. The multi-channel ADC sampling method according to claim 1 or 2, wherein the process of combining the sampling information obtained by each channel of ADC into final sampling data by the data receiving module according to the time sequence comprises the following steps:
acquiring a time sequence of source data, performing linear interpolation on the source data according to the time sequence of the source data, and performing Fourier transformation to obtain a frequency domain signal of the source data;
acquiring the time sequence of sampling information, performing linear interpolation on the sampling information according to the time sequence of the sampling information, and performing Fourier transformation to obtain a frequency domain signal of the sampling information;
and obtaining final sampling data based on inverse Fourier transform according to the frequency domain signal of the source data and the frequency domain signal of the sampling information.
5. The multi-channel ADC sampling method according to claim 4, wherein the obtaining the final sampled data based on the inverse fourier transform from the frequency domain signal of the source data and the frequency domain signal of the sampling information comprises:
acquiring a first time sequence corresponding to a frequency domain signal of source data and a second time sequence corresponding to a frequency domain signal of sampling information, and calculating to obtain a third time sequence according to the first time sequence and the second time sequence;
performing inverse Fourier transform on the third time sequence to obtain an inversion sequence;
and acquiring an element with the largest real part in the inversion sequence, and splicing to obtain final sampling data.
6. The method of multi-channel ADC sampling as recited in claim 5, wherein,
the process of performing fourier transform on the source data after performing linear interpolation according to the time sequence of the source data to obtain the frequency domain signal of the source data comprises the following steps:
setting the number k1 of linear interpolation, and inserting k1 linear interpolation between the data of two adjacent channels;
fourier transforming the interpolated data source:
taking the conjugate sequence of the data source after Fourier transformation as a frequency domain signal of the data source.
7. The multi-channel ADC sampling method according to claim 5, wherein the process of performing fourier transform on the sampling information after performing linear interpolation according to the timing sequence of the sampling information to obtain the frequency domain signal of the sampling information comprises:
setting the number k2 of linear interpolation, and uniformly inserting the k2 linear interpolation between two adjacent sampling information;
and carrying out Fourier transformation on the sampling information after the offline interpolation to obtain a frequency spectrum signal of the sampling information.
8. A multi-channel ADC sampling apparatus, comprising:
the clock module is used for acquiring a data source clock signal and sampling clock signals with the same multipath frequency and fixed phase difference;
and a sending module: the sampling clock signals are respectively sent to the multiple ADC channels;
the acquisition module is used for sampling the targets according to the corresponding sampling clock signals of the ADC channels to obtain sampling information;
the synchronous module is used for sending the acquired sampling information of each path of ADC channels to the data receiving module through the same communication bus according to time sequence;
the data receiving module is used for combining the sampling information acquired by each path of ADC channels into final sampling data according to the time sequence;
wherein the number of sampling clock signals is the same as the ADC channels; the clock signal period is greater than the data source clock signal period.
9. A sampling device, comprising: the device comprises a laser transmitter, a laser receiver and an ADC sampling device, wherein the laser transmitter is used for transmitting laser; the laser receiver is used for receiving the reflected laser and forming a data source, and sending the data source to the ADC sampling device; the ADC sampling device samples by using the multi-channel ADC sampling method according to any one of claims 1 to 7.
10. The sampling device of claim 9, wherein the ADC sampling means is the multi-channel ADC sampling means of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311791716.3A CN117459064B (en) | 2023-12-25 | 2023-12-25 | Multipath ADC sampling method, device and equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311791716.3A CN117459064B (en) | 2023-12-25 | 2023-12-25 | Multipath ADC sampling method, device and equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117459064A true CN117459064A (en) | 2024-01-26 |
| CN117459064B CN117459064B (en) | 2024-03-26 |
Family
ID=89586000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311791716.3A Active CN117459064B (en) | 2023-12-25 | 2023-12-25 | Multipath ADC sampling method, device and equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117459064B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070057829A1 (en) * | 2003-09-24 | 2007-03-15 | Mitsuharu Sugita | Multi-signal analysis device |
| US20080084337A1 (en) * | 2006-09-29 | 2008-04-10 | Optichron, Inc. | Adaptive composite analog to digital converter |
| US20120176260A1 (en) * | 2009-01-19 | 2012-07-12 | Advantest Corporation | Analog-digital converting method and analog-digital converting apparatus |
| CN105991137A (en) * | 2015-03-20 | 2016-10-05 | 德克萨斯仪器股份有限公司 | Systems and methods of variable fractional rate digital resampling |
| CN106291501A (en) * | 2016-08-26 | 2017-01-04 | 上海无线电设备研究所 | High-speed Parallel Signal Processing Systems and processing method thereof |
| CN113765520A (en) * | 2020-11-25 | 2021-12-07 | 国网内蒙古东部电力有限公司 | Method for sampling full waveform of echo of multi-path high-speed ADC (analog to digital converter) sampling FPGA (field programmable gate array) |
| CN116800271A (en) * | 2023-06-19 | 2023-09-22 | 电子科技大学 | Fourier interpolation method suitable for quick time-based gear of oscilloscope |
-
2023
- 2023-12-25 CN CN202311791716.3A patent/CN117459064B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070057829A1 (en) * | 2003-09-24 | 2007-03-15 | Mitsuharu Sugita | Multi-signal analysis device |
| US20080084337A1 (en) * | 2006-09-29 | 2008-04-10 | Optichron, Inc. | Adaptive composite analog to digital converter |
| US20120176260A1 (en) * | 2009-01-19 | 2012-07-12 | Advantest Corporation | Analog-digital converting method and analog-digital converting apparatus |
| CN105991137A (en) * | 2015-03-20 | 2016-10-05 | 德克萨斯仪器股份有限公司 | Systems and methods of variable fractional rate digital resampling |
| CN106291501A (en) * | 2016-08-26 | 2017-01-04 | 上海无线电设备研究所 | High-speed Parallel Signal Processing Systems and processing method thereof |
| CN113765520A (en) * | 2020-11-25 | 2021-12-07 | 国网内蒙古东部电力有限公司 | Method for sampling full waveform of echo of multi-path high-speed ADC (analog to digital converter) sampling FPGA (field programmable gate array) |
| CN116800271A (en) * | 2023-06-19 | 2023-09-22 | 电子科技大学 | Fourier interpolation method suitable for quick time-based gear of oscilloscope |
Non-Patent Citations (2)
| Title |
|---|
| SIHAO SUN: "A Novel Signal Processing Method Based on Cross-correlation and Interpolation for ToF Measurement", 《 2019 IEEE 4TH INTERNATIONAL CONFERENCE ON SIGNAL AND IMAGE PROCESSING (ICSIP)》, 31 December 2019 (2019-12-31), pages 1 - 4 * |
| 向海生: "基于拼接采样技术的宽带数字接收机", 《雷达科学与技术》, 31 December 2014 (2014-12-31), pages 450 - 453 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117459064B (en) | 2024-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3672778B2 (en) | Radar apparatus and coherent integration method thereof | |
| CN108134607A (en) | High-speed AD synchronous acquisition circuit and synchronous method between plate based on JESD204B | |
| CN101599938B (en) | Time domain combined synchronization method for orthogonal frequency division multiplexing (OFDM) ultra wide band system receiver | |
| US10320406B2 (en) | Method for synchronizing data converters by means of a signal transmitted from one to the next | |
| CN104991440A (en) | High-precision IRIG-B(AC) code demodulation method and device | |
| CN101043317A (en) | Method for testing precision of time synchronism equipment and its system | |
| CN103592881A (en) | Multi-path signal synchronous sampling control circuit based on FPGA | |
| CN101212213B (en) | Clock signal generating device and analog-digital conversion device | |
| CN102510327B (en) | Method and device for improving synchronous precision of long-range two-way time comparison modulator-demodulator | |
| CN104297543A (en) | Hybrid oscilloscope with channel synchronization function | |
| CN117459064B (en) | Multipath ADC sampling method, device and equipment | |
| JP2535816Y2 (en) | Radar equipment | |
| CN105044459A (en) | Harmonic analysis method | |
| JPH0577990B2 (en) | ||
| CN110046125B (en) | Method and device for synchronizing same-frequency continuous serial data | |
| CN204086871U (en) | A kind of multiple signals synchronous sampling control circuit based on FPGA | |
| Sudars et al. | Signal Analog-to-Event-to-Digital converting based on periodic sampling and precise event timing | |
| CN112019215B (en) | Pulse width modulation single-distribution type multichannel ADC synchronization method | |
| US6549157B1 (en) | Digital-to-analog converting device and method used in home networking system with compensation mechanism to reduce clock jitter | |
| CN114614823B (en) | Chip clock synchronization method, data acquisition card and data acquisition system | |
| CN116301199B (en) | Signal generation system and method | |
| CN108761431B (en) | Digital delay system for sonar system test and implementation method thereof | |
| US20230238975A1 (en) | Method for synchronizing analogue-digital or digital-analogue converters, and corresponding system | |
| Gou et al. | Multi-channel wideband signal full bandwidth synchronous acquisition method | |
| CN116032278A (en) | Data acquisition device, system and method based on clock synchronization of second pulse |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |