CN109116214A - The LVDS/V-by-one signal testing jig of chip main board - Google Patents
The LVDS/V-by-one signal testing jig of chip main board Download PDFInfo
- Publication number
- CN109116214A CN109116214A CN201810888080.7A CN201810888080A CN109116214A CN 109116214 A CN109116214 A CN 109116214A CN 201810888080 A CN201810888080 A CN 201810888080A CN 109116214 A CN109116214 A CN 109116214A
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- China
- Prior art keywords
- signal
- main board
- lvds
- chip main
- testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of LVDS/V-by-one signal testing jigs of chip main board, including rack, the rack is for installing the chip main board, the test fixture further includes testing needle, signal converting component and the signal connecting line connecting with the signal converting component, and the signal converting component is for exporting the LVDS/V-by-one signal for the chip main board that the testing needle measures to the signal connecting line；The signal converting component includes adapter, the adapter offers the corresponding and matched stitch hole with the testing needle, one end of the testing needle is docked with the LVDS/V-by-one signal testing point on the chip main board, and the other end of the testing needle is inserted into the stitch hole.The high advantage of the good in anti-interference performance and testing efficiency of the LVDS/V-by-one signal testing jig of chip main board of the present invention.
Description
Technical field
The present invention relates to route board test apparatus technical field more particularly to a kind of LVDS/V-by-one of chip main board
Signal testing jig.
Background technique
Chip main board LVDS/ (or) transmission rate of V-by-one signal is quite high, especially V-by-one signal
Transmission rate be up to 1G bps or more.Existing test fixture generallys use the mode of sealing wire to test chip main board
LVDS/V-by-one signal, or by manually signal connecting line is plugged on chip main board in the way of, i.e., artificial grafting believe
The mode of number connecting line tests the LVDS/V-by-one signal of chip main board.Wherein, it is easy to produce by the way of sealing wire
Signal interference makes the picture signal of acquisition that can not restore and lead to test crash, by the way of artificial grafting signal connecting line
Then there is a problem of that testing efficiency is low.
Summary of the invention
The main purpose of the present invention is to provide a kind of LVDS/V-by-one signal testing jigs of chip main board, it is intended to
Solving the problems, such as existing test fixture, there are signal interference and testing efficiency are low.
To achieve the above object, the LVDS/V-by-one signal testing jig of chip main board provided by the invention includes machine
Frame, the rack for installing the chip main board, the test fixture further include testing needle, signal converting component and with institute
The signal connecting line of signal converting component connection is stated, the signal converting component is used for the machine core for measuring the testing needle
The LVDS/V-by-one signal of mainboard is exported to the signal connecting line；The signal converting component includes adapter, and described turn
Joint chair offers the corresponding and matched stitch hole with the testing needle, on one end of the testing needle and the chip main board
The other end of the docking of LVDS/V-by-one signal testing point, the testing needle is inserted into the stitch hole.
Preferably, the LVDS/V-by-one signal testing point using standardized packages arrangement design, the stitch hole with
The quantity of the LVDS/V-by-one signal testing point is consistent and face arranges that each LVDS/V-by-one signal is surveyed one by one
Pilot and a settable testing needle between the stitch hole of its face.
Preferably, the signal converting component further includes printed circuit board and signal output seat, the adapter and described
Signal output seat is installed on the printed circuit board, and the signal connecting line connects the signal and exports seat.
Preferably, the signal connecting line is flexible flat cable and is detachably connected with signal output seat.
Preferably, the shell of the signal output seat is made of metal material.
Preferably, the rack includes column and the transition plates that is mounted on the column, and the transition plates is located at described
Between chip main board and the signal converting component, the through-hole passed through for the testing needle is offered in the transition plates.
Preferably, the rack further includes gland, and the gland is located at the top of the transition plates, the chip main board position
Between the gland and the transition plates, the gland is equipped with the compression leg for abutting the upper surface of the chip main board.
Preferably, the gland is sheathed on the column and can slide up and down along the column.
Preferably, it is arranged with testing needle set outside the testing needle, the through-hole is matched with the test needle guard.
Preferably, the transition plates is acrylic offset plate.
In the inventive solutions, when the LVDS/V-by-one signal using test fixture test chip main board
When, chip main board is mounted on the rack, the LVDS/V-by-one signal testing point on one end and chip main board of testing needle is made
Docking, the stitch hole of the other end insertion adapter of testing needle, thus the LVDS/V-by- for the chip main board that testing needle is measured
One signal is exported by other components of adapter and signal converting component to signal connecting line.The test fixture both saved
LVDS/V-by-one output interface sealing wire has been omited, has avoided the signal interference problem generated due to sealing wire, and do not need
Artificial grafting signal connecting line, high degree of automation improve testing efficiency.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 be chip main board of the embodiment of the present invention, test fixture a visual angle assembling schematic diagram；
Fig. 2 be chip main board of the embodiment of the present invention, test fixture another visual angle assembling schematic diagram；
Fig. 3 is the decomposition diagram of Fig. 2.
Drawing reference numeral explanation:
| Label | Title | Label | Title |
| 100 | Test fixture | 1 | Rack |
| 11 | Column | 12 | Transition plates |
| 121 | Through-hole | 13 | Gland |
| 131 | Compression leg | 2 | Testing needle |
| 3 | Signal connecting line | 4 | Adapter |
| 41 | Stitch hole | 5 | Printed circuit board |
| 6 | Signal exports seat | 200 | Chip main board |
The object of the invention is realized, the embodiments will be further described with reference to the accompanying drawings for functional characteristics and advantage.
Specific embodiment
Below in conjunction with the attached drawing in the present embodiment, the technical solution in the present embodiment is clearly and completely described,
Obviously, described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Based in the present invention
Embodiment, every other embodiment obtained by those of ordinary skill in the art without making creative efforts,
It shall fall within the protection scope of the present invention.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute is only used for solving in the present embodiment
It releases in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, if this is specific
When posture changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being such as related to " first ", " second " in the present invention is used for description purposes only, and should not be understood as
Its relative importance of indication or suggestion or the quantity for implicitly indicating indicated technical characteristic.Define as a result, " first ",
The feature of " second " can explicitly or implicitly include at least one of the features.In the description of the present invention, " multiple " contain
Justice is at least two, such as two, three etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " connection ", " fixation " etc. shall be understood in a broad sense,
For example, " fixation " may be a fixed connection, it may be a detachable connection, or integral；It can be mechanical connection, be also possible to
Electrical connection；It can be directly connected, the connection inside two elements or two can also be can be indirectly connected through an intermediary
The interaction relationship of a element, unless otherwise restricted clearly.It for the ordinary skill in the art, can basis
Concrete condition understands the concrete meaning of above-mentioned term in the present invention.
It in addition, the technical solution between each embodiment of the present invention can be combined with each other, but must be general with this field
Based on logical technical staff can be realized, it will be understood that when the combination of technical solution appearance is conflicting or cannot achieve this
The combination of technical solution is not present, also not the present invention claims protection scope within.
It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not intended to limit the present invention.
As shown in Figure 1 to Figure 3, the present invention provides a kind of LVDS/V-by-one signal testing jig of chip main board 200
100, the test fixture 100 include rack 1, rack 1 be used for installing machine core mainboard 200, test fixture 100 further include testing needle 2,
Signal converting component and signal connecting line 3, the signal connecting line 3 that signal converting component is connect with signal converting component, signal
Adapter assembly is for exporting the LVDS/V-by-one signal for the chip main board 200 that testing needle 2 measures to signal connecting line 3.Letter
Number adapter assembly includes adapter 4, and adapter 4 offers corresponding and matched stitch hole 41, chip main board 200 with testing needle 2
It is equipped with LVDS/V-by-one signal testing point, one end of testing needle 2 is docked with LVDS/V-by-one signal testing point, is tested
The other end of needle 2 is inserted into stitch hole 41.
Specifically, when using the LVDS/V-by-one signal of the test fixture 100 test chip main board 200, by machine core
Mainboard 200 is mounted in rack 1, the one end for making testing needle 2 and the LVDS/V-by-one signal testing point on chip main board 200
Docking, the stitch hole 41 of the other end insertion adapter 4 of testing needle 2, thus the chip main board 200 that testing needle 2 is measured
LVDS/V-by-one signal is exported by other components of adapter 4 and signal converting component to signal connecting line 3.It can
With understanding, the signal connecting line 3 of the present embodiment can export LVDS/V-by-one signal to image information collecting device, and
Collected LVDS/V-by-one signal data is made into analytical judgment by PC host computer.The test fixture 100 was both omitted
LVDS/V-by-one output interface sealing wire, avoids the signal interference problem generated due to sealing wire, interference free performance
It is good, and artificial grafting signal connecting line 3 is not needed, high degree of automation improves testing efficiency.
In the present embodiment, LVDS/V-by-one signal testing point is using standardized packages arrangement design, i.e. LVDS/V-by-
One signal testing point is in array distribution uniformly, regular.LVDS/V-by-one signal testing on the present embodiment chip main board 200
The diameter of point is 1.2mm, and the horizontal spacing and vertical spacing between 2 LVDS/V-by-one signal testing point of arbitrary neighborhood are
2.54mm.Stitch hole 41 it is consistent with the quantity of LVDS/V-by-one signal testing point and one by one face arrange, i.e., on adapter 4
Stitch hole 41 it is consistent with the arrangement mode of LVDS/V-by-one signal testing point.Each LVDS/V-by-one signal testing point with
It may be provided with a testing needle 2 between the stitch hole 41 of its face.In the present embodiment, two can be reserved according to actual needs
A LVDS/V-by-one signal testing point, remaining each LVDS/V-by-one signal testing point with the stitch hole 41 of its face it
Between be provided with a testing needle 2.LVDS/V-by-one signal testing point and switching on the chip main board 200 of the present embodiment
Stitch hole 41 on seat 4 is arranged uniform, regular, and design specification is convenient for assembly, improve the test fixture 100 reliability and
Versatility.Du Pont's seat in the prior art can be used in the adapter of the present embodiment.
In the present embodiment, signal converting component further includes printed circuit board 5 and signal output seat 6, and adapter 4 and signal are defeated
Seat 6 is installed on printed circuit board 5 out, and 3 connection signal of signal connecting line exports seat 6.The chip main board that testing needle 2 will measure
200 LVDS/V-by-one signal is exported to adapter 4, then exports the output of seat 6 to letter by printed circuit board 5 and signal
Number connecting line 3, completes the transmission of signal, has the advantages that simple and reliable.
Further, the shell of the signal output seat 6 of the present embodiment is made of metal material, and signal can be effectively prevent dry
It disturbs, improves the accuracy of test.Omron seat in the prior art can be used in the signal output seat 6 of the present embodiment.The present embodiment
Printed circuit board 5 on every differential signal cabling using packet ground design, with reduce high speed transmission of signals interference.
Further, the signal connecting line 3 of the present embodiment is flexible flat cable (FFC), keeps on line more convenient, reduces and survey
Cost is tried, testing efficiency is improved.Band buckle-type FFC line in the prior art can be used in the signal connecting line 3, to export with signal
Seat 6 is detachably connected, convenient for assembly and replacement.
In the present embodiment, rack 1 includes column 11 and transition plates 12, and transition plates 12 is mounted on column 11, transition plates 12
Between chip main board 200 and signal converting component, the through-hole 121 passed through for testing needle 2 is offered in transition plates 12.Into one
The testing needle 2 on step ground, the present embodiment is arranged with testing needle set (not indicating) outside, and through-hole 121 is matched with test needle guard, is being assembled
When, first testing needle can be covered in the through-hole 121 of insertion transition plates 12, then testing needle 2 is inserted into corresponding test needle guard, just
In realizing docking for testing needle 2 and the LVDS/V-by-one signal testing point on chip main board 200.
In the present embodiment, rack 1 further includes gland 13, and gland 13 is located at the top of transition plates 12, and chip main board 200 is located at
Between gland 13 and transition plates 12, gland 13 is equipped with the compression leg 131 for abutting the upper surface of chip main board 200.The present embodiment column
11 quantity is four, and gland 13, transition plates 12 and chip main board 200 are mounted on four columns in rectangle and surrounding correspondence
On 11, in order to improve the stability of assembly, when chip main board 200 is mounted in rack 1, compression leg 131 abuts chip main board 200
Upper surface, be firmly mounted to chip main board 200 in rack 1, be conducive to test.
Further, in this embodiment gland 13 is sheathed on column 11 and can slide up and down along column 11.By chip main board
After 200 are assemblied in rack 1, gland 13 is adjusted, so that gland 13 slides up and down on column 11, and then it is suitable to adjust compression leg 131
Locality abuts the upper surface of chip main board 200.
The transition plates 12 of the present embodiment is acrylic offset plate, and acrylic offset plate is transparent products, facilitates observation.It is understood that
, it is provided with positioning column (not shown) in the present embodiment transition plates 12, chip main board 200 is equipped with for cooperating with positioning column
Location hole realizes the accurate assembly of chip main board 200 and rack 1.
The above is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills
Art field, is included within the scope of the present invention.
Claims (10)
1. a kind of LVDS/V-by-one signal testing jig of chip main board, which is characterized in that including rack, the rack is used
In installing the chip main board, the test fixture further include testing needle, signal converting component and with the signal converting group
The signal connecting line of part connection, the LVDS/ for the chip main board that the signal converting component is used to measure the testing needle
V-by-one signal is exported to the signal connecting line；The signal converting component includes adapter, and the adapter offers
LVDS/V-by- on the corresponding and matched stitch hole with the testing needle, one end of the testing needle and the chip main board
The other end of the docking of one signal testing point, the testing needle is inserted into the stitch hole.
2. the LVDS/V-by-one signal testing jig of chip main board according to claim 1, which is characterized in that described
LVDS/V-by-one signal testing point is believed using standardized packages arrangement design, the stitch hole and the LVDS/V-by-one
The quantity of number test point it is consistent and one by one face arrange, each LVDS/V-by-one signal testing point and the institute with its face
State a settable testing needle between stitch hole.
3. the LVDS/V-by-one signal testing jig of chip main board according to claim 1, which is characterized in that described
Signal converting component further includes printed circuit board and signal output seat, and the adapter and signal output seat are installed in institute
It states on printed circuit board, the signal connecting line connects the signal and exports seat.
4. the LVDS/V-by-one signal testing jig of chip main board according to claim 3, which is characterized in that described
Signal connecting line is flexible flat cable and is detachably connected with signal output seat.
5. the LVDS/V-by-one signal testing jig of chip main board according to claim 3, which is characterized in that described
The shell of signal output seat is made of metal material.
6. the LVDS/V-by-one signal testing jig of chip main board according to any one of claims 1-5, feature
Be, the rack includes column and the transition plates that is mounted on the column, the transition plates be located at the chip main board with
Between the signal converting component, the through-hole passed through for the testing needle is offered in the transition plates.
7. the LVDS/V-by-one signal testing jig of chip main board according to claim 6, which is characterized in that described
Rack further includes gland, and the gland is located at the top of the transition plates, and the chip main board is located at the gland and the mistake
Between cab apron, the gland is equipped with the compression leg for abutting the upper surface of the chip main board.
8. the LVDS/V-by-one signal testing jig of chip main board according to claim 7, which is characterized in that described
Gland is sheathed on the column and can slide up and down along the column.
9. the LVDS/V-by-one signal testing jig of chip main board according to claim 6, which is characterized in that described
It is arranged with testing needle set outside testing needle, the through-hole is matched with the test needle guard.
10. the LVDS/V-by-one signal testing jig of chip main board according to claim 6, which is characterized in that described
Transition plates is acrylic offset plate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2018204588035 | 2018-03-30 | ||
| CN201820458803 | 2018-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109116214A true CN109116214A (en) | 2019-01-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810888080.7A Pending CN109116214A (en) | 2018-03-30 | 2018-08-06 | The LVDS/V-by-one signal testing jig of chip main board |
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|---|---|
| CN (1) | CN109116214A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111090018A (en) * | 2019-12-27 | 2020-05-01 | 苏州浪潮智能科技有限公司 | Testing device for server fan board |
| CN114446210A (en) * | 2022-01-28 | 2022-05-06 | 冠捷显示科技（厦门）有限公司 | Scaler mainboard detection method adaptive to liquid crystal panel |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111090018A (en) * | 2019-12-27 | 2020-05-01 | 苏州浪潮智能科技有限公司 | Testing device for server fan board |
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| CN114446210A (en) * | 2022-01-28 | 2022-05-06 | 冠捷显示科技（厦门）有限公司 | Scaler mainboard detection method adaptive to liquid crystal panel |
| CN114446210B (en) * | 2022-01-28 | 2023-12-29 | 冠捷显示科技（厦门）有限公司 | Scaler main board detection method adapting to liquid crystal panel |
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| CB03 | Change of inventor or designer information |
Inventor after: Wu Hongkai Inventor after: Liang Yanwen Inventor after: Li Yesheng Inventor before: Liang Yanwen Inventor before: Li Yesheng |
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Application publication date: 20190101 |
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