JP2011232076A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device having high versatility that can perform a favorable testing with less crosstalk even if an efficient way to use pins is employed.SOLUTION: The semiconductor testing device comprises: a pin electronics card for applying signals to devices under test (DUT) and executing measurement of signals generated from the DUT; a device board or probe card for contacting pin terminals of the DUT; a wiring conversion part for making the measurement pins on the pin electronics card correspond to desired pin terminals of the DUT; and a fitting part for connecting between the wiring conversion part and the device board or probe card using a connector. In this device, a band limiting circuit is inserted between the measurement pins on the pin electronics card and the DUT pin terminals.

Description

  The present invention includes a pin electronics card that performs signal application to a device under test (DUT) and measurement of a signal generated from the DUT, a device board or probe card that contacts a pin terminal of the DUT, and the pin electronics. A wiring conversion unit for causing a measurement pin of the card to correspond to a desired pin terminal of the DUT, and a fitting unit for connecting the wiring conversion unit and the device board or the probe card with a connector, and a pin of the fitting unit The present invention relates to a semiconductor test apparatus in which the allocation is configured such that both sides of two adjacent signal pins are sandwiched between a pair of ground pins.

Patent Document 1 discloses a detailed technical disclosure of the basic configuration of the semiconductor test apparatus.
FIG. 5 is a functional block diagram showing a configuration of a conventional semiconductor test apparatus. The test head 10 has a function of applying a signal to the device under test (DUT) 61,... 6n and measuring a signal generated from the DUT, and measuring the operation of the device and the state of the signal to determine pass / fail. A pin electronics card 20 is mounted. Functional circuits necessary for the semiconductor test apparatus including the pin electronics card 20 are mounted on the test head 10.

  Further, a device board or probe card 50 that contacts the pin terminals of the DUTs 61,... 6n, and a wiring conversion unit 30 for making the measurement pins of the pin electronics card 20 correspond to the desired pin terminals of the DUTs 61,. The wire conversion section and a fitting section 40 for connecting the device board or the probe card 50 with a connector are provided.

  In recent years, with the increase in device speed, semiconductor test apparatuses are also required to operate at high speed. On the other hand, along with the increase in size of wafers, a test apparatus capable of measuring many DUTs simultaneously is also required. As a result, the number of signal pins in the semiconductor test apparatus tends to increase.

  However, the number of connection pins of the fitting portion 40 to be connected to the connector is physically limited, and it may be difficult to arbitrarily increase it as required. In recent years, there are cases where the connection pin of the fitting portion is effectively used by the following usage method.

  FIG. 6 is a plan view showing an example of usage of signal pins. The pin assignment at the fitting portion 40 is a comparison between the general example of FIG. 6 (A) and the effective usage example of FIG. 6 (B). It is. As in the general example of FIG. 6A, the signal pin “S” and the ground pin “G” are arranged alternately in the prior art. The two adjacent paths are made into a set, and this set is sandwiched between a pair of ground pins “G”. In this usage mode, about 1.33 times as many signal pins as the same number of connection pins can be used effectively.

JP-A-9-304482

  In the case of the effective usage example shown in FIG. 6B, the crosstalk becomes larger than that of the general example. FIG. 7 is a characteristic diagram for explaining a difference in crosstalk between signal pins corresponding to the use form of the signal pins.

  It has signal pins S1 and S2, and S1 is a signal moving side (perpetrator) and S2 is a side affected by S1 (victim). S2 is dropped to the ground level via a terminating resistor for simple explanation.

FIG. 7A shows crosstalk in the case of a general example, and FIG. 7B shows crosstalk in an effective use example. In (a) and (b), (A) is a plan view showing the use form of the pin, (B) is a step response waveform at the S1 end (DUT end), and (C) is at the S2 end (DUT end). Crosstalk waveform.

  In the general example of FIG. 7A, the crosstalk is small due to the ground shielding effect between S1 and S2 and the large distance between S1 and S2. However, in the example of effective use in FIG. 7 (b), the distance between S1 and S2 is small and there is no ground between them, so the amount of crosstalk is larger than in FIG. 7 (a). A large crosstalk affects the rising / falling edge waveform of the signal pin, and prevents good quality testing.

  For this reason, general examples are often used as pin assignments in ordinary semiconductor test equipment. In particular, when performing a high-speed test, the crosstalk adversely affects the timing accuracy of the signal, so the general pin assignment is adopted. However, the number of simultaneous measurement DUTs at a relatively low speed as in the wafer test or the like. In an application that takes a lot of information, the pin assignment of an effective usage example may be adopted.

  An object of the present invention is to realize a highly versatile semiconductor test apparatus capable of performing a good test with little crosstalk even when the pin is effectively used.

In order to achieve such a subject, the present invention has the following configuration.
(1) A pin electronics card that executes signal application to a device under test (DUT) and measurement of a signal generated from the DUT, a device board or probe card that contacts a pin terminal of the DUT, and the pin electronics card In a semiconductor test apparatus comprising a wiring conversion unit for making the measurement pin correspond to a desired pin terminal of the DUT, and a fitting unit for connecting the wiring conversion unit and the device board or the probe card with a connector,
A semiconductor test apparatus, wherein a band limiting circuit is inserted between a measurement pin of the pin electronics card and a pin terminal of the DUT.

(2) The semiconductor test apparatus according to (1), wherein the band limiting circuit is provided between the wiring conversion unit and the fitting unit.

(3) The semiconductor test apparatus according to (1) or (2), wherein the band limiting circuit is provided between the fitting portion and the device board or probe card.

(4) The semiconductor test apparatus according to any one of (1) to (3), wherein the band limiting circuit is detachable.

(5) The semiconductor test apparatus according to any one of (1) to (4), wherein the band limiting circuit includes a low-pass filter.

(6) The semiconductor test apparatus according to any one of (1) to (5), wherein the band limiting circuit includes jumper means for invalidating a filter characteristic.

According to the present invention, the following effects can be expected.
(1) Even if the pin electronics card itself has a high slew rate as a result of inserting a band limiting circuit between the measurement pin of the pin electronics card and the pin terminal of the DUT, the cutoff frequency of the band limiting circuit is appropriate. The same pin electronics card is used for cases where signal pins must be used effectively due to multi-pin requirements and when general pin assignment is used for the mating part due to high-speed requirements. It is possible to cope with various tests, and the versatility of the apparatus is improved.
(2) It also leads to reduction in the development man-hours and development costs of semiconductor test equipment.

It is a functional block diagram which shows one Example of the semiconductor testing apparatus to which this invention is applied. It is a circuit block diagram at the time of applying the band-limiting circuit of this invention in a signal pin effective utilization form. It is a characteristic view explaining the crosstalk reduction effect by the band limiting circuit of the present invention. It is a characteristic figure which shows the example of analysis of the step response by the band limiting circuit of this invention. It is a functional block diagram which shows the structure of the conventional semiconductor test apparatus. It is a top view which shows the utilization form example of a signal pin. It is a characteristic view explaining the difference of the crosstalk between the signal pins corresponding to a signal pin utilization form.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of a semiconductor test apparatus to which the present invention is applied. The same elements as those of the conventional configuration described with reference to FIG.

  A feature of the present invention added to the conventional configuration described in FIG. 5 is a configuration in which a band limiting circuit 100 is inserted between the wiring conversion unit 30 and the fitting unit 40. Examples of the band limiting circuit 100 include an LPF (low-pass filter) using an inductive element L, a capacitive element C, and a resistive element R.

  By designing the band limiting circuit 100 to an appropriate cut-off frequency, the rising / falling slew rate of S1 (perpetrator) described with reference to FIG. 7 can be reduced. In general, it is well known that reducing the passing signal slew rate of the perpetrator S1 reduces crosstalk to the victim (here, S2). By adopting the configuration of FIG. Can be reduced.

  Since the cutoff frequency of the crosstalk and the band limiting circuit has a trade-off relationship, a suitable test can be performed by selecting an appropriate cutoff frequency according to the type of DUT to be tested and the test program.

  For example, when the general example of FIG. 6A is adopted as the pin usage form in the fitting unit 40, since the crosstalk is small, it becomes possible to set the cut-off frequency of the band limiting circuit 100 to be higher, and the higher speed. Test can be carried out.

  When the example of effective use in FIG. 6B is adopted, crosstalk increases when a high-speed signal is passed. Therefore, the cutoff frequency of the band limiting circuit 100 is set appropriately, and crosstalk is used for the test. It is possible to optimize the test speed while eliminating the adverse effects.

  FIG. 2 is a circuit configuration diagram in the case where the band limiting circuit of the present invention is applied in the signal pin effective use form. The cut-off frequency of the band limiting circuit 100 has an appropriate value depending on the type of DUT and test program.

  For this purpose, the band limiting circuit 100 is provided with a second fitting part, and is connected to the wiring conversion part 30 side of the fitting part 40 or the device port or probe card 50 side so that the band limiting circuit 100 can be attached and detached. It can be.

  When such a configuration is used, for example, even when a test target device or a test program of an operating semiconductor test apparatus is changed and the cut-off frequency of the band limiting circuit 100 needs to be changed, the wiring conversion unit 30 can be changed. Without replacement, only the band limiting circuit 100 can be replaced, so that maintenance costs can be reduced and the operating rate of the semiconductor test apparatus can be expected.

  FIG. 3 is a characteristic diagram for explaining the crosstalk reducing effect of the band limiting circuit according to the present invention. FIG. 3A shows a step response waveform at the S1 end (DUT end), where the solid line F1 is a response without a band limiting circuit, and the broken line F2 is a response characteristic with an additional band limiting circuit. FIG. 3B shows a crosstalk waveform at the S2 end (DUT end), where the solid line P1 shows the response without the band limiting circuit and the broken line P2 shows the response characteristic with the band limiting circuit added.

  FIG. 4 is a characteristic diagram showing an example of step response analysis by the band-limiting circuit of the present invention. A 50-ohm line 100 mm using a general dielectric substrate typified by FR-4 is 1 GHz (at 10-90%). The response at the observation point when a waveform of 1.6ps amplitude of 350ps) was input was analyzed with or without a band limiting circuit.

The relationship between rise time and frequency is
Tr (10-90%) = 0.35 / Fmax
Tr (10-90%): Rise time between 10% -90% (s)
Fmax: The highest frequency component in the waveform
The conversion is performed using a well-known formula.

In this analysis, as an example, an example is shown in which a low-pass filter designed at 400 MHz as a band limiting circuit 100 is added at the midpoint of the line.
When there is no band limiting circuit, the frequency after conversion is 945 MHz because it is 370 ps at 10-90%.
When the band limiting circuit is added, the frequency is 415 MHz after conversion because it is 843 ps at 10-90%, which indicates that the object of the present invention can be realized by adding the band limiting circuit.

  As an embodiment of the present invention, by providing an appropriate jumper means that can invalidate the filter characteristics in the band limiting circuit 100, a semiconductor test apparatus having a conventional configuration that does not include the band limiting circuit while the band limiting circuit is mounted. It is possible to return to

  In the embodiment of FIG. 1, the band limiting circuit 100 is disposed between the wiring conversion unit 30 and the fitting unit 40, but may be inserted between the fitting unit 40 and the device port or probe card 50. Theoretically, the band limiting circuit 100 can be expected to have the same effect regardless of the location between the measurement pin terminal of the pin electronics card 20 and the pin terminal of the DUT.

DESCRIPTION OF SYMBOLS 10 Test head 20 pin electronics card 30 Wiring conversion part 40 Fitting part 50 Device board or probe card 61, ... 6n DUT
100 Bandwidth limiter circuit

Claims (6)

A pin electronics card that performs signal application to a device under test (DUT) and measurement of a signal generated from the DUT, a device board or probe card that contacts a pin terminal of the DUT, and a measurement pin of the pin electronics card In a semiconductor test apparatus comprising: a wiring conversion unit for corresponding to a desired pin terminal of the DUT; and a fitting unit for connecting the wiring conversion unit and the device board or the probe card to a connector.
A semiconductor test apparatus, wherein a band limiting circuit is inserted between a measurement pin of the pin electronics card and a pin terminal of the DUT.   The semiconductor test apparatus according to claim 1, wherein the band limiting circuit is provided between the wiring conversion unit and the fitting unit.   3. The semiconductor test apparatus according to claim 1, wherein the band limiting circuit is provided between the fitting portion and the device board or probe card.   The semiconductor test apparatus according to claim 1, wherein the band limiting circuit is detachable.   The semiconductor test apparatus according to claim 1, wherein the band limiting circuit includes a low-pass filter.   6. The semiconductor test apparatus according to claim 1, wherein the band limiting circuit includes jumper means for invalidating a filter characteristic.