CN109103252A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN109103252A CN109103252A CN201710468976.5A CN201710468976A CN109103252A CN 109103252 A CN109103252 A CN 109103252A CN 201710468976 A CN201710468976 A CN 201710468976A CN 109103252 A CN109103252 A CN 109103252A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 128
- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 238000000926 separation method Methods 0.000 claims abstract description 67
- 238000009413 insulation Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 207
- 238000005530 etching Methods 0.000 claims description 39
- 238000000137 annealing Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 238000011065 in-situ storage Methods 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 15
- 238000001312 dry etching Methods 0.000 claims description 13
- 238000001020 plasma etching Methods 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 25
- 229910004074 SiF6 Inorganic materials 0.000 description 15
- 239000007789 gas Substances 0.000 description 15
- -1 hexafluoro silicon ammonia Chemical compound 0.000 description 15
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 12
- 229910021529 ammonia Inorganic materials 0.000 description 7
- 239000006227 byproduct Substances 0.000 description 7
- 238000009825 accumulation Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910004014 SiF4 Inorganic materials 0.000 description 2
- 230000004087 circulation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical group 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
Abstract
A kind of semiconductor devices and forming method thereof, wherein method includes: offer semiconductor substrate, has fin in the semiconductor substrate；The target separation layer of covering fin partial sidewall is formed in the semiconductor substrate surface, target separation layer includes the second target area positioned at semiconductor substrate surface and with the first object area of fin adjoining and positioned at semiconductor substrate surface and with the adjoining of first object area, there is recess, the side wall of the recess exposes fin in the first object area；After forming target separation layer, gate structure is formed, the gate structure is across the atop part surface and partial sidewall surface of fin, covering fin, and the gate structure is located in target insulation surface and the recess.The method improves the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Source region and position positioned at the gate structure of semiconductor substrate surface, in the semiconductor substrate of gate structure side
Drain region in the semiconductor substrate of the gate structure other side.The working principle of MOS transistor is: apply voltage in gate structure,
Switching signal is generated by adjusting the electric current of gate structure bottom channel.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.And fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of sidewall surfaces described in covering part are located at grid
Source region in the fin of pole structure side and the drain region in the fin of the gate structure other side.
However, the performance for the semiconductor devices that existing fin formula field effect transistor is constituted is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, to improve the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide semiconductor lining
Bottom has fin in the semiconductor substrate；The semiconductor substrate surface formed covering fin partial sidewall target every
Absciss layer, target separation layer include positioned at semiconductor substrate surface and with the first object area of fin adjoining and positioned at semiconductor
Substrate surface and second target area adjacent with first object area have recess, the side of the recess in the first object area
Wall exposes fin；After forming target separation layer, gate structure is formed, the gate structure is across the portion of fin, covering fin
Divide top surface and partial sidewall surface, and the gate structure is located in target insulation surface and the recess.
Optionally, the method for forming the target separation layer includes: to form initial isolation in the semiconductor substrate surface
Layer, the side wall of the initial seal coat covering fin and the top surface for exposing fin；It is etched using Certas etching technics
Initial seal coat makes initial seal coat form intermediate isolating layer, and the top surface of intermediate isolating layer is lower than the top surface of fin,
Intermediate isolating layer includes positioned at semiconductor substrate surface and with the first middle area of fin adjoining and positioned at semiconductor substrate table
Face and second middle area adjacent with the first middle area；Intermediate isolating layer, SiCoNi etching are etched using SiCoNi etching technics
Technique is greater than the etch rate to the second middle area to the etch rate of the first middle area, and intermediate isolating layer is made to form the target
Separation layer, and the first middle area is made to form the first object area of target separation layer, so that the second middle area is formed target separation layer
Second target area.
Optionally, the material of the initial seal coat, intermediate isolating layer and target separation layer is silica.
Optionally, the Certas etching technics include carry out after long-range dry etching and long-range dry etching it is first former
Position annealing；The parameter of the long-range dry etching includes: that the gas of use includes NH3And NF3, NH3Flow be 200sccm~
500sccm, NF3Gas flow be 20sccm~200sccm, chamber pressure is 0.1torr~760torr, and temperature is -40 to take the photograph
Family name degree~25 degree Celsius；The parameter of first in-situ annealing includes: that temperature is 60 degrees Celsius~100 degrees Celsius, chamber pressure
For 0.1torr~760torr.
Optionally, the SiCoNi etching technics includes carrying out after remote plasma etching is etched with remote plasma
The second in-situ annealing；The parameter of the remote plasma etching includes: that the gas of use includes NH3And NF3, NH3Flow
For 200sccm~500sccm, NF3Gas flow be 20sccm~200sccm, source radio-frequency power be 50 watts~2000 watts, partially
Setting voltage is 30 volts~500 volts, and chamber pressure is 0.1torr~760torr, and temperature is -40 degrees Celsius~25 degrees Celsius；It is described
The parameter of second in-situ annealing includes: that temperature is 60 degrees Celsius~100 degrees Celsius, and chamber pressure is 0.1torr~760torr.
Optionally, the top surface of second middle area to fin top surface have first distance, described second
The top surface of the top surface of target area to fin has second distance；The first distance be fin height 5%~
20%, the second distance is the 30%~60% of first distance.
Optionally, before forming the initial seal coat, the top surface of the fin has mask layer；Described in formation
After initial seal coat, initial seal coat covers the side wall of fin and the side wall of mask layer and the top surface for exposing mask layer；
The forming method of the semiconductor devices further include: after forming initial seal coat, and carry out the Certas etching technics it
Before, mask layer is removed, the top surface of fin is exposed.
Optionally, further includes: before forming the initial seal coat, aoxidize the side wall of the fin.
Optionally, the technique for aoxidizing the side wall of the fin includes situ steam method of formation.
Optionally, further includes: before forming the initial seal coat, round and smooth processing is carried out to the apex angle of fin.
Optionally, the round and smooth processing includes annealing process.
Optionally, it includes H that the parameter of the annealing process, which includes: the gas of use,2And Ar, annealing temperature are 100 Celsius
~400 degrees Celsius of degree.
Optionally, the depth of the recess is 1nm~5nm.
Optionally, the bottom width of the fin is greater than the top width of the fin.
Optionally, further includes: before forming gate structure, form dummy gate structure, dummy gate structure is across the fin
Portion, cover fin atop part surface and partial sidewall surface, and the dummy gate structure be located at target insulation surface with
In the recess, the dummy gate structure includes pseudo- gate electrode layer, and pseudo- gate electrode layer is across the fin；In the dummy grid knot
Source and drain doping area is formed in the fin of structure two sides；After forming source and drain doping area, interlayer is formed in the target insulation surface and is situated between
Matter layer, interlayer dielectric layer cover dummy gate structure side wall, fin and source and drain doping area and the top table for exposing dummy gate structure
Face；After forming interlayer dielectric layer, pseudo- gate electrode layer is removed, gate openings are formed；The grid is formed in the gate openings
Structure.
The present invention also provides a kind of semiconductor devices, comprising: semiconductor substrate；Fin in semiconductor substrate；Position
In semiconductor substrate surface and the target separation layer of covering fin partial sidewall, target separation layer includes being located at semiconductor substrate table
Face and the first object area adjacent with fin and positioned at semiconductor substrate surface and second target adjacent with first object area
Area, has recess in the first object area, and the side wall of the recess exposes fin；Gate structure, the gate structure are horizontal
Atop part surface and partial sidewall surface across fin, covering fin, and the gate structure is located at target insulation surface
In the recess.
Optionally, the material of the target separation layer includes silica.
Optionally, the depth of the recess is 1nm~5nm.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor devices that technical solution of the present invention provides, target separation layer, the target are formd
There is recess, the side wall of the recess exposes fin in the first object area of separation layer.After forming gate structure, part of grid pole
Structure is located in the recess, make gate structure and institute across fin in lean on close-target insulation surface region directly connect
Touching, thus gate structure to institute across fin in by close-target insulation surface region control ability enhancing, improve
The performance of semiconductor devices.
Technical solution of the present invention provide semiconductor devices in, gate structure and institute across fin in by close-target isolation
The region of layer surface directly contacts, thus gate structure to across fin in by close-target insulation surface region control
Ability enhancing processed, improves the performance of semiconductor devices.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process；
Fig. 4 to Figure 13 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process.
With reference to Fig. 1, semiconductor substrate 100 is provided, there is fin 110 in the semiconductor substrate 100；In semiconductor substrate
100 surfaces form covering 110 side wall of fin and expose the initial seal coat 120 of 110 top surface of fin, initial seal coat
120 top surface and the top surface of fin 110 flush.
With reference to Fig. 2, it is etched back to the initial seal coat 120 (with reference to Fig. 1), initial seal coat 120 is made to form covering fin
The target separation layer 121 of 110 partial sidewalls.
With reference to Fig. 3, after forming target separation layer 121, gate structure 130 is formed, the gate structure 130 is across fin
110, the atop part surface and partial sidewall surface of fin 110 are covered, and the gate structure 130 is located at target separation layer
121 surfaces.
However, the performance for the semiconductor devices that the above method is formed is poor, it has been investigated that, reason is:
During being etched back to the initial seal coat 120, part that initial seal coat 120 and fin 110 contact by
The blocking of fin 110 and cause etch direction be restricted.And during being etched back to the initial seal coat 120, initially every
Absciss layer 120 does not have the blocking of fin 110, therefore region of the initial seal coat 120 far from fin 110 far from the region of fin 110
By more multidirectional etching.After forming target separation layer 121, target separation layer 121 is higher than target close to the surface of fin 110
Surface of the separation layer 121 far from fin 110.
Secondly, in order to improve gate structure 130 to the control ability of fin 110, need to make gate structure 130 across fin
The height of 110 side wall of portion is larger.Correspondingly, the height for 110 side wall of fin that target separation layer 121 exposes is larger.So need
It is etched back to the biggish depth of initial seal coat 120, the time for being etched back to initial seal coat 120 is longer, correspondingly, target is isolated
Thickness in layer 121 close to 110 region of fin is much larger than the thickness in target separation layer 121 far from 110 region of fin.
To sum up, cause gate structure 130 across fin 110 in lean on close-target separation layer 121 region, gate structure
Between 130 and fin 110 with more target separation layer 121 material, cause gate structure 130 to across fin 110
In by close-target separation layer 121 region control ability reduce, it is lower so as to cause the performance of semiconductor devices.
On this basis, the present invention provides a kind of forming method of semiconductor devices, forms target separation layer, target isolation
Floor includes positioned at semiconductor substrate surface and the first object area adjacent with fin and being located at semiconductor substrate surface and with the
The second adjacent target area of one target area has recess in first object area, and the side wall of recess exposes fin；It is formed later horizontal
Gate structure across fin, and gate structure is located in target insulation surface and recess.The method makes semiconductor devices
Performance improves.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 13 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 4, semiconductor substrate 200 is provided, there is fin 210 in the semiconductor substrate 200.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；The semiconductor substrate 200 can also be with
It is the semiconductor materials such as silicon, germanium, SiGe, GaAs；The semiconductor substrate 200 can be body material, be also possible to compound
Structure, such as silicon-on-insulator；The semiconductor substrate 200 can also be other semiconductor materials, no longer illustrate one by one here.This
In embodiment, the material of the semiconductor substrate 200 is silicon.
The fin 210 is formed by patterned semiconductor substrate 200.Alternatively, forming fin on semiconductor substrate 200
Portion's material layer forms fin 210 by graphical fin material layer.
The quantity of the fin 210 is one or more.
The top surface of the fin 210 has mask layer 220.
In the present embodiment, the mask layer 220 is laminated construction, and the mask layer 220 includes being located at 210 top of fin
First mask layer (not shown) on surface and the second mask layer (not shown) positioned at the first mask layer top surface.Described first
The material of mask layer includes silica, and the material of second mask layer includes silicon nitride.
First mask layer can reduce the second mask layer to the stress of 210 top surface of fin.
In other embodiments, the mask layer is single layer structure, and the material of the mask layer includes silicon nitride or nitrogen oxygen
SiClx.
In one embodiment, the method for forming the fin 210 and mask layer 220 includes: in the semiconductor substrate
Fin material layer is formed on 200；Mask layer is formed in the fin material surface；The graphical mask layer and
Fin material layer forms mask layer 220 and fin 210.The corresponding fin material layer of the fin 210, the mask layer 220
The corresponding mask layer.
It is influenced by etching technics, the bottom width of fin 210 is greater than the top width of fin 210.The fin 210
Bottom width and top width refer to be parallel to 200 surface of semiconductor substrate and perpendicular to 210 extending direction of fin
On size.
Then, the target separation layer of covering 210 partial sidewall of fin, target are formed on 200 surface of semiconductor substrate
Separation layer includes positioned at 200 surface of semiconductor substrate and with the first object area of the adjoining of fin 210 and positioned at semiconductor substrate
200 surfaces and second target area adjacent with first object area have recess, the side wall of the recess in the first object area
Expose fin 210.
The method for forming the target separation layer includes: to form initial seal coat, institute on 200 surface of semiconductor substrate
It states the side wall of initial seal coat covering fin 210 and exposes the top surface of fin 210；It is etched using Certas etching technics
Initial seal coat, makes initial seal coat form intermediate isolating layer, and the top surface of intermediate isolating layer is lower than the top table of fin 210
Face, intermediate isolating layer include positioned at 200 surface of semiconductor substrate and with the first middle area of the adjoining of fin 210 and positioned at half
200 surface of conductor substrate and second middle area adjacent with the first middle area；Intermediate isolating is etched using SiCoNi etching technics
Layer, SiCoNi etching technics are greater than the etch rate to the second middle area to the etch rate of the first middle area, make intermediate isolating
Layer forms the target separation layer, and the first middle area is made to form the first object area of target separation layer, makes the second middle area shape
At the second target area of target separation layer.
In the present embodiment, further includes: before forming the initial seal coat, aoxidize the side wall of the fin 210；In shape
Before the initial seal coat, round and smooth processing is carried out to the apex angle of fin 210.
With reference to Fig. 5, the side wall of the fin 210 is aoxidized；Round and smooth processing is carried out to the apex angle of fin 210.
The technique for aoxidizing the side wall of the fin 210 is wet process oxidation technology or dry oxidation technique.
After the side wall for aoxidizing the fin 210, oxide layer 230 is formed in the sidewall surfaces of fin 210.
The effect for aoxidizing the fin 210 includes: the quarter for repairing 210 sidewall surfaces of fin during forming fin 210
Deteriorate wound.
In the present embodiment, the technique for aoxidizing the side wall of the fin 210 is situ steam method of formation, and advantage includes: oxidation
It is comparatively dense that oxide layer 230 is formed after the side wall of fin 210, it is preferable to the reparation of the side wall of fin 210.
The effect of the round and smooth processing includes: that the apex angle of fin 210 is made to become more round and smooth, and subsequent gate structure is across fin
Portion 210 avoids the electric field strength at 210 top surface edge of fin excessive, avoids fin after applying voltage on gate structure
Point discharge phenomenon occurs at 210 top surface edge of portion, and then avoids breakdown gate dielectric layer.
The round and smooth processing includes annealing process.
The parameter of the annealing process includes: that the gas of use includes H2And Ar, annealing temperature are 100 degrees Celsius~400
Degree Celsius.
After the side wall for aoxidizing the fin 210, round and smooth processing is carried out to the apex angle of fin 210；Alternatively, to fin 210
After apex angle carries out round and smooth processing, the side wall of the fin 210 is aoxidized.
The method to form target separation layer is introduced below with reference to Fig. 6 to Fig. 8.
Initial seal coat 240 is formed on 200 surface of semiconductor substrate, the initial seal coat 240 covers fin 210
Side wall and expose the top surface of fin 210.
With reference to Fig. 6, initial seal coat 240 is formed on 200 surface of semiconductor substrate, initial seal coat 240 covers fin
The side wall in portion 210 and the side wall of mask layer 220 and the top surface for exposing mask layer 220.
The material of the initial seal coat 240 includes silica.
The method for forming the initial seal coat 240 includes: to form initial isolation film in the semiconductor substrate 200
(not shown)；The initial isolation film is planarized until exposing the top surface of mask layer 220, forms initial seal coat 240.
With reference to Fig. 7, after forming initial seal coat 240, removal mask layer 220 (refers to Fig. 6), exposes the top of fin 210
Portion surface.
The technique for removing mask layer 220 is etching technics.
In other embodiments, initial isolation film is formed on a semiconductor substrate；It planarizes the initial isolation film and covers
Film layer forms initial seal coat until expose the top surface of fin, the side wall of the initial seal coat covering fin and sudden and violent
Expose the top surface of fin.
Initial seal coat 240 is made using Certas etching technics etching initial seal coat 240 (referring to Fig. 7) with reference to Fig. 8
Intermediate isolating layer 241 is formed, the top surface of intermediate isolating layer 241 is lower than the top surface of fin 210, intermediate isolating layer 241
Including being located at 200 surface of semiconductor substrate and with the first middle area of the adjoining of fin 210 and positioned at 200 table of semiconductor substrate
Face and second middle area adjacent with the first middle area.
Perpendicular to the extending direction of fin 210 and semiconductor lining is parallel to from the first middle area to the direction of the second middle area
The surface at bottom 200.
After removing mask layer 220, Certas etching technics is carried out.
In one embodiment, the Certas etching technics includes carrying out after long-range dry etching and long-range dry etching
The first in-situ annealing.The parameter of the long-range dry etching includes: that the gas of use includes NH3And NF3, NH3Flow be
200sccm~500sccm, NF3Gas flow be 20sccm~200sccm, chamber pressure be 0.1torr~760torr, such as
10torr, 100torr or 400torr, temperature are -40 degrees Celsius~25 degrees Celsius, such as 20 degrees Celsius；First in-situ annealing
Parameter include: temperature be 60 degrees Celsius~100 degrees Celsius, such as 80 degrees Celsius, chamber pressure be 0.1torr~760torr, such as
10torr, 100torr or 400torr.
Specifically, during the long-range dry etching, NH3And NF3The precursor gas and initial seal coat of composition
240 surfacings react to form hexafluoro silicon ammonia ((NH4)SiF6) and accumulation on 240 surface of initial seal coat；It is in situ described first
During annealing, under the action of temperature is 60 degrees Celsius~100 degrees Celsius, the hexafluoro silicon ammonia on 240 surface of initial seal coat
((NH4)SiF6) it is decomposed into gaseous by-product, gaseous by-product includes ocratation (SiF4), ammonia (NH3) and hydrogen fluoride
(HF)；The gaseous by-product is detached later.
It should be noted that the long-range dry etching and first in-situ annealing carry out in same etching machine bench.
Source radio-frequency power and bias voltage, NH are not applied in the long-range dry etching3And NF3The precursor gas of composition will not be by
It is plasmarized, therefore hexafluoro silicon the ammonia ((NH on 240 surface of initial seal coat4)SiF6) will not be influenced by plasma collision
240 surface different zones hexafluoro silicon ammonia ((NH of initial seal coat4)SiF6) thickness.Therefore, 240 surface of initial seal coat not same district
Domain hexafluoro silicon ammonia ((NH4)SiF6) thickness distribution is more uniform.
For convenience of explanation, the region for being used to correspond to the second middle area in initial seal coat 240 is known as initial middle area.
Hexafluoro silicon the ammonia ((NH on especially initial middle area surface4)SiF6) thickness distribution is more uniform.Therefore pass through the first in-situ annealing
Afterwards, the surface of the second middle area is preferable.
In the actual process, Certas etching technics includes the first sub- etching technics of several circulations, the first son etching work
Skill includes primary long-range dry etching, corresponding first in-situ annealing and the step for once detaching gaseous by-product accordingly
Suddenly.
It should be noted that during Certas etching technics, the portion of initial seal coat 240 and the contact of fin 210
Divide due to being stopped by fin 210 and is restricted etching direction, and the second middle area of initial seal coat 240 does not have fin
110 blocking, therefore the second middle area of initial seal coat 240 is by more multidirectional etching.Therefore, intermediate isolating layer is formed
After 241, the first middle area is slightly above the surface of the second middle area close to the surface of fin 210.
Due to the second middle area surface to fin 210 top surface distance be less than subsequent second target area surface extremely
The distance of the top surface of fin 210, therefore the depth of Certas etching technics etching initial seal coat 240 is smaller, correspondingly,
Keep the first middle area smaller close to the difference in height on the surface and the second middle area surface of fin 210.
The top surface of the top surface of second middle area to fin 210 has first distance.
In one embodiment, the first distance is the 5%~20% of 210 height of fin, such as 5%, 10% or 20%.
The height of the fin 210 refers to size of the fin 210 on 200 surface normal direction of semiconductor substrate.
With reference to Fig. 9, using SiCoNi etching technics etching intermediate isolating layer 241 (referring to Fig. 8), SiCoNi etching technics pair
The etch rate of first middle area is greater than the etch rate to the second middle area, and intermediate isolating layer 241 is made to form target separation layer
242, and the first middle area is made to form the first object area of target separation layer 242, so that the second middle area is formed target separation layer 242
The second target area.
The material of the target separation layer 242 includes silica.
The target separation layer 242 includes first object positioned at 200 surface of semiconductor substrate and adjacent with fin 210
Area and positioned at 200 surface of semiconductor substrate and second target area adjacent with first object area, has in the first object area
There is recess 243,243 side wall of being recessed exposes fin 210.
Perpendicular to the extending direction of fin 210 and semiconductor lining is parallel to from first object area to the direction of the second target area
The surface at bottom 200.
In 210 width direction of fin, the size in first object area is the 10%~40% of the second target area size.
In one embodiment, the SiCoNi etching technics includes that remote plasma etching and remote plasma are carved
The second in-situ annealing carried out after erosion；The parameter of the remote plasma etching includes: that the gas of use includes NH3And NF3,
NH3Flow be 200sccm~500sccm, NF3Gas flow be 20sccm~200sccm, source radio-frequency power be 50 watts~
2000 watts, such as 50 watts, 300 watts, 500 watts, 800 watts, 1500 watts or 2000 watts, bias voltage are 30 volts~500 volts, such as 30 volts,
50 volts, 100 volts, 200 volts or 500 volts, chamber pressure is 0.1torr~760torr, such as 10torr, 100torr or 400torr,
Temperature is -40 degrees Celsius~25 degrees Celsius, such as 20 degrees Celsius；The parameter of second in-situ annealing includes: that temperature is 60 Celsius
~100 degrees Celsius of degree, such as 80 degrees Celsius, chamber pressure are 0.1torr~760torr, such as 10torr, 100torr or
400torr。
Specifically, during remote plasma etching, NH3And NF3The precursor gas of composition is by plasma
Body and form ammonium fluoride (NH4F) plasma and bifluoride ammonia (NH4F2) plasma, it is formed by plasma and centre
241 surfacing of separation layer reacts to form hexafluoro silicon ammonia ((NH4)SiF6) and accumulation on 241 surface of intermediate isolating layer；Described
During two in-situ annealings, under the action of temperature is 60 degrees Celsius~100 degrees Celsius, the six of 241 surface of intermediate isolating layer
Fluorine silicon ammonia ((NH4)SiF6) it is decomposed into gaseous by-product, gaseous by-product includes ocratation (SiF4), ammonia (NH3) and fluorination
Hydrogen (HF)；The gaseous by-product is detached later.
It should be noted that remote plasma etching and second in-situ annealing in same etching machine bench into
Row.Apply source radio-frequency power and bias voltage, NH in the remote plasma etching3And NF3The precursor gas of composition by etc.
Gas ions, therefore hexafluoro silicon the ammonia ((NH on 241 surface of intermediate isolating layer4)SiF6) centre can be influenced by plasma collision
241 surface different zones hexafluoro silicon ammonia ((NH of separation layer4)SiF6) thickness.
Specifically, in remote plasma etching, 241 surface hexafluoro silicon ammonia of plasma collision intermediate isolating layer
((NH4)SiF6) during, blocking of first middle area by fin 210, so that the hexafluoro silicon on the first middle area surface
Ammonia ((NH4)SiF6) hexafluoro silicon ammonia ((NH by the degree of plasma collision less than the second middle area surface4)SiF6) by it is equal from
The degree of daughter collision.Correspondingly, accumulation is in the second middle area surface hexafluoro silicon ammonia ((NH4)SiF6) thickness be less than accumulation exist
First middle area surface hexafluoro silicon ammonia ((NH4)SiF6) thickness.Correspondingly, being greater than to the degree of the first middle area surface etch
To the degree of the second middle area surface etch.
In the actual process, SiCoNi etching technics includes the second sub- etching technics of several circulations, the second son etching work
Skill includes a remote plasma etching, corresponding second in-situ annealing and once detaches gaseous state pair accordingly accordingly
The step of product.
The top surface of the top surface of second target area to fin 210 has second distance.
In one embodiment, the first distance is the 5%~20% of 210 height of fin, and the second distance is the
The 30%~60% of one distance.It includes: to guarantee intermediate isolating layer 241 that first distance and second distance, which select the meaning of this range,
Size of one middle area close to the second middle area of surface distance surface of fin 210 is smaller, is unlikely to the depth of recess 243
It is small, and keep the flatness of the top surface of the second target area of target separation layer 242 preferable.
The depth of the recess 243 is 1nm~5nm.If the depth of the recess 243 selects the meaning of this range to include:
Keep the ability of subsequent gate structure filling recess 243 preferable, avoids the occurrence of cavity；And make gate structure to across fin
The control ability of bottom section in 210 is preferable.
After forming target separation layer 242, gate structure is formed, gate structure is across the portion of fin 210, covering fin 210
Divide top surface and partial sidewall surface, and gate structure is located in 242 surface of target separation layer and recess 243.
In the present embodiment, further includes: before forming gate structure, form dummy gate structure, dummy gate structure is across institute
State fin 210, covering fin 210, atop part surface and partial sidewall surface, and the dummy gate structure be located at target every
In 242 surface of absciss layer and the recess 243, the dummy gate structure includes pseudo- gate electrode layer, and pseudo- gate electrode layer is across the fin
Portion 210；Source and drain doping area is formed in the fin 210 of the dummy gate structure two sides；After forming source and drain doping area, in the mesh
It marks 242 surface of separation layer and forms interlayer dielectric layer, interlayer dielectric layer covers dummy gate structure side wall, fin 210 and source and drain doping
Area and the top surface for exposing dummy gate structure；After forming interlayer dielectric layer, pseudo- gate electrode layer is removed, gate openings are formed；
Gate structure is formed in the gate openings.
With reference to Figure 10, form dummy gate structure 250, dummy gate structure 250 is across the fin 210, covering fin 210
Atop part surface and partial sidewall surface, and the dummy gate structure 250 is located at 242 surface of target separation layer and the recess
In 243 (referring to Fig. 9).
The dummy gate structure 250 includes pseudo- gate dielectric layer 251 and the pseudo- gate electrode layer positioned at pseudo- 251 surface of gate electrode layer
252.Pseudo- gate electrode layer 251 is across the atop part surface and partial sidewall surface of the fin 210, covering fin 210.
In the present embodiment, the material of pseudo- gate dielectric layer 251 is silica, and the material of the pseudo electrode layer 252 is polysilicon.
In the present embodiment, pseudo- gate dielectric layer 251 is formed by aoxidizing 210 surface of fin, correspondingly, pseudo- gate dielectric layer
251 are only located at the partial sidewall surface and atop part surface of fin 210.Correspondingly, the puppet gate electrode layer 252 is located at pseudo- grid
251 surface of dielectric layer, the puppet gate electrode layer 252 also extend in 242 surface of partial target separation layer and recess 243.
In addition, since pseudo- gate dielectric layer 251 uses oxidation technology to be formed, so that the consistency of pseudo- gate dielectric layer 251
It is higher, so that the resistance to sparking of semiconductor devices can improve.
Specifically, forming pseudo- gate dielectric layer 251, advantage using situ steam method of formation (ISSG) are as follows: pseudo- in the present embodiment
Interface between gate dielectric layer 251 and fin 210 is preferable, is conducive to improve carrier mobility and semiconductor devices in fin 210
Reliability；The quality of pseudo- gate dielectric layer 251 is preferable, and the resistance to sparking of pseudo- gate dielectric layer 251 is preferable.
In other embodiments, pseudo- gate dielectric layer is formed by deposition, and pseudo- gate dielectric layer is across fin, pseudo- gate dielectric layer
Positioned at partial target insulation surface and recess inner wall, the atop part surface and partial sidewall surface that cover fin, correspondingly,
The puppet gate electrode layer is located at pseudo- gate electrode layer surface.
During forming dummy gate structure 250, the pseudo- grid exposure mask for being located at 250 top surface of dummy gate structure is also formed
Layer 260.The material of the puppet grid mask layer 260 includes silicon nitride.
With reference to Figure 11, source and drain doping area (not shown) is formed in the fin 210 of 250 two sides of dummy gate structure；Shape
Behind source and drain doping area, interlayer dielectric layer 270 is formed on 242 surface of target separation layer, interlayer dielectric layer 270 covers pseudo- grid
250 side wall of pole structure, fin 210 and source and drain doping area and the top surface for exposing dummy gate structure 250.
Specifically, the step of forming interlayer dielectric layer 270 includes: in the 242 surface forming layer of target separation layer
Between deielectric-coating, inter-level dielectric film covering dummy gate structure 250, fin 210, source and drain doping area and pseudo- grid mask layer 260；It is flat
Until exposing the top surface of dummy gate structure 250, formation interlayer is situated between for the smoothization inter-level dielectric film and pseudo- grid mask layer 260
Matter layer 270.
The material of the interlayer dielectric layer 270 is silica, silicon oxide carbide or silicon oxynitride.
With reference to Figure 12, after forming interlayer dielectric layer 270, pseudo- gate electrode layer 252 (referring to Figure 11) is removed, gate openings are formed
271。
In the present embodiment, dummy gate structure 250 is located at the marginal zone of semiconductor substrate 200, the edge of semiconductor substrate 200
Area is used to form peripheral logical circuit.Correspondingly, removing pseudo- gate electrode layer 252 and retaining pseudo- gate dielectric layer 251 and form grid
Opening 271.
In other embodiments, dummy gate structure is located at the core space of semiconductor substrate, 200 edge position of semiconductor substrate
In the periphery of semiconductor substrate core space, the core space of semiconductor substrate is used to form core circuit.Correspondingly, removing pseudo- grid electricity
Pole layer and pseudo- gate dielectric layer and form gate openings.
With reference to Figure 13, gate structure 280 is formed in the gate openings 271 (referring to Figure 12).
The gate structure 280 across fin 210, cover fin 210 atop part surface and partial sidewall surface, and
Gate structure 280 is located in 242 surface of target separation layer and recess 243.
The gate structure 280 includes being located at the gate dielectric layer 281 of 271 side of gate openings and bottom and positioned at grid
Gate electrode layer 282 on dielectric layer 281.
The material of the gate dielectric layer 281 is high K (K is greater than 3.9) dielectric material, and the material of the gate electrode layer 282 is
Metal.
In the present embodiment, gate dielectric layer 281 is also located on pseudo- gate dielectric layer 251.The gate dielectric layer 281 and pseudo- gate medium
The overall thickness of layer 251 is greater than the thickness of gate dielectric layer 281, therefore enhances the resistance to sparking of semiconductor devices.
In other embodiments, pseudo- gate electrode layer and pseudo- gate dielectric layer are removed and forms gate openings, correspondingly, gate medium
Without pseudo- gate dielectric layer between layer and fin.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method, Figure 13 is please referred to, is wrapped
It includes: semiconductor substrate 200；Fin 210 in semiconductor substrate 200；Positioned at 200 surface of semiconductor substrate and covering 210
The target separation layer 242 of fin partial sidewall, target separation layer 242 include positioned at 200 surface of semiconductor substrate and with fin 210
Adjacent first object area and the second target area positioned at 200 surface of semiconductor substrate and with the adjoining of first object area, it is described
There is recess 243 (referring to Fig. 9), the side wall of the recess 243 exposes fin 210 in first object area；Gate structure 280,
The gate structure 280 across fin 210, cover the atop part surface and partial sidewall surface of fin 210, and gate structure
280 are located in 242 surface of target separation layer and the recess 243 (referring to Fig. 9).
The material of the target separation layer 242 includes silica.
The depth of the recess 243 is 1nm~5nm.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, there is fin in the semiconductor substrate；
The target separation layer of covering fin partial sidewall is formed in the semiconductor substrate surface, target separation layer includes being located at half
Conductor substrate surface and the first object area adjacent with fin and it is located at semiconductor substrate surface and adjacent with first object area
The second target area, there is recess, the side wall of the recess exposes fin in the first object area；
After forming target separation layer, gate structure is formed, the gate structure is across the atop part surface of fin, covering fin
With partial sidewall surface, and the gate structure is located in target insulation surface and the recess.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that form the target separation layer
Method includes: to form initial seal coat in the semiconductor substrate surface, the side wall of initial seal coat covering fin and sudden and violent
Expose the top surface of fin；Initial seal coat is etched using Certas etching technics, initial seal coat is made to form intermediate isolating
Layer, the top surface of intermediate isolating layer are lower than the top surface of fin, intermediate isolating layer include positioned at semiconductor substrate surface and
The first adjacent middle area and the second middle area positioned at semiconductor substrate surface and with the adjoining of the first middle area with fin；
Intermediate isolating layer is etched using SiCoNi etching technics, SiCoNi etching technics is greater than to the etch rate of first middle area
The etch rate of two middle areas makes intermediate isolating layer form the target separation layer, and the first middle area is made to form target isolation
The first object area of floor makes the second middle area form the second target area of target separation layer.
3. the forming method of semiconductor devices according to claim 2, which is characterized in that the initial seal coat, centre
The material of separation layer and target separation layer is silica.
4. the forming method of semiconductor devices according to claim 3, which is characterized in that the Certas etching technics packet
Include the first in-situ annealing carried out after long-range dry etching and long-range dry etching；The parameter of the long-range dry etching includes:
The gas of use includes NH3And NF3, NH3Flow be 200sccm~500sccm, NF3Gas flow be 20sccm~
200sccm, chamber pressure are 0.1torr~760torr, and temperature is -40 degrees Celsius~25 degrees Celsius；First in-situ annealing
Parameter include: temperature be 60 degrees Celsius~100 degrees Celsius, chamber pressure be 0.1torr~760torr.
5. the forming method of semiconductor devices according to claim 3, which is characterized in that the SiCoNi etching technics packet
Include the second in-situ annealing carried out after remote plasma etching and remote plasma etching；The remote plasma etching
Parameter include: the gas of use include NH3And NF3, NH3Flow be 200sccm~500sccm, NF3Gas flow be
20sccm~200sccm, source radio-frequency power are 50 watts~2000 watts, and bias voltage is 30 volts~500 volts, and chamber pressure is
0.1torr~760torr, temperature are -40 degrees Celsius~25 degrees Celsius；The parameter of second in-situ annealing includes: that temperature is
60 degrees Celsius~100 degrees Celsius, chamber pressure is 0.1torr~760torr.
6. the forming method of semiconductor devices according to claim 2, which is characterized in that the top of second middle area
The top surface of surface to fin has first distance, and the top surface of top surface to the fin of second target area has
Second distance；The first distance be fin height 5%~20%, the second distance be first distance 30%~
60%.
7. the forming method of semiconductor devices according to claim 2, which is characterized in that forming the initial seal coat
Before, the top surface of the fin has mask layer；After forming the initial seal coat, initial seal coat covers the side of fin
The side wall of wall and mask layer and the top surface for exposing mask layer；The forming method of the semiconductor devices further include: formed
After initial seal coat, and before carrying out the Certas etching technics, mask layer is removed, the top surface of fin is exposed.
8. the forming method of semiconductor devices according to claim 7, which is characterized in that further include: it is described first being formed
Before beginning separation layer, the side wall of the fin is aoxidized.
9. the forming method of semiconductor devices according to claim 8, which is characterized in that aoxidize the side wall of the fin
Technique includes situ steam method of formation.
10. the forming method of semiconductor devices according to claim 7, which is characterized in that further include: it is described first being formed
Before beginning separation layer, round and smooth processing is carried out to the apex angle of fin.
11. the forming method of semiconductor devices according to claim 10, which is characterized in that the round and smooth processing includes moving back
Fire process.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that the parameter of the annealing process
The gas for including: use includes H2And Ar, annealing temperature are 100 degrees Celsius~400 degrees Celsius.
13. the forming method of semiconductor devices according to claim 1, which is characterized in that the depth of the recess is 1nm
~5nm.
14. the forming method of semiconductor devices according to claim 1, which is characterized in that the bottom width of the fin
Greater than the top width of the fin.
15. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: forming grid knot
Before structure, dummy gate structure is formed, dummy gate structure is across the fin, the atop part surface of covering fin and partial sidewall
Surface, and the dummy gate structure is located in target insulation surface and the recess, the dummy gate structure includes pseudo- grid electricity
Pole layer, pseudo- gate electrode layer is across the fin；Source and drain doping area is formed in the fin of the dummy gate structure two sides；Formation source
After leaking doped region, interlayer dielectric layer is formed in the target insulation surface, interlayer dielectric layer covers dummy gate structure side wall, fin
Portion and source and drain doping area and the top surface for exposing dummy gate structure；After forming interlayer dielectric layer, pseudo- gate electrode layer, shape are removed
At gate openings；The gate structure is formed in the gate openings.
16. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Fin in semiconductor substrate；
Positioned at semiconductor substrate surface and the target separation layer of covering fin partial sidewall, target separation layer includes being located at semiconductor
Substrate surface and the first object area adjacent with fin and adjacent positioned at semiconductor substrate surface and with first object area the
Two target areas, have recess in the first object area, and the side wall of the recess exposes fin；
Gate structure, the gate structure across fin, cover the atop part surface and partial sidewall surface of fin, and it is described
Gate structure is located in target insulation surface and the recess.
17. semiconductor devices according to claim 16, which is characterized in that the material of the target separation layer includes oxidation
Silicon.
18. semiconductor devices according to claim 16, which is characterized in that the depth of the recess is 1nm~5nm.
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| CN102637625A (en) * | 2011-02-11 | 2012-08-15 | 台湾积体电路制造股份有限公司 | End-to-end gap fill using dielectric film |
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| CN104733307A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN106684147A (en) * | 2015-08-11 | 2017-05-17 | 三星电子株式会社 | Semiconductor device |
| CN106711217A (en) * | 2015-11-16 | 2017-05-24 | 台湾积体电路制造股份有限公司 | Fin field effect transistor and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102637625A (en) * | 2011-02-11 | 2012-08-15 | 台湾积体电路制造股份有限公司 | End-to-end gap fill using dielectric film |
| US20140370697A1 (en) * | 2013-06-17 | 2014-12-18 | Globalfoundries Inc. | Removal of nitride bump in opening replacement gate structure |
| CN104733307A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN106684147A (en) * | 2015-08-11 | 2017-05-17 | 三星电子株式会社 | Semiconductor device |
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